arch/arm/mm/proc-v7m.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7m.S
   3  *
   4  *  Copyright (C) 2008 ARM Ltd.
   5  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv7-M processor support.
  12  */
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/v7m.h>
  16 #include "proc-macros.S"
  17
  18 ENTRY(cpu_v7m_proc_init)
  19         mov     pc, lr
  20 ENDPROC(cpu_v7m_proc_init)
  21
  22 ENTRY(cpu_v7m_proc_fin)
  23         mov     pc, lr
  24 ENDPROC(cpu_v7m_proc_fin)
  25
  26 /*
  27  *      cpu_v7m_reset(loc)
  28  *
  29  *      Perform a soft reset of the system.  Put the CPU into the
  30  *      same state as it would be if it had been reset, and branch
  31  *      to what would be the reset vector.
  32  *
  33  *      - loc   - location to jump to for soft reset
  34  */
  35         .align  5
  36 ENTRY(cpu_v7m_reset)
  37         mov     pc, r0
  38 ENDPROC(cpu_v7m_reset)
  39
  40 /*
  41  *      cpu_v7m_do_idle()
  42  *
  43  *      Idle the processor (eg, wait for interrupt).
  44  *
  45  *      IRQs are already disabled.
  46  */
  47 ENTRY(cpu_v7m_do_idle)
  48         wfi
  49         mov     pc, lr
  50 ENDPROC(cpu_v7m_do_idle)
  51
  52 ENTRY(cpu_v7m_dcache_clean_area)
  53         mov     pc, lr
  54 ENDPROC(cpu_v7m_dcache_clean_area)
  55
  56 /*
  57  * There is no MMU, so here is nothing to do.
  58  */
  59 ENTRY(cpu_v7m_switch_mm)
  60         mov     pc, lr
  61 ENDPROC(cpu_v7m_switch_mm)
  62
  63 .globl  cpu_v7m_suspend_size
  64 .equ    cpu_v7m_suspend_size, 0
  65
  66 #ifdef CONFIG_ARM_CPU_SUSPEND
  67 ENTRY(cpu_v7m_do_suspend)
  68         mov     pc, lr
  69 ENDPROC(cpu_v7m_do_suspend)
  70
  71 ENTRY(cpu_v7m_do_resume)
  72         mov     pc, lr
  73 ENDPROC(cpu_v7m_do_resume)
  74 #endif
  75
  76         .section ".text.init", #alloc, #execinstr
  77
  78 /*
  79  *      __v7m_setup
  80  *
  81  *      This should be able to cover all ARMv7-M cores.
  82  */
  83 __v7m_setup:
  84         @ Configure the vector table base address
  85         ldr     r0, =BASEADDR_V7M_SCB
  86         ldr     r12, =vector_table
  87         str     r12, [r0, V7M_SCB_VTOR]
  88
  89         @ enable UsageFault, BusFault and MemManage fault.
  90         ldr     r5, [r0, #V7M_SCB_SHCSR]
  91         orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
  92         str     r5, [r0, #V7M_SCB_SHCSR]
  93
  94         @ Lower the priority of the SVC and PendSV exceptions
  95         mov     r5, #0x80000000
  96         str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
  97         mov     r5, #0x00800000
  98         str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
  99
 100         @ SVC to run the kernel in this mode
 101         adr     r1, BSYM(1f)
 102         ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
 103         str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
 104         mov     r6, lr                  @ save LR
 105         mov     r7, sp                  @ save SP
 106         ldr     sp, =__v7m_setup_stack_top
 107         cpsie   i
 108         svc     #0
 109 1:      cpsid   i
 110         str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
 111         mov     lr, r6                  @ restore LR
 112         mov     sp, r7                  @ restore SP
 113
 114         @ Special-purpose control register
 115         mov     r1, #1
 116         msr     control, r1             @ Thread mode has unpriviledged access
 117
 118         @ Configure the System Control Register to ensure 8-byte stack alignment
 119         @ Note the STKALIGN bit is either RW or RAO.
 120         ldr     r12, [r0, V7M_SCB_CCR]  @ system control register
 121         orr     r12, #V7M_SCB_CCR_STKALIGN
 122         str     r12, [r0, V7M_SCB_CCR]
 123         mov     pc, lr
 124 ENDPROC(__v7m_setup)
 125
 126         define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
 127
 128         .section ".rodata"
 129         string cpu_arch_name, "armv7m"
 130         string cpu_elf_name "v7m"
 131         string cpu_v7m_name "ARMv7-M"
 132
 133         .section ".proc.info.init", #alloc, #execinstr
 134
 135         /*
 136          * Match any ARMv7-M processor core.
 137          */
 138         .type   __v7m_proc_info, #object
 139 __v7m_proc_info:
 140         .long   0x000f0000              @ Required ID value
 141         .long   0x000f0000              @ Mask for ID
 142         .long   0                       @ proc_info_list.__cpu_mm_mmu_flags
 143         .long   0                       @ proc_info_list.__cpu_io_mmu_flags
 144         b       __v7m_setup             @ proc_info_list.__cpu_flush
 145         .long   cpu_arch_name
 146         .long   cpu_elf_name
 147         .long   HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
 148         .long   cpu_v7m_name
 149         .long   v7m_processor_functions @ proc_info_list.proc
 150         .long   0                       @ proc_info_list.tlb
 151         .long   0                       @ proc_info_list.user
 152         .long   nop_cache_fns           @ proc_info_list.cache
 153         .size   __v7m_proc_info, . - __v7m_proc_info
 154
 155 __v7m_setup_stack:
 156         .space  4 * 8                           @ 8 registers
 157 __v7m_setup_stack_top: