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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / avr32 / mach-at32ap / at32ap700x.c
bloba68f3cf7c3c1bda0f3d02dc8d45672a4f3db0793
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/gpio.h>
17 #include <linux/spi/spi.h>
18 #include <linux/usb/atmel_usba_udc.h>
19
20 #include <mach/atmel-mci.h>
21 #include <linux/atmel-mci.h>
22
23 #include <asm/io.h>
24 #include <asm/irq.h>
25
26 #include <mach/at32ap700x.h>
27 #include <mach/board.h>
28 #include <mach/hmatrix.h>
29 #include <mach/portmux.h>
30 #include <mach/sram.h>
31
32 #include <sound/atmel-abdac.h>
33 #include <sound/atmel-ac97c.h>
34
35 #include <video/atmel_lcdc.h>
36
37 #include "clock.h"
38 #include "pio.h"
39 #include "pm.h"
40
41
42 #define PBMEM(base) \
43 { \
44 .start = base, \
45 .end = base + 0x3ff, \
46 .flags = IORESOURCE_MEM, \
47 }
48 #define IRQ(num) \
49 { \
50 .start = num, \
51 .end = num, \
52 .flags = IORESOURCE_IRQ, \
53 }
54 #define NAMED_IRQ(num, _name) \
55 { \
56 .start = num, \
57 .end = num, \
58 .name = _name, \
59 .flags = IORESOURCE_IRQ, \
60 }
61
62 /* REVISIT these assume *every* device supports DMA, but several
63 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
64 */
65 #define DEFINE_DEV(_name, _id) \
66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
67 static struct platform_device _name##_id##_device = { \
68 .name = #_name, \
69 .id = _id, \
70 .dev = { \
71 .dma_mask = &_name##_id##_dma_mask, \
72 .coherent_dma_mask = DMA_BIT_MASK(32), \
73 }, \
74 .resource = _name##_id##_resource, \
75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
76 }
77 #define DEFINE_DEV_DATA(_name, _id) \
78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
79 static struct platform_device _name##_id##_device = { \
80 .name = #_name, \
81 .id = _id, \
82 .dev = { \
83 .dma_mask = &_name##_id##_dma_mask, \
84 .platform_data = &_name##_id##_data, \
85 .coherent_dma_mask = DMA_BIT_MASK(32), \
86 }, \
87 .resource = _name##_id##_resource, \
88 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
89 }
90
91 #define select_peripheral(port, pin_mask, periph, flags) \
92 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
93 GPIO_##periph, flags)
94
95 #define DEV_CLK(_name, devname, bus, _index) \
96 static struct clk devname##_##_name = { \
97 .name = #_name, \
98 .dev = &devname##_device.dev, \
99 .parent = &bus##_clk, \
100 .mode = bus##_clk_mode, \
101 .get_rate = bus##_clk_get_rate, \
102 .index = _index, \
103 }
104
105 static DEFINE_SPINLOCK(pm_lock);
106
107 static struct clk osc0;
108 static struct clk osc1;
109
110 static unsigned long osc_get_rate(struct clk *clk)
111 {
112 return at32_board_osc_rates[clk->index];
113 }
114
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
116 {
117 unsigned long div, mul, rate;
118
119 div = PM_BFEXT(PLLDIV, control) + 1;
120 mul = PM_BFEXT(PLLMUL, control) + 1;
121
122 rate = clk->parent->get_rate(clk->parent);
123 rate = (rate + div / 2) / div;
124 rate *= mul;
125
126 return rate;
127 }
128
129 static long pll_set_rate(struct clk *clk, unsigned long rate,
130 u32 *pll_ctrl)
131 {
132 unsigned long mul;
133 unsigned long mul_best_fit = 0;
134 unsigned long div;
135 unsigned long div_min;
136 unsigned long div_max;
137 unsigned long div_best_fit = 0;
138 unsigned long base;
139 unsigned long pll_in;
140 unsigned long actual = 0;
141 unsigned long rate_error;
142 unsigned long rate_error_prev = ~0UL;
143 u32 ctrl;
144
145 /* Rate must be between 80 MHz and 200 Mhz. */
146 if (rate < 80000000UL || rate > 200000000UL)
147 return -EINVAL;
148
149 ctrl = PM_BF(PLLOPT, 4);
150 base = clk->parent->get_rate(clk->parent);
151
152 /* PLL input frequency must be between 6 MHz and 32 MHz. */
153 div_min = DIV_ROUND_UP(base, 32000000UL);
154 div_max = base / 6000000UL;
155
156 if (div_max < div_min)
157 return -EINVAL;
158
159 for (div = div_min; div <= div_max; div++) {
160 pll_in = (base + div / 2) / div;
161 mul = (rate + pll_in / 2) / pll_in;
162
163 if (mul == 0)
164 continue;
165
166 actual = pll_in * mul;
167 rate_error = abs(actual - rate);
168
169 if (rate_error < rate_error_prev) {
170 mul_best_fit = mul;
171 div_best_fit = div;
172 rate_error_prev = rate_error;
173 }
174
175 if (rate_error == 0)
176 break;
177 }
178
179 if (div_best_fit == 0)
180 return -EINVAL;
181
182 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
183 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
184 ctrl |= PM_BF(PLLCOUNT, 16);
185
186 if (clk->parent == &osc1)
187 ctrl |= PM_BIT(PLLOSC);
188
189 *pll_ctrl = ctrl;
190
191 return actual;
192 }
193
194 static unsigned long pll0_get_rate(struct clk *clk)
195 {
196 u32 control;
197
198 control = pm_readl(PLL0);
199
200 return pll_get_rate(clk, control);
201 }
202
203 static void pll1_mode(struct clk *clk, int enabled)
204 {
205 unsigned long timeout;
206 u32 status;
207 u32 ctrl;
208
209 ctrl = pm_readl(PLL1);
210
211 if (enabled) {
212 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
213 pr_debug("clk %s: failed to enable, rate not set\n",
214 clk->name);
215 return;
216 }
217
218 ctrl |= PM_BIT(PLLEN);
219 pm_writel(PLL1, ctrl);
220
221 /* Wait for PLL lock. */
222 for (timeout = 10000; timeout; timeout--) {
223 status = pm_readl(ISR);
224 if (status & PM_BIT(LOCK1))
225 break;
226 udelay(10);
227 }
228
229 if (!(status & PM_BIT(LOCK1)))
230 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
231 clk->name);
232 } else {
233 ctrl &= ~PM_BIT(PLLEN);
234 pm_writel(PLL1, ctrl);
235 }
236 }
237
238 static unsigned long pll1_get_rate(struct clk *clk)
239 {
240 u32 control;
241
242 control = pm_readl(PLL1);
243
244 return pll_get_rate(clk, control);
245 }
246
247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
248 {
249 u32 ctrl = 0;
250 unsigned long actual_rate;
251
252 actual_rate = pll_set_rate(clk, rate, &ctrl);
253
254 if (apply) {
255 if (actual_rate != rate)
256 return -EINVAL;
257 if (clk->users > 0)
258 return -EBUSY;
259 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
260 clk->name, rate, actual_rate);
261 pm_writel(PLL1, ctrl);
262 }
263
264 return actual_rate;
265 }
266
267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
268 {
269 u32 ctrl;
270
271 if (clk->users > 0)
272 return -EBUSY;
273
274 ctrl = pm_readl(PLL1);
275 WARN_ON(ctrl & PM_BIT(PLLEN));
276
277 if (parent == &osc0)
278 ctrl &= ~PM_BIT(PLLOSC);
279 else if (parent == &osc1)
280 ctrl |= PM_BIT(PLLOSC);
281 else
282 return -EINVAL;
283
284 pm_writel(PLL1, ctrl);
285 clk->parent = parent;
286
287 return 0;
288 }
289
290 /*
291 * The AT32AP7000 has five primary clock sources: One 32kHz
292 * oscillator, two crystal oscillators and two PLLs.
293 */
294 static struct clk osc32k = {
295 .name = "osc32k",
296 .get_rate = osc_get_rate,
297 .users = 1,
298 .index = 0,
299 };
300 static struct clk osc0 = {
301 .name = "osc0",
302 .get_rate = osc_get_rate,
303 .users = 1,
304 .index = 1,
305 };
306 static struct clk osc1 = {
307 .name = "osc1",
308 .get_rate = osc_get_rate,
309 .index = 2,
310 };
311 static struct clk pll0 = {
312 .name = "pll0",
313 .get_rate = pll0_get_rate,
314 .parent = &osc0,
315 };
316 static struct clk pll1 = {
317 .name = "pll1",
318 .mode = pll1_mode,
319 .get_rate = pll1_get_rate,
320 .set_rate = pll1_set_rate,
321 .set_parent = pll1_set_parent,
322 .parent = &osc0,
323 };
324
325 /*
326 * The main clock can be either osc0 or pll0. The boot loader may
327 * have chosen one for us, so we don't really know which one until we
328 * have a look at the SM.
329 */
330 static struct clk *main_clock;
331
332 /*
333 * Synchronous clocks are generated from the main clock. The clocks
334 * must satisfy the constraint
335 * fCPU >= fHSB >= fPB
336 * i.e. each clock must not be faster than its parent.
337 */
338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
339 {
340 return main_clock->get_rate(main_clock) >> shift;
341 };
342
343 static void cpu_clk_mode(struct clk *clk, int enabled)
344 {
345 unsigned long flags;
346 u32 mask;
347
348 spin_lock_irqsave(&pm_lock, flags);
349 mask = pm_readl(CPU_MASK);
350 if (enabled)
351 mask |= 1 << clk->index;
352 else
353 mask &= ~(1 << clk->index);
354 pm_writel(CPU_MASK, mask);
355 spin_unlock_irqrestore(&pm_lock, flags);
356 }
357
358 static unsigned long cpu_clk_get_rate(struct clk *clk)
359 {
360 unsigned long cksel, shift = 0;
361
362 cksel = pm_readl(CKSEL);
363 if (cksel & PM_BIT(CPUDIV))
364 shift = PM_BFEXT(CPUSEL, cksel) + 1;
365
366 return bus_clk_get_rate(clk, shift);
367 }
368
369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
370 {
371 u32 control;
372 unsigned long parent_rate, child_div, actual_rate, div;
373
374 parent_rate = clk->parent->get_rate(clk->parent);
375 control = pm_readl(CKSEL);
376
377 if (control & PM_BIT(HSBDIV))
378 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
379 else
380 child_div = 1;
381
382 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
383 actual_rate = parent_rate;
384 control &= ~PM_BIT(CPUDIV);
385 } else {
386 unsigned int cpusel;
387 div = (parent_rate + rate / 2) / rate;
388 if (div > child_div)
389 div = child_div;
390 cpusel = (div > 1) ? (fls(div) - 2) : 0;
391 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
392 actual_rate = parent_rate / (1 << (cpusel + 1));
393 }
394
395 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
396 clk->name, rate, actual_rate);
397
398 if (apply)
399 pm_writel(CKSEL, control);
400
401 return actual_rate;
402 }
403
404 static void hsb_clk_mode(struct clk *clk, int enabled)
405 {
406 unsigned long flags;
407 u32 mask;
408
409 spin_lock_irqsave(&pm_lock, flags);
410 mask = pm_readl(HSB_MASK);
411 if (enabled)
412 mask |= 1 << clk->index;
413 else
414 mask &= ~(1 << clk->index);
415 pm_writel(HSB_MASK, mask);
416 spin_unlock_irqrestore(&pm_lock, flags);
417 }
418
419 static unsigned long hsb_clk_get_rate(struct clk *clk)
420 {
421 unsigned long cksel, shift = 0;
422
423 cksel = pm_readl(CKSEL);
424 if (cksel & PM_BIT(HSBDIV))
425 shift = PM_BFEXT(HSBSEL, cksel) + 1;
426
427 return bus_clk_get_rate(clk, shift);
428 }
429
430 void pba_clk_mode(struct clk *clk, int enabled)
431 {
432 unsigned long flags;
433 u32 mask;
434
435 spin_lock_irqsave(&pm_lock, flags);
436 mask = pm_readl(PBA_MASK);
437 if (enabled)
438 mask |= 1 << clk->index;
439 else
440 mask &= ~(1 << clk->index);
441 pm_writel(PBA_MASK, mask);
442 spin_unlock_irqrestore(&pm_lock, flags);
443 }
444
445 unsigned long pba_clk_get_rate(struct clk *clk)
446 {
447 unsigned long cksel, shift = 0;
448
449 cksel = pm_readl(CKSEL);
450 if (cksel & PM_BIT(PBADIV))
451 shift = PM_BFEXT(PBASEL, cksel) + 1;
452
453 return bus_clk_get_rate(clk, shift);
454 }
455
456 static void pbb_clk_mode(struct clk *clk, int enabled)
457 {
458 unsigned long flags;
459 u32 mask;
460
461 spin_lock_irqsave(&pm_lock, flags);
462 mask = pm_readl(PBB_MASK);
463 if (enabled)
464 mask |= 1 << clk->index;
465 else
466 mask &= ~(1 << clk->index);
467 pm_writel(PBB_MASK, mask);
468 spin_unlock_irqrestore(&pm_lock, flags);
469 }
470
471 static unsigned long pbb_clk_get_rate(struct clk *clk)
472 {
473 unsigned long cksel, shift = 0;
474
475 cksel = pm_readl(CKSEL);
476 if (cksel & PM_BIT(PBBDIV))
477 shift = PM_BFEXT(PBBSEL, cksel) + 1;
478
479 return bus_clk_get_rate(clk, shift);
480 }
481
482 static struct clk cpu_clk = {
483 .name = "cpu",
484 .get_rate = cpu_clk_get_rate,
485 .set_rate = cpu_clk_set_rate,
486 .users = 1,
487 };
488 static struct clk hsb_clk = {
489 .name = "hsb",
490 .parent = &cpu_clk,
491 .get_rate = hsb_clk_get_rate,
492 };
493 static struct clk pba_clk = {
494 .name = "pba",
495 .parent = &hsb_clk,
496 .mode = hsb_clk_mode,
497 .get_rate = pba_clk_get_rate,
498 .index = 1,
499 };
500 static struct clk pbb_clk = {
501 .name = "pbb",
502 .parent = &hsb_clk,
503 .mode = hsb_clk_mode,
504 .get_rate = pbb_clk_get_rate,
505 .users = 1,
506 .index = 2,
507 };
508
509 /* --------------------------------------------------------------------
510 * Generic Clock operations
511 * -------------------------------------------------------------------- */
512
513 static void genclk_mode(struct clk *clk, int enabled)
514 {
515 u32 control;
516
517 control = pm_readl(GCCTRL(clk->index));
518 if (enabled)
519 control |= PM_BIT(CEN);
520 else
521 control &= ~PM_BIT(CEN);
522 pm_writel(GCCTRL(clk->index), control);
523 }
524
525 static unsigned long genclk_get_rate(struct clk *clk)
526 {
527 u32 control;
528 unsigned long div = 1;
529
530 control = pm_readl(GCCTRL(clk->index));
531 if (control & PM_BIT(DIVEN))
532 div = 2 * (PM_BFEXT(DIV, control) + 1);
533
534 return clk->parent->get_rate(clk->parent) / div;
535 }
536
537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
538 {
539 u32 control;
540 unsigned long parent_rate, actual_rate, div;
541
542 parent_rate = clk->parent->get_rate(clk->parent);
543 control = pm_readl(GCCTRL(clk->index));
544
545 if (rate > 3 * parent_rate / 4) {
546 actual_rate = parent_rate;
547 control &= ~PM_BIT(DIVEN);
548 } else {
549 div = (parent_rate + rate) / (2 * rate) - 1;
550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
551 actual_rate = parent_rate / (2 * (div + 1));
552 }
553
554 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
555 clk->name, rate, actual_rate);
556
557 if (apply)
558 pm_writel(GCCTRL(clk->index), control);
559
560 return actual_rate;
561 }
562
563 int genclk_set_parent(struct clk *clk, struct clk *parent)
564 {
565 u32 control;
566
567 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
568 clk->name, parent->name, clk->parent->name);
569
570 control = pm_readl(GCCTRL(clk->index));
571
572 if (parent == &osc1 || parent == &pll1)
573 control |= PM_BIT(OSCSEL);
574 else if (parent == &osc0 || parent == &pll0)
575 control &= ~PM_BIT(OSCSEL);
576 else
577 return -EINVAL;
578
579 if (parent == &pll0 || parent == &pll1)
580 control |= PM_BIT(PLLSEL);
581 else
582 control &= ~PM_BIT(PLLSEL);
583
584 pm_writel(GCCTRL(clk->index), control);
585 clk->parent = parent;
586
587 return 0;
588 }
589
590 static void __init genclk_init_parent(struct clk *clk)
591 {
592 u32 control;
593 struct clk *parent;
594
595 BUG_ON(clk->index > 7);
596
597 control = pm_readl(GCCTRL(clk->index));
598 if (control & PM_BIT(OSCSEL))
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
600 else
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
602
603 clk->parent = parent;
604 }
605
606 static struct dw_dma_platform_data dw_dmac0_data = {
607 .nr_channels = 3,
608 .block_size = 4095U,
609 .nr_masters = 2,
610 .data_width = { 2, 2, 0, 0 },
611 };
612
613 static struct resource dw_dmac0_resource[] = {
614 PBMEM(0xff200000),
615 IRQ(2),
616 };
617 DEFINE_DEV_DATA(dw_dmac, 0);
618 DEV_CLK(hclk, dw_dmac0, hsb, 10);
619
620 /* --------------------------------------------------------------------
621 * System peripherals
622 * -------------------------------------------------------------------- */
623 static struct resource at32_pm0_resource[] = {
624 {
625 .start = 0xfff00000,
626 .end = 0xfff0007f,
627 .flags = IORESOURCE_MEM,
628 },
629 IRQ(20),
630 };
631
632 static struct resource at32ap700x_rtc0_resource[] = {
633 {
634 .start = 0xfff00080,
635 .end = 0xfff000af,
636 .flags = IORESOURCE_MEM,
637 },
638 IRQ(21),
639 };
640
641 static struct resource at32_wdt0_resource[] = {
642 {
643 .start = 0xfff000b0,
644 .end = 0xfff000cf,
645 .flags = IORESOURCE_MEM,
646 },
647 };
648
649 static struct resource at32_eic0_resource[] = {
650 {
651 .start = 0xfff00100,
652 .end = 0xfff0013f,
653 .flags = IORESOURCE_MEM,
654 },
655 IRQ(19),
656 };
657
658 DEFINE_DEV(at32_pm, 0);
659 DEFINE_DEV(at32ap700x_rtc, 0);
660 DEFINE_DEV(at32_wdt, 0);
661 DEFINE_DEV(at32_eic, 0);
662
663 /*
664 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
665 * is always running.
666 */
667 static struct clk at32_pm_pclk = {
668 .name = "pclk",
669 .dev = &at32_pm0_device.dev,
670 .parent = &pbb_clk,
671 .mode = pbb_clk_mode,
672 .get_rate = pbb_clk_get_rate,
673 .users = 1,
674 .index = 0,
675 };
676
677 static struct resource intc0_resource[] = {
678 PBMEM(0xfff00400),
679 };
680 struct platform_device at32_intc0_device = {
681 .name = "intc",
682 .id = 0,
683 .resource = intc0_resource,
684 .num_resources = ARRAY_SIZE(intc0_resource),
685 };
686 DEV_CLK(pclk, at32_intc0, pbb, 1);
687
688 static struct clk ebi_clk = {
689 .name = "ebi",
690 .parent = &hsb_clk,
691 .mode = hsb_clk_mode,
692 .get_rate = hsb_clk_get_rate,
693 .users = 1,
694 };
695 static struct clk hramc_clk = {
696 .name = "hramc",
697 .parent = &hsb_clk,
698 .mode = hsb_clk_mode,
699 .get_rate = hsb_clk_get_rate,
700 .users = 1,
701 .index = 3,
702 };
703 static struct clk sdramc_clk = {
704 .name = "sdramc_clk",
705 .parent = &pbb_clk,
706 .mode = pbb_clk_mode,
707 .get_rate = pbb_clk_get_rate,
708 .users = 1,
709 .index = 14,
710 };
711
712 static struct resource smc0_resource[] = {
713 PBMEM(0xfff03400),
714 };
715 DEFINE_DEV(smc, 0);
716 DEV_CLK(pclk, smc0, pbb, 13);
717 DEV_CLK(mck, smc0, hsb, 0);
718
719 static struct platform_device pdc_device = {
720 .name = "pdc",
721 .id = 0,
722 };
723 DEV_CLK(hclk, pdc, hsb, 4);
724 DEV_CLK(pclk, pdc, pba, 16);
725
726 static struct clk pico_clk = {
727 .name = "pico",
728 .parent = &cpu_clk,
729 .mode = cpu_clk_mode,
730 .get_rate = cpu_clk_get_rate,
731 .users = 1,
732 };
733
734 /* --------------------------------------------------------------------
735 * HMATRIX
736 * -------------------------------------------------------------------- */
737
738 struct clk at32_hmatrix_clk = {
739 .name = "hmatrix_clk",
740 .parent = &pbb_clk,
741 .mode = pbb_clk_mode,
742 .get_rate = pbb_clk_get_rate,
743 .index = 2,
744 .users = 1,
745 };
746
747 /*
748 * Set bits in the HMATRIX Special Function Register (SFR) used by the
749 * External Bus Interface (EBI). This can be used to enable special
750 * features like CompactFlash support, NAND Flash support, etc. on
751 * certain chipselects.
752 */
753 static inline void set_ebi_sfr_bits(u32 mask)
754 {
755 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
756 }
757
758 /* --------------------------------------------------------------------
759 * Timer/Counter (TC)
760 * -------------------------------------------------------------------- */
761
762 static struct resource at32_tcb0_resource[] = {
763 PBMEM(0xfff00c00),
764 IRQ(22),
765 };
766 static struct platform_device at32_tcb0_device = {
767 .name = "atmel_tcb",
768 .id = 0,
769 .resource = at32_tcb0_resource,
770 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
771 };
772 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
773
774 static struct resource at32_tcb1_resource[] = {
775 PBMEM(0xfff01000),
776 IRQ(23),
777 };
778 static struct platform_device at32_tcb1_device = {
779 .name = "atmel_tcb",
780 .id = 1,
781 .resource = at32_tcb1_resource,
782 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
783 };
784 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
785
786 /* --------------------------------------------------------------------
787 * PIO
788 * -------------------------------------------------------------------- */
789
790 static struct resource pio0_resource[] = {
791 PBMEM(0xffe02800),
792 IRQ(13),
793 };
794 DEFINE_DEV(pio, 0);
795 DEV_CLK(mck, pio0, pba, 10);
796
797 static struct resource pio1_resource[] = {
798 PBMEM(0xffe02c00),
799 IRQ(14),
800 };
801 DEFINE_DEV(pio, 1);
802 DEV_CLK(mck, pio1, pba, 11);
803
804 static struct resource pio2_resource[] = {
805 PBMEM(0xffe03000),
806 IRQ(15),
807 };
808 DEFINE_DEV(pio, 2);
809 DEV_CLK(mck, pio2, pba, 12);
810
811 static struct resource pio3_resource[] = {
812 PBMEM(0xffe03400),
813 IRQ(16),
814 };
815 DEFINE_DEV(pio, 3);
816 DEV_CLK(mck, pio3, pba, 13);
817
818 static struct resource pio4_resource[] = {
819 PBMEM(0xffe03800),
820 IRQ(17),
821 };
822 DEFINE_DEV(pio, 4);
823 DEV_CLK(mck, pio4, pba, 14);
824
825 static int __init system_device_init(void)
826 {
827 platform_device_register(&at32_pm0_device);
828 platform_device_register(&at32_intc0_device);
829 platform_device_register(&at32ap700x_rtc0_device);
830 platform_device_register(&at32_wdt0_device);
831 platform_device_register(&at32_eic0_device);
832 platform_device_register(&smc0_device);
833 platform_device_register(&pdc_device);
834 platform_device_register(&dw_dmac0_device);
835
836 platform_device_register(&at32_tcb0_device);
837 platform_device_register(&at32_tcb1_device);
838
839 platform_device_register(&pio0_device);
840 platform_device_register(&pio1_device);
841 platform_device_register(&pio2_device);
842 platform_device_register(&pio3_device);
843 platform_device_register(&pio4_device);
844
845 return 0;
846 }
847 core_initcall(system_device_init);
848
849 /* --------------------------------------------------------------------
850 * PSIF
851 * -------------------------------------------------------------------- */
852 static struct resource atmel_psif0_resource[] __initdata = {
853 {
854 .start = 0xffe03c00,
855 .end = 0xffe03cff,
856 .flags = IORESOURCE_MEM,
857 },
858 IRQ(18),
859 };
860 static struct clk atmel_psif0_pclk = {
861 .name = "pclk",
862 .parent = &pba_clk,
863 .mode = pba_clk_mode,
864 .get_rate = pba_clk_get_rate,
865 .index = 15,
866 };
867
868 static struct resource atmel_psif1_resource[] __initdata = {
869 {
870 .start = 0xffe03d00,
871 .end = 0xffe03dff,
872 .flags = IORESOURCE_MEM,
873 },
874 IRQ(18),
875 };
876 static struct clk atmel_psif1_pclk = {
877 .name = "pclk",
878 .parent = &pba_clk,
879 .mode = pba_clk_mode,
880 .get_rate = pba_clk_get_rate,
881 .index = 15,
882 };
883
884 struct platform_device *__init at32_add_device_psif(unsigned int id)
885 {
886 struct platform_device *pdev;
887 u32 pin_mask;
888
889 if (!(id == 0 || id == 1))
890 return NULL;
891
892 pdev = platform_device_alloc("atmel_psif", id);
893 if (!pdev)
894 return NULL;
895
896 switch (id) {
897 case 0:
898 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
899
900 if (platform_device_add_resources(pdev, atmel_psif0_resource,
901 ARRAY_SIZE(atmel_psif0_resource)))
902 goto err_add_resources;
903 atmel_psif0_pclk.dev = &pdev->dev;
904 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
905 break;
906 case 1:
907 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
908
909 if (platform_device_add_resources(pdev, atmel_psif1_resource,
910 ARRAY_SIZE(atmel_psif1_resource)))
911 goto err_add_resources;
912 atmel_psif1_pclk.dev = &pdev->dev;
913 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
914 break;
915 default:
916 return NULL;
917 }
918
919 platform_device_add(pdev);
920 return pdev;
921
922 err_add_resources:
923 platform_device_put(pdev);
924 return NULL;
925 }
926
927 /* --------------------------------------------------------------------
928 * USART
929 * -------------------------------------------------------------------- */
930
931 static struct atmel_uart_data atmel_usart0_data = {
932 .use_dma_tx = 1,
933 .use_dma_rx = 1,
934 };
935 static struct resource atmel_usart0_resource[] = {
936 PBMEM(0xffe00c00),
937 IRQ(6),
938 };
939 DEFINE_DEV_DATA(atmel_usart, 0);
940 DEV_CLK(usart, atmel_usart0, pba, 3);
941
942 static struct atmel_uart_data atmel_usart1_data = {
943 .use_dma_tx = 1,
944 .use_dma_rx = 1,
945 };
946 static struct resource atmel_usart1_resource[] = {
947 PBMEM(0xffe01000),
948 IRQ(7),
949 };
950 DEFINE_DEV_DATA(atmel_usart, 1);
951 DEV_CLK(usart, atmel_usart1, pba, 4);
952
953 static struct atmel_uart_data atmel_usart2_data = {
954 .use_dma_tx = 1,
955 .use_dma_rx = 1,
956 };
957 static struct resource atmel_usart2_resource[] = {
958 PBMEM(0xffe01400),
959 IRQ(8),
960 };
961 DEFINE_DEV_DATA(atmel_usart, 2);
962 DEV_CLK(usart, atmel_usart2, pba, 5);
963
964 static struct atmel_uart_data atmel_usart3_data = {
965 .use_dma_tx = 1,
966 .use_dma_rx = 1,
967 };
968 static struct resource atmel_usart3_resource[] = {
969 PBMEM(0xffe01800),
970 IRQ(9),
971 };
972 DEFINE_DEV_DATA(atmel_usart, 3);
973 DEV_CLK(usart, atmel_usart3, pba, 6);
974
975 static inline void configure_usart0_pins(int flags)
976 {
977 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
978 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
979 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
980 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
981
982 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
983 }
984
985 static inline void configure_usart1_pins(int flags)
986 {
987 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
988 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
989 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
990 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
991
992 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
993 }
994
995 static inline void configure_usart2_pins(int flags)
996 {
997 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
998 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
999 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
1000 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
1001
1002 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1003 }
1004
1005 static inline void configure_usart3_pins(int flags)
1006 {
1007 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1008 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1009 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1010 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1011
1012 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1013 }
1014
1015 static struct platform_device *__initdata at32_usarts[4];
1016
1017 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1018 {
1019 struct platform_device *pdev;
1020 struct atmel_uart_data *pdata;
1021
1022 switch (hw_id) {
1023 case 0:
1024 pdev = &atmel_usart0_device;
1025 configure_usart0_pins(flags);
1026 break;
1027 case 1:
1028 pdev = &atmel_usart1_device;
1029 configure_usart1_pins(flags);
1030 break;
1031 case 2:
1032 pdev = &atmel_usart2_device;
1033 configure_usart2_pins(flags);
1034 break;
1035 case 3:
1036 pdev = &atmel_usart3_device;
1037 configure_usart3_pins(flags);
1038 break;
1039 default:
1040 return;
1041 }
1042
1043 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1044 /* Addresses in the P4 segment are permanently mapped 1:1 */
1045 struct atmel_uart_data *data = pdev->dev.platform_data;
1046 data->regs = (void __iomem *)pdev->resource[0].start;
1047 }
1048
1049 pdev->id = line;
1050 pdata = pdev->dev.platform_data;
1051 pdata->num = line;
1052 at32_usarts[line] = pdev;
1053 }
1054
1055 struct platform_device *__init at32_add_device_usart(unsigned int id)
1056 {
1057 platform_device_register(at32_usarts[id]);
1058 return at32_usarts[id];
1059 }
1060
1061 void __init at32_setup_serial_console(unsigned int usart_id)
1062 {
1063 #ifdef CONFIG_SERIAL_ATMEL
1064 atmel_default_console_device = at32_usarts[usart_id];
1065 #endif
1066 }
1067
1068 /* --------------------------------------------------------------------
1069 * Ethernet
1070 * -------------------------------------------------------------------- */
1071
1072 #ifdef CONFIG_CPU_AT32AP7000
1073 static struct macb_platform_data macb0_data;
1074 static struct resource macb0_resource[] = {
1075 PBMEM(0xfff01800),
1076 IRQ(25),
1077 };
1078 DEFINE_DEV_DATA(macb, 0);
1079 DEV_CLK(hclk, macb0, hsb, 8);
1080 DEV_CLK(pclk, macb0, pbb, 6);
1081
1082 static struct macb_platform_data macb1_data;
1083 static struct resource macb1_resource[] = {
1084 PBMEM(0xfff01c00),
1085 IRQ(26),
1086 };
1087 DEFINE_DEV_DATA(macb, 1);
1088 DEV_CLK(hclk, macb1, hsb, 9);
1089 DEV_CLK(pclk, macb1, pbb, 7);
1090
1091 struct platform_device *__init
1092 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1093 {
1094 struct platform_device *pdev;
1095 u32 pin_mask;
1096
1097 switch (id) {
1098 case 0:
1099 pdev = &macb0_device;
1100
1101 pin_mask = (1 << 3); /* TXD0 */
1102 pin_mask |= (1 << 4); /* TXD1 */
1103 pin_mask |= (1 << 7); /* TXEN */
1104 pin_mask |= (1 << 8); /* TXCK */
1105 pin_mask |= (1 << 9); /* RXD0 */
1106 pin_mask |= (1 << 10); /* RXD1 */
1107 pin_mask |= (1 << 13); /* RXER */
1108 pin_mask |= (1 << 15); /* RXDV */
1109 pin_mask |= (1 << 16); /* MDC */
1110 pin_mask |= (1 << 17); /* MDIO */
1111
1112 if (!data->is_rmii) {
1113 pin_mask |= (1 << 0); /* COL */
1114 pin_mask |= (1 << 1); /* CRS */
1115 pin_mask |= (1 << 2); /* TXER */
1116 pin_mask |= (1 << 5); /* TXD2 */
1117 pin_mask |= (1 << 6); /* TXD3 */
1118 pin_mask |= (1 << 11); /* RXD2 */
1119 pin_mask |= (1 << 12); /* RXD3 */
1120 pin_mask |= (1 << 14); /* RXCK */
1121 #ifndef CONFIG_BOARD_MIMC200
1122 pin_mask |= (1 << 18); /* SPD */
1123 #endif
1124 }
1125
1126 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1127
1128 break;
1129
1130 case 1:
1131 pdev = &macb1_device;
1132
1133 pin_mask = (1 << 13); /* TXD0 */
1134 pin_mask |= (1 << 14); /* TXD1 */
1135 pin_mask |= (1 << 11); /* TXEN */
1136 pin_mask |= (1 << 12); /* TXCK */
1137 pin_mask |= (1 << 10); /* RXD0 */
1138 pin_mask |= (1 << 6); /* RXD1 */
1139 pin_mask |= (1 << 5); /* RXER */
1140 pin_mask |= (1 << 4); /* RXDV */
1141 pin_mask |= (1 << 3); /* MDC */
1142 pin_mask |= (1 << 2); /* MDIO */
1143
1144 #ifndef CONFIG_BOARD_MIMC200
1145 if (!data->is_rmii)
1146 pin_mask |= (1 << 15); /* SPD */
1147 #endif
1148
1149 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1150
1151 if (!data->is_rmii) {
1152 pin_mask = (1 << 19); /* COL */
1153 pin_mask |= (1 << 23); /* CRS */
1154 pin_mask |= (1 << 26); /* TXER */
1155 pin_mask |= (1 << 27); /* TXD2 */
1156 pin_mask |= (1 << 28); /* TXD3 */
1157 pin_mask |= (1 << 29); /* RXD2 */
1158 pin_mask |= (1 << 30); /* RXD3 */
1159 pin_mask |= (1 << 24); /* RXCK */
1160
1161 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1162 }
1163 break;
1164
1165 default:
1166 return NULL;
1167 }
1168
1169 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1170 platform_device_register(pdev);
1171
1172 return pdev;
1173 }
1174 #endif
1175
1176 /* --------------------------------------------------------------------
1177 * SPI
1178 * -------------------------------------------------------------------- */
1179 static struct resource atmel_spi0_resource[] = {
1180 PBMEM(0xffe00000),
1181 IRQ(3),
1182 };
1183 DEFINE_DEV(atmel_spi, 0);
1184 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1185
1186 static struct resource atmel_spi1_resource[] = {
1187 PBMEM(0xffe00400),
1188 IRQ(4),
1189 };
1190 DEFINE_DEV(atmel_spi, 1);
1191 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1192
1193 void __init
1194 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1195 {
1196 /*
1197 * Manage the chipselects as GPIOs, normally using the same pins
1198 * the SPI controller expects; but boards can use other pins.
1199 */
1200 static u8 __initdata spi_pins[][4] = {
1201 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1202 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1203 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1204 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1205 };
1206 unsigned int pin, mode;
1207
1208 /* There are only 2 SPI controllers */
1209 if (bus_num > 1)
1210 return;
1211
1212 for (; n; n--, b++) {
1213 b->bus_num = bus_num;
1214 if (b->chip_select >= 4)
1215 continue;
1216 pin = (unsigned)b->controller_data;
1217 if (!pin) {
1218 pin = spi_pins[bus_num][b->chip_select];
1219 b->controller_data = (void *)pin;
1220 }
1221 mode = AT32_GPIOF_OUTPUT;
1222 if (!(b->mode & SPI_CS_HIGH))
1223 mode |= AT32_GPIOF_HIGH;
1224 at32_select_gpio(pin, mode);
1225 }
1226 }
1227
1228 struct platform_device *__init
1229 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1230 {
1231 struct platform_device *pdev;
1232 u32 pin_mask;
1233
1234 switch (id) {
1235 case 0:
1236 pdev = &atmel_spi0_device;
1237 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1238
1239 /* pullup MISO so a level is always defined */
1240 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1241 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1242
1243 at32_spi_setup_slaves(0, b, n);
1244 break;
1245
1246 case 1:
1247 pdev = &atmel_spi1_device;
1248 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1249
1250 /* pullup MISO so a level is always defined */
1251 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1252 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1253
1254 at32_spi_setup_slaves(1, b, n);
1255 break;
1256
1257 default:
1258 return NULL;
1259 }
1260
1261 spi_register_board_info(b, n);
1262 platform_device_register(pdev);
1263 return pdev;
1264 }
1265
1266 /* --------------------------------------------------------------------
1267 * TWI
1268 * -------------------------------------------------------------------- */
1269 static struct resource atmel_twi0_resource[] __initdata = {
1270 PBMEM(0xffe00800),
1271 IRQ(5),
1272 };
1273 static struct clk atmel_twi0_pclk = {
1274 .name = "twi_pclk",
1275 .parent = &pba_clk,
1276 .mode = pba_clk_mode,
1277 .get_rate = pba_clk_get_rate,
1278 .index = 2,
1279 };
1280
1281 struct platform_device *__init at32_add_device_twi(unsigned int id,
1282 struct i2c_board_info *b,
1283 unsigned int n)
1284 {
1285 struct platform_device *pdev;
1286 u32 pin_mask;
1287
1288 if (id != 0)
1289 return NULL;
1290
1291 pdev = platform_device_alloc("atmel_twi", id);
1292 if (!pdev)
1293 return NULL;
1294
1295 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1296 ARRAY_SIZE(atmel_twi0_resource)))
1297 goto err_add_resources;
1298
1299 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1300
1301 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1302
1303 atmel_twi0_pclk.dev = &pdev->dev;
1304
1305 if (b)
1306 i2c_register_board_info(id, b, n);
1307
1308 platform_device_add(pdev);
1309 return pdev;
1310
1311 err_add_resources:
1312 platform_device_put(pdev);
1313 return NULL;
1314 }
1315
1316 /* --------------------------------------------------------------------
1317 * MMC
1318 * -------------------------------------------------------------------- */
1319 static struct resource atmel_mci0_resource[] __initdata = {
1320 PBMEM(0xfff02400),
1321 IRQ(28),
1322 };
1323 static struct clk atmel_mci0_pclk = {
1324 .name = "mci_clk",
1325 .parent = &pbb_clk,
1326 .mode = pbb_clk_mode,
1327 .get_rate = pbb_clk_get_rate,
1328 .index = 9,
1329 };
1330
1331 struct platform_device *__init
1332 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1333 {
1334 struct platform_device *pdev;
1335 struct mci_dma_data *slave;
1336 u32 pioa_mask;
1337 u32 piob_mask;
1338
1339 if (id != 0 || !data)
1340 return NULL;
1341
1342 /* Must have at least one usable slot */
1343 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1344 return NULL;
1345
1346 pdev = platform_device_alloc("atmel_mci", id);
1347 if (!pdev)
1348 goto fail;
1349
1350 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1351 ARRAY_SIZE(atmel_mci0_resource)))
1352 goto fail;
1353
1354 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1355 if (!slave)
1356 goto fail;
1357
1358 slave->sdata.dma_dev = &dw_dmac0_device.dev;
1359 slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1360 | DWC_CFGH_DST_PER(1));
1361 slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1362 | DWC_CFGL_HS_SRC_POL);
1363
1364 data->dma_slave = slave;
1365
1366 if (platform_device_add_data(pdev, data,
1367 sizeof(struct mci_platform_data)))
1368 goto fail_free;
1369
1370 /* CLK line is common to both slots */
1371 pioa_mask = 1 << 10;
1372
1373 switch (data->slot[0].bus_width) {
1374 case 4:
1375 pioa_mask |= 1 << 13; /* DATA1 */
1376 pioa_mask |= 1 << 14; /* DATA2 */
1377 pioa_mask |= 1 << 15; /* DATA3 */
1378 /* fall through */
1379 case 1:
1380 pioa_mask |= 1 << 11; /* CMD */
1381 pioa_mask |= 1 << 12; /* DATA0 */
1382
1383 if (gpio_is_valid(data->slot[0].detect_pin))
1384 at32_select_gpio(data->slot[0].detect_pin, 0);
1385 if (gpio_is_valid(data->slot[0].wp_pin))
1386 at32_select_gpio(data->slot[0].wp_pin, 0);
1387 break;
1388 case 0:
1389 /* Slot is unused */
1390 break;
1391 default:
1392 goto fail_free;
1393 }
1394
1395 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1396 piob_mask = 0;
1397
1398 switch (data->slot[1].bus_width) {
1399 case 4:
1400 piob_mask |= 1 << 8; /* DATA1 */
1401 piob_mask |= 1 << 9; /* DATA2 */
1402 piob_mask |= 1 << 10; /* DATA3 */
1403 /* fall through */
1404 case 1:
1405 piob_mask |= 1 << 6; /* CMD */
1406 piob_mask |= 1 << 7; /* DATA0 */
1407 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1408
1409 if (gpio_is_valid(data->slot[1].detect_pin))
1410 at32_select_gpio(data->slot[1].detect_pin, 0);
1411 if (gpio_is_valid(data->slot[1].wp_pin))
1412 at32_select_gpio(data->slot[1].wp_pin, 0);
1413 break;
1414 case 0:
1415 /* Slot is unused */
1416 break;
1417 default:
1418 if (!data->slot[0].bus_width)
1419 goto fail_free;
1420
1421 data->slot[1].bus_width = 0;
1422 break;
1423 }
1424
1425 atmel_mci0_pclk.dev = &pdev->dev;
1426
1427 platform_device_add(pdev);
1428 return pdev;
1429
1430 fail_free:
1431 kfree(slave);
1432 fail:
1433 data->dma_slave = NULL;
1434 platform_device_put(pdev);
1435 return NULL;
1436 }
1437
1438 /* --------------------------------------------------------------------
1439 * LCDC
1440 * -------------------------------------------------------------------- */
1441 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1442 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1443 static struct resource atmel_lcdfb0_resource[] = {
1444 {
1445 .start = 0xff000000,
1446 .end = 0xff000fff,
1447 .flags = IORESOURCE_MEM,
1448 },
1449 IRQ(1),
1450 {
1451 /* Placeholder for pre-allocated fb memory */
1452 .start = 0x00000000,
1453 .end = 0x00000000,
1454 .flags = 0,
1455 },
1456 };
1457 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1458 DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
1459 static struct clk atmel_lcdfb0_pixclk = {
1460 .name = "lcdc_clk",
1461 .dev = &atmel_lcdfb0_device.dev,
1462 .mode = genclk_mode,
1463 .get_rate = genclk_get_rate,
1464 .set_rate = genclk_set_rate,
1465 .set_parent = genclk_set_parent,
1466 .index = 7,
1467 };
1468
1469 struct platform_device *__init
1470 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1471 unsigned long fbmem_start, unsigned long fbmem_len,
1472 u64 pin_mask)
1473 {
1474 struct platform_device *pdev;
1475 struct atmel_lcdfb_info *info;
1476 struct fb_monspecs *monspecs;
1477 struct fb_videomode *modedb;
1478 unsigned int modedb_size;
1479 u32 portc_mask, portd_mask, porte_mask;
1480
1481 /*
1482 * Do a deep copy of the fb data, monspecs and modedb. Make
1483 * sure all allocations are done before setting up the
1484 * portmux.
1485 */
1486 monspecs = kmemdup(data->default_monspecs,
1487 sizeof(struct fb_monspecs), GFP_KERNEL);
1488 if (!monspecs)
1489 return NULL;
1490
1491 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1492 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1493 if (!modedb)
1494 goto err_dup_modedb;
1495 monspecs->modedb = modedb;
1496
1497 switch (id) {
1498 case 0:
1499 pdev = &atmel_lcdfb0_device;
1500
1501 if (pin_mask == 0ULL)
1502 /* Default to "full" lcdc control signals and 24bit */
1503 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1504
1505 /* LCDC on port C */
1506 portc_mask = pin_mask & 0xfff80000;
1507 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1508
1509 /* LCDC on port D */
1510 portd_mask = pin_mask & 0x0003ffff;
1511 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1512
1513 /* LCDC on port E */
1514 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1515 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1516
1517 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1518 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1519 break;
1520
1521 default:
1522 goto err_invalid_id;
1523 }
1524
1525 if (fbmem_len) {
1526 pdev->resource[2].start = fbmem_start;
1527 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1528 pdev->resource[2].flags = IORESOURCE_MEM;
1529 }
1530
1531 info = pdev->dev.platform_data;
1532 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1533 info->default_monspecs = monspecs;
1534
1535 pdev->name = "at32ap-lcdfb";
1536
1537 platform_device_register(pdev);
1538 return pdev;
1539
1540 err_invalid_id:
1541 kfree(modedb);
1542 err_dup_modedb:
1543 kfree(monspecs);
1544 return NULL;
1545 }
1546 #endif
1547
1548 /* --------------------------------------------------------------------
1549 * PWM
1550 * -------------------------------------------------------------------- */
1551 static struct resource atmel_pwm0_resource[] __initdata = {
1552 PBMEM(0xfff01400),
1553 IRQ(24),
1554 };
1555 static struct clk atmel_pwm0_mck = {
1556 .name = "pwm_clk",
1557 .parent = &pbb_clk,
1558 .mode = pbb_clk_mode,
1559 .get_rate = pbb_clk_get_rate,
1560 .index = 5,
1561 };
1562
1563 struct platform_device *__init at32_add_device_pwm(u32 mask)
1564 {
1565 struct platform_device *pdev;
1566 u32 pin_mask;
1567
1568 if (!mask)
1569 return NULL;
1570
1571 pdev = platform_device_alloc("atmel_pwm", 0);
1572 if (!pdev)
1573 return NULL;
1574
1575 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1576 ARRAY_SIZE(atmel_pwm0_resource)))
1577 goto out_free_pdev;
1578
1579 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1580 goto out_free_pdev;
1581
1582 pin_mask = 0;
1583 if (mask & (1 << 0))
1584 pin_mask |= (1 << 28);
1585 if (mask & (1 << 1))
1586 pin_mask |= (1 << 29);
1587 if (pin_mask > 0)
1588 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1589
1590 pin_mask = 0;
1591 if (mask & (1 << 2))
1592 pin_mask |= (1 << 21);
1593 if (mask & (1 << 3))
1594 pin_mask |= (1 << 22);
1595 if (pin_mask > 0)
1596 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1597
1598 atmel_pwm0_mck.dev = &pdev->dev;
1599
1600 platform_device_add(pdev);
1601
1602 return pdev;
1603
1604 out_free_pdev:
1605 platform_device_put(pdev);
1606 return NULL;
1607 }
1608
1609 /* --------------------------------------------------------------------
1610 * SSC
1611 * -------------------------------------------------------------------- */
1612 static struct resource ssc0_resource[] = {
1613 PBMEM(0xffe01c00),
1614 IRQ(10),
1615 };
1616 DEFINE_DEV(ssc, 0);
1617 DEV_CLK(pclk, ssc0, pba, 7);
1618
1619 static struct resource ssc1_resource[] = {
1620 PBMEM(0xffe02000),
1621 IRQ(11),
1622 };
1623 DEFINE_DEV(ssc, 1);
1624 DEV_CLK(pclk, ssc1, pba, 8);
1625
1626 static struct resource ssc2_resource[] = {
1627 PBMEM(0xffe02400),
1628 IRQ(12),
1629 };
1630 DEFINE_DEV(ssc, 2);
1631 DEV_CLK(pclk, ssc2, pba, 9);
1632
1633 struct platform_device *__init
1634 at32_add_device_ssc(unsigned int id, unsigned int flags)
1635 {
1636 struct platform_device *pdev;
1637 u32 pin_mask = 0;
1638
1639 switch (id) {
1640 case 0:
1641 pdev = &ssc0_device;
1642 if (flags & ATMEL_SSC_RF)
1643 pin_mask |= (1 << 21); /* RF */
1644 if (flags & ATMEL_SSC_RK)
1645 pin_mask |= (1 << 22); /* RK */
1646 if (flags & ATMEL_SSC_TK)
1647 pin_mask |= (1 << 23); /* TK */
1648 if (flags & ATMEL_SSC_TF)
1649 pin_mask |= (1 << 24); /* TF */
1650 if (flags & ATMEL_SSC_TD)
1651 pin_mask |= (1 << 25); /* TD */
1652 if (flags & ATMEL_SSC_RD)
1653 pin_mask |= (1 << 26); /* RD */
1654
1655 if (pin_mask > 0)
1656 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1657
1658 break;
1659 case 1:
1660 pdev = &ssc1_device;
1661 if (flags & ATMEL_SSC_RF)
1662 pin_mask |= (1 << 0); /* RF */
1663 if (flags & ATMEL_SSC_RK)
1664 pin_mask |= (1 << 1); /* RK */
1665 if (flags & ATMEL_SSC_TK)
1666 pin_mask |= (1 << 2); /* TK */
1667 if (flags & ATMEL_SSC_TF)
1668 pin_mask |= (1 << 3); /* TF */
1669 if (flags & ATMEL_SSC_TD)
1670 pin_mask |= (1 << 4); /* TD */
1671 if (flags & ATMEL_SSC_RD)
1672 pin_mask |= (1 << 5); /* RD */
1673
1674 if (pin_mask > 0)
1675 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1676
1677 break;
1678 case 2:
1679 pdev = &ssc2_device;
1680 if (flags & ATMEL_SSC_TD)
1681 pin_mask |= (1 << 13); /* TD */
1682 if (flags & ATMEL_SSC_RD)
1683 pin_mask |= (1 << 14); /* RD */
1684 if (flags & ATMEL_SSC_TK)
1685 pin_mask |= (1 << 15); /* TK */
1686 if (flags & ATMEL_SSC_TF)
1687 pin_mask |= (1 << 16); /* TF */
1688 if (flags & ATMEL_SSC_RF)
1689 pin_mask |= (1 << 17); /* RF */
1690 if (flags & ATMEL_SSC_RK)
1691 pin_mask |= (1 << 18); /* RK */
1692
1693 if (pin_mask > 0)
1694 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1695
1696 break;
1697 default:
1698 return NULL;
1699 }
1700
1701 platform_device_register(pdev);
1702 return pdev;
1703 }
1704
1705 /* --------------------------------------------------------------------
1706 * USB Device Controller
1707 * -------------------------------------------------------------------- */
1708 static struct resource usba0_resource[] __initdata = {
1709 {
1710 .start = 0xff300000,
1711 .end = 0xff3fffff,
1712 .flags = IORESOURCE_MEM,
1713 }, {
1714 .start = 0xfff03000,
1715 .end = 0xfff033ff,
1716 .flags = IORESOURCE_MEM,
1717 },
1718 IRQ(31),
1719 };
1720 static struct clk usba0_pclk = {
1721 .name = "pclk",
1722 .parent = &pbb_clk,
1723 .mode = pbb_clk_mode,
1724 .get_rate = pbb_clk_get_rate,
1725 .index = 12,
1726 };
1727 static struct clk usba0_hclk = {
1728 .name = "hclk",
1729 .parent = &hsb_clk,
1730 .mode = hsb_clk_mode,
1731 .get_rate = hsb_clk_get_rate,
1732 .index = 6,
1733 };
1734
1735 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1736 [idx] = { \
1737 .name = nam, \
1738 .index = idx, \
1739 .fifo_size = maxpkt, \
1740 .nr_banks = maxbk, \
1741 .can_dma = dma, \
1742 .can_isoc = isoc, \
1743 }
1744
1745 static struct usba_ep_data at32_usba_ep[] __initdata = {
1746 EP("ep0", 0, 64, 1, 0, 0),
1747 EP("ep1", 1, 512, 2, 1, 1),
1748 EP("ep2", 2, 512, 2, 1, 1),
1749 EP("ep3-int", 3, 64, 3, 1, 0),
1750 EP("ep4-int", 4, 64, 3, 1, 0),
1751 EP("ep5", 5, 1024, 3, 1, 1),
1752 EP("ep6", 6, 1024, 3, 1, 1),
1753 };
1754
1755 #undef EP
1756
1757 struct platform_device *__init
1758 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1759 {
1760 /*
1761 * pdata doesn't have room for any endpoints, so we need to
1762 * append room for the ones we need right after it.
1763 */
1764 struct {
1765 struct usba_platform_data pdata;
1766 struct usba_ep_data ep[7];
1767 } usba_data;
1768 struct platform_device *pdev;
1769
1770 if (id != 0)
1771 return NULL;
1772
1773 pdev = platform_device_alloc("atmel_usba_udc", 0);
1774 if (!pdev)
1775 return NULL;
1776
1777 if (platform_device_add_resources(pdev, usba0_resource,
1778 ARRAY_SIZE(usba0_resource)))
1779 goto out_free_pdev;
1780
1781 if (data) {
1782 usba_data.pdata.vbus_pin = data->vbus_pin;
1783 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1784 } else {
1785 usba_data.pdata.vbus_pin = -EINVAL;
1786 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1787 }
1788
1789 data = &usba_data.pdata;
1790 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1791 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1792
1793 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1794 goto out_free_pdev;
1795
1796 if (gpio_is_valid(data->vbus_pin))
1797 at32_select_gpio(data->vbus_pin, 0);
1798
1799 usba0_pclk.dev = &pdev->dev;
1800 usba0_hclk.dev = &pdev->dev;
1801
1802 platform_device_add(pdev);
1803
1804 return pdev;
1805
1806 out_free_pdev:
1807 platform_device_put(pdev);
1808 return NULL;
1809 }
1810
1811 /* --------------------------------------------------------------------
1812 * IDE / CompactFlash
1813 * -------------------------------------------------------------------- */
1814 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1815 static struct resource at32_smc_cs4_resource[] __initdata = {
1816 {
1817 .start = 0x04000000,
1818 .end = 0x07ffffff,
1819 .flags = IORESOURCE_MEM,
1820 },
1821 IRQ(~0UL), /* Magic IRQ will be overridden */
1822 };
1823 static struct resource at32_smc_cs5_resource[] __initdata = {
1824 {
1825 .start = 0x20000000,
1826 .end = 0x23ffffff,
1827 .flags = IORESOURCE_MEM,
1828 },
1829 IRQ(~0UL), /* Magic IRQ will be overridden */
1830 };
1831
1832 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1833 unsigned int cs, unsigned int extint)
1834 {
1835 static unsigned int extint_pin_map[4] __initdata = {
1836 (1 << 25),
1837 (1 << 26),
1838 (1 << 27),
1839 (1 << 28),
1840 };
1841 static bool common_pins_initialized __initdata = false;
1842 unsigned int extint_pin;
1843 int ret;
1844 u32 pin_mask;
1845
1846 if (extint >= ARRAY_SIZE(extint_pin_map))
1847 return -EINVAL;
1848 extint_pin = extint_pin_map[extint];
1849
1850 switch (cs) {
1851 case 4:
1852 ret = platform_device_add_resources(pdev,
1853 at32_smc_cs4_resource,
1854 ARRAY_SIZE(at32_smc_cs4_resource));
1855 if (ret)
1856 return ret;
1857
1858 /* NCS4 -> OE_N */
1859 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1860 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1861 break;
1862 case 5:
1863 ret = platform_device_add_resources(pdev,
1864 at32_smc_cs5_resource,
1865 ARRAY_SIZE(at32_smc_cs5_resource));
1866 if (ret)
1867 return ret;
1868
1869 /* NCS5 -> OE_N */
1870 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1871 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1872 break;
1873 default:
1874 return -EINVAL;
1875 }
1876
1877 if (!common_pins_initialized) {
1878 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1879 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1880 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1881 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1882
1883 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1884
1885 common_pins_initialized = true;
1886 }
1887
1888 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1889
1890 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1891 pdev->resource[1].end = pdev->resource[1].start;
1892
1893 return 0;
1894 }
1895
1896 struct platform_device *__init
1897 at32_add_device_ide(unsigned int id, unsigned int extint,
1898 struct ide_platform_data *data)
1899 {
1900 struct platform_device *pdev;
1901
1902 pdev = platform_device_alloc("at32_ide", id);
1903 if (!pdev)
1904 goto fail;
1905
1906 if (platform_device_add_data(pdev, data,
1907 sizeof(struct ide_platform_data)))
1908 goto fail;
1909
1910 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1911 goto fail;
1912
1913 platform_device_add(pdev);
1914 return pdev;
1915
1916 fail:
1917 platform_device_put(pdev);
1918 return NULL;
1919 }
1920
1921 struct platform_device *__init
1922 at32_add_device_cf(unsigned int id, unsigned int extint,
1923 struct cf_platform_data *data)
1924 {
1925 struct platform_device *pdev;
1926
1927 pdev = platform_device_alloc("at32_cf", id);
1928 if (!pdev)
1929 goto fail;
1930
1931 if (platform_device_add_data(pdev, data,
1932 sizeof(struct cf_platform_data)))
1933 goto fail;
1934
1935 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1936 goto fail;
1937
1938 if (gpio_is_valid(data->detect_pin))
1939 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1940 if (gpio_is_valid(data->reset_pin))
1941 at32_select_gpio(data->reset_pin, 0);
1942 if (gpio_is_valid(data->vcc_pin))
1943 at32_select_gpio(data->vcc_pin, 0);
1944 /* READY is used as extint, so we can't select it as gpio */
1945
1946 platform_device_add(pdev);
1947 return pdev;
1948
1949 fail:
1950 platform_device_put(pdev);
1951 return NULL;
1952 }
1953 #endif
1954
1955 /* --------------------------------------------------------------------
1956 * NAND Flash / SmartMedia
1957 * -------------------------------------------------------------------- */
1958 static struct resource smc_cs3_resource[] __initdata = {
1959 {
1960 .start = 0x0c000000,
1961 .end = 0x0fffffff,
1962 .flags = IORESOURCE_MEM,
1963 }, {
1964 .start = 0xfff03c00,
1965 .end = 0xfff03fff,
1966 .flags = IORESOURCE_MEM,
1967 },
1968 };
1969
1970 struct platform_device *__init
1971 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1972 {
1973 struct platform_device *pdev;
1974
1975 if (id != 0 || !data)
1976 return NULL;
1977
1978 pdev = platform_device_alloc("atmel_nand", id);
1979 if (!pdev)
1980 goto fail;
1981
1982 if (platform_device_add_resources(pdev, smc_cs3_resource,
1983 ARRAY_SIZE(smc_cs3_resource)))
1984 goto fail;
1985
1986 /* For at32ap7000, we use the reset workaround for nand driver */
1987 data->need_reset_workaround = true;
1988
1989 if (platform_device_add_data(pdev, data,
1990 sizeof(struct atmel_nand_data)))
1991 goto fail;
1992
1993 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1994 if (data->enable_pin)
1995 at32_select_gpio(data->enable_pin,
1996 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1997 if (data->rdy_pin)
1998 at32_select_gpio(data->rdy_pin, 0);
1999 if (data->det_pin)
2000 at32_select_gpio(data->det_pin, 0);
2001
2002 platform_device_add(pdev);
2003 return pdev;
2004
2005 fail:
2006 platform_device_put(pdev);
2007 return NULL;
2008 }
2009
2010 /* --------------------------------------------------------------------
2011 * AC97C
2012 * -------------------------------------------------------------------- */
2013 static struct resource atmel_ac97c0_resource[] __initdata = {
2014 PBMEM(0xfff02800),
2015 IRQ(29),
2016 };
2017 static struct clk atmel_ac97c0_pclk = {
2018 .name = "pclk",
2019 .parent = &pbb_clk,
2020 .mode = pbb_clk_mode,
2021 .get_rate = pbb_clk_get_rate,
2022 .index = 10,
2023 };
2024
2025 struct platform_device *__init
2026 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2027 unsigned int flags)
2028 {
2029 struct platform_device *pdev;
2030 struct dw_dma_slave *rx_dws;
2031 struct dw_dma_slave *tx_dws;
2032 struct ac97c_platform_data _data;
2033 u32 pin_mask;
2034
2035 if (id != 0)
2036 return NULL;
2037
2038 pdev = platform_device_alloc("atmel_ac97c", id);
2039 if (!pdev)
2040 return NULL;
2041
2042 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2043 ARRAY_SIZE(atmel_ac97c0_resource)))
2044 goto out_free_resources;
2045
2046 if (!data) {
2047 data = &_data;
2048 memset(data, 0, sizeof(struct ac97c_platform_data));
2049 data->reset_pin = -ENODEV;
2050 }
2051
2052 rx_dws = &data->rx_dws;
2053 tx_dws = &data->tx_dws;
2054
2055 /* Check if DMA slave interface for capture should be configured. */
2056 if (flags & AC97C_CAPTURE) {
2057 rx_dws->dma_dev = &dw_dmac0_device.dev;
2058 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2059 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2060 rx_dws->src_master = 0;
2061 rx_dws->dst_master = 1;
2062 }
2063
2064 /* Check if DMA slave interface for playback should be configured. */
2065 if (flags & AC97C_PLAYBACK) {
2066 tx_dws->dma_dev = &dw_dmac0_device.dev;
2067 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2068 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2069 tx_dws->src_master = 0;
2070 tx_dws->dst_master = 1;
2071 }
2072
2073 if (platform_device_add_data(pdev, data,
2074 sizeof(struct ac97c_platform_data)))
2075 goto out_free_resources;
2076
2077 /* SDO | SYNC | SCLK | SDI */
2078 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2079
2080 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2081
2082 if (gpio_is_valid(data->reset_pin))
2083 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2084 | AT32_GPIOF_HIGH);
2085
2086 atmel_ac97c0_pclk.dev = &pdev->dev;
2087
2088 platform_device_add(pdev);
2089 return pdev;
2090
2091 out_free_resources:
2092 platform_device_put(pdev);
2093 return NULL;
2094 }
2095
2096 /* --------------------------------------------------------------------
2097 * ABDAC
2098 * -------------------------------------------------------------------- */
2099 static struct resource abdac0_resource[] __initdata = {
2100 PBMEM(0xfff02000),
2101 IRQ(27),
2102 };
2103 static struct clk abdac0_pclk = {
2104 .name = "pclk",
2105 .parent = &pbb_clk,
2106 .mode = pbb_clk_mode,
2107 .get_rate = pbb_clk_get_rate,
2108 .index = 8,
2109 };
2110 static struct clk abdac0_sample_clk = {
2111 .name = "sample_clk",
2112 .mode = genclk_mode,
2113 .get_rate = genclk_get_rate,
2114 .set_rate = genclk_set_rate,
2115 .set_parent = genclk_set_parent,
2116 .index = 6,
2117 };
2118
2119 struct platform_device *__init
2120 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2121 {
2122 struct platform_device *pdev;
2123 struct dw_dma_slave *dws;
2124 u32 pin_mask;
2125
2126 if (id != 0 || !data)
2127 return NULL;
2128
2129 pdev = platform_device_alloc("atmel_abdac", id);
2130 if (!pdev)
2131 return NULL;
2132
2133 if (platform_device_add_resources(pdev, abdac0_resource,
2134 ARRAY_SIZE(abdac0_resource)))
2135 goto out_free_resources;
2136
2137 dws = &data->dws;
2138
2139 dws->dma_dev = &dw_dmac0_device.dev;
2140 dws->cfg_hi = DWC_CFGH_DST_PER(2);
2141 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2142 dws->src_master = 0;
2143 dws->dst_master = 1;
2144
2145 if (platform_device_add_data(pdev, data,
2146 sizeof(struct atmel_abdac_pdata)))
2147 goto out_free_resources;
2148
2149 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2150 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2151
2152 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2153
2154 abdac0_pclk.dev = &pdev->dev;
2155 abdac0_sample_clk.dev = &pdev->dev;
2156
2157 platform_device_add(pdev);
2158 return pdev;
2159
2160 out_free_resources:
2161 platform_device_put(pdev);
2162 return NULL;
2163 }
2164
2165 /* --------------------------------------------------------------------
2166 * GCLK
2167 * -------------------------------------------------------------------- */
2168 static struct clk gclk0 = {
2169 .name = "gclk0",
2170 .mode = genclk_mode,
2171 .get_rate = genclk_get_rate,
2172 .set_rate = genclk_set_rate,
2173 .set_parent = genclk_set_parent,
2174 .index = 0,
2175 };
2176 static struct clk gclk1 = {
2177 .name = "gclk1",
2178 .mode = genclk_mode,
2179 .get_rate = genclk_get_rate,
2180 .set_rate = genclk_set_rate,
2181 .set_parent = genclk_set_parent,
2182 .index = 1,
2183 };
2184 static struct clk gclk2 = {
2185 .name = "gclk2",
2186 .mode = genclk_mode,
2187 .get_rate = genclk_get_rate,
2188 .set_rate = genclk_set_rate,
2189 .set_parent = genclk_set_parent,
2190 .index = 2,
2191 };
2192 static struct clk gclk3 = {
2193 .name = "gclk3",
2194 .mode = genclk_mode,
2195 .get_rate = genclk_get_rate,
2196 .set_rate = genclk_set_rate,
2197 .set_parent = genclk_set_parent,
2198 .index = 3,
2199 };
2200 static struct clk gclk4 = {
2201 .name = "gclk4",
2202 .mode = genclk_mode,
2203 .get_rate = genclk_get_rate,
2204 .set_rate = genclk_set_rate,
2205 .set_parent = genclk_set_parent,
2206 .index = 4,
2207 };
2208
2209 static __initdata struct clk *init_clocks[] = {
2210 &osc32k,
2211 &osc0,
2212 &osc1,
2213 &pll0,
2214 &pll1,
2215 &cpu_clk,
2216 &hsb_clk,
2217 &pba_clk,
2218 &pbb_clk,
2219 &at32_pm_pclk,
2220 &at32_intc0_pclk,
2221 &at32_hmatrix_clk,
2222 &ebi_clk,
2223 &hramc_clk,
2224 &sdramc_clk,
2225 &smc0_pclk,
2226 &smc0_mck,
2227 &pdc_hclk,
2228 &pdc_pclk,
2229 &dw_dmac0_hclk,
2230 &pico_clk,
2231 &pio0_mck,
2232 &pio1_mck,
2233 &pio2_mck,
2234 &pio3_mck,
2235 &pio4_mck,
2236 &at32_tcb0_t0_clk,
2237 &at32_tcb1_t0_clk,
2238 &atmel_psif0_pclk,
2239 &atmel_psif1_pclk,
2240 &atmel_usart0_usart,
2241 &atmel_usart1_usart,
2242 &atmel_usart2_usart,
2243 &atmel_usart3_usart,
2244 &atmel_pwm0_mck,
2245 #if defined(CONFIG_CPU_AT32AP7000)
2246 &macb0_hclk,
2247 &macb0_pclk,
2248 &macb1_hclk,
2249 &macb1_pclk,
2250 #endif
2251 &atmel_spi0_spi_clk,
2252 &atmel_spi1_spi_clk,
2253 &atmel_twi0_pclk,
2254 &atmel_mci0_pclk,
2255 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2256 &atmel_lcdfb0_hclk,
2257 &atmel_lcdfb0_pixclk,
2258 #endif
2259 &ssc0_pclk,
2260 &ssc1_pclk,
2261 &ssc2_pclk,
2262 &usba0_hclk,
2263 &usba0_pclk,
2264 &atmel_ac97c0_pclk,
2265 &abdac0_pclk,
2266 &abdac0_sample_clk,
2267 &gclk0,
2268 &gclk1,
2269 &gclk2,
2270 &gclk3,
2271 &gclk4,
2272 };
2273
2274 void __init setup_platform(void)
2275 {
2276 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2277 int i;
2278
2279 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2280 main_clock = &pll0;
2281 cpu_clk.parent = &pll0;
2282 } else {
2283 main_clock = &osc0;
2284 cpu_clk.parent = &osc0;
2285 }
2286
2287 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2288 pll0.parent = &osc1;
2289 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2290 pll1.parent = &osc1;
2291
2292 genclk_init_parent(&gclk0);
2293 genclk_init_parent(&gclk1);
2294 genclk_init_parent(&gclk2);
2295 genclk_init_parent(&gclk3);
2296 genclk_init_parent(&gclk4);
2297 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2298 genclk_init_parent(&atmel_lcdfb0_pixclk);
2299 #endif
2300 genclk_init_parent(&abdac0_sample_clk);
2301
2302 /*
2303 * Build initial dynamic clock list by registering all clocks
2304 * from the array.
2305 * At the same time, turn on all clocks that have at least one
2306 * user already, and turn off everything else. We only do this
2307 * for module clocks, and even though it isn't particularly
2308 * pretty to check the address of the mode function, it should
2309 * do the trick...
2310 */
2311 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2312 struct clk *clk = init_clocks[i];
2313
2314 /* first, register clock */
2315 at32_clk_register(clk);
2316
2317 if (clk->users == 0)
2318 continue;
2319
2320 if (clk->mode == &cpu_clk_mode)
2321 cpu_mask |= 1 << clk->index;
2322 else if (clk->mode == &hsb_clk_mode)
2323 hsb_mask |= 1 << clk->index;
2324 else if (clk->mode == &pba_clk_mode)
2325 pba_mask |= 1 << clk->index;
2326 else if (clk->mode == &pbb_clk_mode)
2327 pbb_mask |= 1 << clk->index;
2328 }
2329
2330 pm_writel(CPU_MASK, cpu_mask);
2331 pm_writel(HSB_MASK, hsb_mask);
2332 pm_writel(PBA_MASK, pba_mask);
2333 pm_writel(PBB_MASK, pbb_mask);
2334
2335 /* Initialize the port muxes */
2336 at32_init_pio(&pio0_device);
2337 at32_init_pio(&pio1_device);
2338 at32_init_pio(&pio2_device);
2339 at32_init_pio(&pio3_device);
2340 at32_init_pio(&pio4_device);
2341 }
2342
2343 struct gen_pool *sram_pool;
2344
2345 static int __init sram_init(void)
2346 {
2347 struct gen_pool *pool;
2348
2349 /* 1KiB granularity */
2350 pool = gen_pool_create(10, -1);
2351 if (!pool)
2352 goto fail;
2353
2354 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2355 goto err_pool_add;
2356
2357 sram_pool = pool;
2358 return 0;
2359
2360 err_pool_add:
2361 gen_pool_destroy(pool);
2362 fail:
2363 pr_err("Failed to create SRAM pool\n");
2364 return -ENOMEM;
2365 }
2366 core_initcall(sram_init);
Linux with added FPC-III support