1 /* pci-vdk.c: MB93090-MB00 (VDK) PCI support
3 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/delay.h>
20 #include <asm/segment.h>
22 #include <asm/mb-regs.h>
23 #include <asm/mb86943a.h>
26 unsigned int __nongpreldata pci_probe
= 1;
28 int __nongpreldata pcibios_last_bus
= -1;
29 struct pci_ops
*__nongpreldata pci_root_ops
;
32 * The accessible PCI window does not cover the entire CPU address space, but
33 * there are devices we want to access outside of that window, so we need to
34 * insert specific PCI bus resources instead of using the platform-level bus
35 * resources directly for the PCI root bus.
37 * These are configured and inserted by pcibios_init() and are attached to the
38 * root bus by pcibios_fixup_bus().
40 static struct resource pci_ioport_resource
= {
43 .end
= IO_SPACE_LIMIT
,
44 .flags
= IORESOURCE_IO
,
47 static struct resource pci_iomem_resource
= {
51 .flags
= IORESOURCE_MEM
,
55 * Functions for accessing PCI configuration space
58 #define CONFIG_CMD(bus, dev, where) \
59 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
61 #define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
63 #define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
64 #define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
65 #define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
67 #define __set_PciCfgDataB(A,V) \
68 writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
70 #define __set_PciCfgDataW(A,V) \
71 writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
73 #define __set_PciCfgDataL(A,V) \
74 writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
76 #define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
77 #define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
78 #define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
80 #define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
81 #define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
82 #define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
84 static inline int __query(const struct pci_dev
*dev
)
86 // return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
87 // return dev->bus->number==1;
88 // return dev->bus->number==0 &&
89 // (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
93 /*****************************************************************************/
97 static int pci_frv_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
,
102 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
103 _value
= __get_PciBridgeDataL(where
& ~3);
106 __set_PciCfgAddr(CONFIG_CMD(bus
, devfn
, where
));
107 _value
= __get_PciCfgDataL(where
& ~3);
112 _value
= _value
>> ((where
& 3) * 8);
116 _value
= _value
>> ((where
& 2) * 8);
127 return PCIBIOS_SUCCESSFUL
;
130 static int pci_frv_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
,
135 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
136 __set_PciBridgeDataB(where
, value
);
139 __set_PciCfgAddr(CONFIG_CMD(bus
, devfn
, where
));
140 __set_PciCfgDataB(where
, value
);
145 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
146 __set_PciBridgeDataW(where
, value
);
149 __set_PciCfgAddr(CONFIG_CMD(bus
, devfn
, where
));
150 __set_PciCfgDataW(where
, value
);
155 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
156 __set_PciBridgeDataL(where
, value
);
159 __set_PciCfgAddr(CONFIG_CMD(bus
, devfn
, where
));
160 __set_PciCfgDataL(where
, value
);
168 return PCIBIOS_SUCCESSFUL
;
171 static struct pci_ops pci_direct_frv
= {
173 pci_frv_write_config
,
177 * Before we decide to use direct hardware access mechanisms, we try to do some
178 * trivial checks to ensure it at least _seems_ to be working -- we just test
179 * whether bus 00 contains a host bridge (this is similar to checking
180 * techniques used in XFree86, but ours should be more reliable since we
181 * attempt to make use of direct access hints provided by the PCI BIOS).
183 * This should be close to trivial, but it isn't, because there are buggy
184 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
186 static int __init
pci_sanity_check(struct pci_ops
*o
)
188 struct pci_bus bus
; /* Fake bus and device */
193 if (o
->read(&bus
, 0, PCI_VENDOR_ID
, 4, &id
) == PCIBIOS_SUCCESSFUL
) {
194 printk("PCI: VDK Bridge device:vendor: %08x\n", id
);
195 if (id
== 0x200e10cf)
199 printk("PCI: VDK Bridge: Sanity check failed\n");
203 static struct pci_ops
* __init
pci_check_direct(void)
207 local_irq_save(flags
);
209 /* check if access works */
210 if (pci_sanity_check(&pci_direct_frv
)) {
211 local_irq_restore(flags
);
212 printk("PCI: Using configuration frv\n");
213 // request_mem_region(0xBE040000, 256, "FRV bridge");
214 // request_mem_region(0xBFFFFFF4, 12, "PCI frv");
215 return &pci_direct_frv
;
218 local_irq_restore(flags
);
223 * Discover remaining PCI buses in case there are peer host bridges.
224 * We use the number of last PCI bus provided by the PCI BIOS.
226 static void __init
pcibios_fixup_peer_bridges(void)
233 if (pcibios_last_bus
<= 0 || pcibios_last_bus
>= 0xff)
235 printk("PCI: Peer bridge fixup\n");
236 for (n
=0; n
<= pcibios_last_bus
; n
++) {
237 if (pci_find_bus(0, n
))
240 bus
.ops
= pci_root_ops
;
242 for(dev
.devfn
=0; dev
.devfn
<256; dev
.devfn
+= 8)
243 if (!pci_read_config_word(&dev
, PCI_VENDOR_ID
, &l
) &&
244 l
!= 0x0000 && l
!= 0xffff) {
245 printk("Found device at %02x:%02x [%04x]\n", n
, dev
.devfn
, l
);
246 printk("PCI: Discovered peer bus %02x\n", n
);
247 pci_scan_bus(n
, pci_root_ops
, NULL
);
254 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
257 static void __init
pci_fixup_umc_ide(struct pci_dev
*d
)
260 * UM8886BF IDE controller sets region type bits incorrectly,
261 * therefore they look like memory despite of them being I/O.
265 printk("PCI: Fixing base address flags for device %s\n", pci_name(d
));
267 d
->resource
[i
].flags
|= PCI_BASE_ADDRESS_SPACE_IO
;
270 static void pci_fixup_ide_bases(struct pci_dev
*d
)
275 * PCI IDE controllers use non-standard I/O port decoding, respect it.
277 if ((d
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
279 printk("PCI: IDE base address fixup for %s\n", pci_name(d
));
281 struct resource
*r
= &d
->resource
[i
];
282 if ((r
->start
& ~0x80) == 0x374) {
289 static void pci_fixup_ide_trash(struct pci_dev
*d
)
294 * There exist PCI IDE controllers which have utter garbage
295 * in first four base registers. Ignore that.
297 printk("PCI: IDE base address trash cleared for %s\n", pci_name(d
));
299 d
->resource
[i
].start
= d
->resource
[i
].end
= d
->resource
[i
].flags
= 0;
302 static void pci_fixup_latency(struct pci_dev
*d
)
305 * SiS 5597 and 5598 chipsets require latency timer set to
306 * at most 32 to avoid lockups.
308 DBG("PCI: Setting max latency to 32\n");
309 pcibios_max_latency
= 32;
312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC
, PCI_DEVICE_ID_UMC_UM8886BF
, pci_fixup_umc_ide
);
313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5513
, pci_fixup_ide_trash
);
314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, pci_fixup_latency
);
315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5598
, pci_fixup_latency
);
316 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pci_fixup_ide_bases
);
319 * Called after each bus is probed, but before its children
323 void pcibios_fixup_bus(struct pci_bus
*bus
)
326 printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus
->number
);
329 pci_read_bridge_bases(bus
);
331 if (bus
->number
== 0) {
333 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
334 if (dev
->devfn
== 0) {
335 dev
->resource
[0].start
= 0;
336 dev
->resource
[0].end
= 0;
343 * Initialization. Try all known PCI access methods. Note that we support
344 * using both PCI BIOS and direct access: in such cases, we use I/O ports
345 * to access config space, but we still keep BIOS order of cards to be
346 * compatible with 2.0.X. This should go away some day.
349 int __init
pcibios_init(void)
351 struct pci_ops
*dir
= NULL
;
352 LIST_HEAD(resources
);
354 if (!mb93090_mb00_detected
)
357 __reg_MB86943_sl_ctl
|= MB86943_SL_CTL_DRCT_MASTER_SWAP
| MB86943_SL_CTL_DRCT_SLAVE_SWAP
;
359 __reg_MB86943_ecs_base(1) = ((__region_CS2
+ 0x01000000) >> 9) | 0x08000000;
360 __reg_MB86943_ecs_base(2) = ((__region_CS2
+ 0x00000000) >> 9) | 0x08000000;
362 *(volatile uint32_t *) (__region_CS1
+ 0x848) = 0xe0000000;
363 *(volatile uint32_t *) (__region_CS1
+ 0x8b8) = 0x00000000;
365 __reg_MB86943_sl_pci_io_base
= (__region_CS2
+ 0x04000000) >> 9;
366 __reg_MB86943_sl_pci_mem_base
= (__region_CS2
+ 0x08000000) >> 9;
367 __reg_MB86943_pci_sl_io_base
= __region_CS2
+ 0x04000000;
368 __reg_MB86943_pci_sl_mem_base
= __region_CS2
+ 0x08000000;
371 /* enable PCI arbitration */
372 __reg_MB86943_pci_arbiter
= MB86943_PCIARB_EN
;
374 pci_ioport_resource
.start
= (__reg_MB86943_sl_pci_io_base
<< 9) & 0xfffffc00;
375 pci_ioport_resource
.end
= (__reg_MB86943_sl_pci_io_range
<< 9) | 0x3ff;
376 pci_ioport_resource
.end
+= pci_ioport_resource
.start
;
378 printk("PCI IO window: %08llx-%08llx\n",
379 (unsigned long long) pci_ioport_resource
.start
,
380 (unsigned long long) pci_ioport_resource
.end
);
382 pci_iomem_resource
.start
= (__reg_MB86943_sl_pci_mem_base
<< 9) & 0xfffffc00;
383 pci_iomem_resource
.end
= (__reg_MB86943_sl_pci_mem_range
<< 9) | 0x3ff;
384 pci_iomem_resource
.end
+= pci_iomem_resource
.start
;
386 /* Reserve somewhere to write to flush posted writes. This is used by
387 * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
388 * CPU-PCI bridge to flush as this doesn't happen automatically when a
389 * read is performed on the MB93090 development kit motherboard.
391 pci_iomem_resource
.start
+= 0x400;
393 printk("PCI MEM window: %08llx-%08llx\n",
394 (unsigned long long) pci_iomem_resource
.start
,
395 (unsigned long long) pci_iomem_resource
.end
);
396 printk("PCI DMA memory: %08lx-%08lx\n",
397 dma_coherent_mem_start
, dma_coherent_mem_end
);
399 if (insert_resource(&iomem_resource
, &pci_iomem_resource
) < 0)
400 panic("Unable to insert PCI IOMEM resource\n");
401 if (insert_resource(&ioport_resource
, &pci_ioport_resource
) < 0)
402 panic("Unable to insert PCI IOPORT resource\n");
407 dir
= pci_check_direct();
411 printk("PCI: No PCI bus detected\n");
415 printk("PCI: Probing PCI hardware\n");
416 pci_add_resource(&resources
, &pci_ioport_resource
);
417 pci_add_resource(&resources
, &pci_iomem_resource
);
418 pci_scan_root_bus(NULL
, 0, pci_root_ops
, NULL
, &resources
);
421 pcibios_fixup_peer_bridges();
422 pcibios_fixup_irqs();
423 pcibios_resource_survey();
428 arch_initcall(pcibios_init
);
430 char * __init
pcibios_setup(char *str
)
432 if (!strcmp(str
, "off")) {
435 } else if (!strncmp(str
, "lastbus=", 8)) {
436 pcibios_last_bus
= simple_strtol(str
+8, NULL
, 0);
442 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
446 if ((err
= pci_enable_resources(dev
, mask
)) < 0)
448 if (!dev
->msi_enabled
)
449 pcibios_enable_irq(dev
);