x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / mips / fw / arc / promlib.c
blob7e8ba5ce95be0778c958d2772a2015e0450aaf85
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1996 David S. Miller (dm@sgi.com)
7 * Compatibility with board caches, Ulf Carlsson
8 */
9 #include <linux/kernel.h>
10 #include <asm/sgialib.h>
11 #include <asm/bcache.h>
14 * IP22 boardcache is not compatible with board caches. Thus we disable it
15 * during romvec action. Since r4xx0.c is always compiled and linked with your
16 * kernel, this shouldn't cause any harm regardless what MIPS processor you
17 * have.
19 * The ARC write and read functions seem to interfere with the serial lines
20 * in some way. You should be careful with them.
23 void prom_putchar(char c)
25 ULONG cnt;
26 CHAR it = c;
28 bc_disable();
29 ArcWrite(1, &it, 1, &cnt);
30 bc_enable();
33 char prom_getchar(void)
35 ULONG cnt;
36 CHAR c;
38 bc_disable();
39 ArcRead(0, &c, 1, &cnt);
40 bc_enable();
42 return c;