2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/context_tracking.h>
17 #include <linux/kexec.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/spinlock.h>
25 #include <linux/kallsyms.h>
26 #include <linux/bootmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/ptrace.h>
29 #include <linux/kgdb.h>
30 #include <linux/kdebug.h>
31 #include <linux/kprobes.h>
32 #include <linux/notifier.h>
33 #include <linux/kdb.h>
34 #include <linux/irq.h>
35 #include <linux/perf_event.h>
37 #include <asm/bootinfo.h>
38 #include <asm/branch.h>
39 #include <asm/break.h>
42 #include <asm/cpu-type.h>
45 #include <asm/fpu_emulator.h>
47 #include <asm/mipsregs.h>
48 #include <asm/mipsmtregs.h>
49 #include <asm/module.h>
50 #include <asm/pgtable.h>
51 #include <asm/ptrace.h>
52 #include <asm/sections.h>
53 #include <asm/tlbdebug.h>
54 #include <asm/traps.h>
55 #include <asm/uaccess.h>
56 #include <asm/watch.h>
57 #include <asm/mmu_context.h>
58 #include <asm/types.h>
59 #include <asm/stacktrace.h>
62 extern void check_wait(void);
63 extern asmlinkage
void rollback_handle_int(void);
64 extern asmlinkage
void handle_int(void);
65 extern u32 handle_tlbl
[];
66 extern u32 handle_tlbs
[];
67 extern u32 handle_tlbm
[];
68 extern asmlinkage
void handle_adel(void);
69 extern asmlinkage
void handle_ades(void);
70 extern asmlinkage
void handle_ibe(void);
71 extern asmlinkage
void handle_dbe(void);
72 extern asmlinkage
void handle_sys(void);
73 extern asmlinkage
void handle_bp(void);
74 extern asmlinkage
void handle_ri(void);
75 extern asmlinkage
void handle_ri_rdhwr_vivt(void);
76 extern asmlinkage
void handle_ri_rdhwr(void);
77 extern asmlinkage
void handle_cpu(void);
78 extern asmlinkage
void handle_ov(void);
79 extern asmlinkage
void handle_tr(void);
80 extern asmlinkage
void handle_fpe(void);
81 extern asmlinkage
void handle_mdmx(void);
82 extern asmlinkage
void handle_watch(void);
83 extern asmlinkage
void handle_mt(void);
84 extern asmlinkage
void handle_dsp(void);
85 extern asmlinkage
void handle_mcheck(void);
86 extern asmlinkage
void handle_reserved(void);
88 void (*board_be_init
)(void);
89 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
90 void (*board_nmi_handler_setup
)(void);
91 void (*board_ejtag_handler_setup
)(void);
92 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
93 void (*board_ebase_setup
)(void);
94 void(*board_cache_error_setup
)(void);
96 static void show_raw_backtrace(unsigned long reg29
)
98 unsigned long *sp
= (unsigned long *)(reg29
& ~3);
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
105 while (!kstack_end(sp
)) {
106 unsigned long __user
*p
=
107 (unsigned long __user
*)(unsigned long)sp
++;
108 if (__get_user(addr
, p
)) {
109 printk(" (Bad stack address)");
112 if (__kernel_text_address(addr
))
118 #ifdef CONFIG_KALLSYMS
120 static int __init
set_raw_show_trace(char *str
)
125 __setup("raw_show_trace", set_raw_show_trace
);
128 static void show_backtrace(struct task_struct
*task
, const struct pt_regs
*regs
)
130 unsigned long sp
= regs
->regs
[29];
131 unsigned long ra
= regs
->regs
[31];
132 unsigned long pc
= regs
->cp0_epc
;
137 if (raw_show_trace
|| !__kernel_text_address(pc
)) {
138 show_raw_backtrace(sp
);
141 printk("Call Trace:\n");
144 pc
= unwind_stack(task
, &sp
, pc
, &ra
);
150 * This routine abuses get_user()/put_user() to reference pointers
151 * with at least a bit of error checking ...
153 static void show_stacktrace(struct task_struct
*task
,
154 const struct pt_regs
*regs
)
156 const int field
= 2 * sizeof(unsigned long);
159 unsigned long __user
*sp
= (unsigned long __user
*)regs
->regs
[29];
163 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
164 if (i
&& ((i
% (64 / field
)) == 0))
171 if (__get_user(stackdata
, sp
++)) {
172 printk(" (Bad stack address)");
176 printk(" %0*lx", field
, stackdata
);
180 show_backtrace(task
, regs
);
183 void show_stack(struct task_struct
*task
, unsigned long *sp
)
187 regs
.regs
[29] = (unsigned long)sp
;
191 if (task
&& task
!= current
) {
192 regs
.regs
[29] = task
->thread
.reg29
;
194 regs
.cp0_epc
= task
->thread
.reg31
;
195 #ifdef CONFIG_KGDB_KDB
196 } else if (atomic_read(&kgdb_active
) != -1 &&
198 memcpy(®s
, kdb_current_regs
, sizeof(regs
));
199 #endif /* CONFIG_KGDB_KDB */
201 prepare_frametrace(®s
);
204 show_stacktrace(task
, ®s
);
207 static void show_code(unsigned int __user
*pc
)
210 unsigned short __user
*pc16
= NULL
;
214 if ((unsigned long)pc
& 1)
215 pc16
= (unsigned short __user
*)((unsigned long)pc
& ~1);
216 for(i
= -3 ; i
< 6 ; i
++) {
218 if (pc16
? __get_user(insn
, pc16
+ i
) : __get_user(insn
, pc
+ i
)) {
219 printk(" (Bad address in epc)\n");
222 printk("%c%0*x%c", (i
?' ':'<'), pc16
? 4 : 8, insn
, (i
?' ':'>'));
226 static void __show_regs(const struct pt_regs
*regs
)
228 const int field
= 2 * sizeof(unsigned long);
229 unsigned int cause
= regs
->cp0_cause
;
232 show_regs_print_info(KERN_DEFAULT
);
235 * Saved main processor registers
237 for (i
= 0; i
< 32; ) {
241 printk(" %0*lx", field
, 0UL);
242 else if (i
== 26 || i
== 27)
243 printk(" %*s", field
, "");
245 printk(" %0*lx", field
, regs
->regs
[i
]);
252 #ifdef CONFIG_CPU_HAS_SMARTMIPS
253 printk("Acx : %0*lx\n", field
, regs
->acx
);
255 printk("Hi : %0*lx\n", field
, regs
->hi
);
256 printk("Lo : %0*lx\n", field
, regs
->lo
);
259 * Saved cp0 registers
261 printk("epc : %0*lx %pS\n", field
, regs
->cp0_epc
,
262 (void *) regs
->cp0_epc
);
263 printk(" %s\n", print_tainted());
264 printk("ra : %0*lx %pS\n", field
, regs
->regs
[31],
265 (void *) regs
->regs
[31]);
267 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
270 if (regs
->cp0_status
& ST0_KUO
)
272 if (regs
->cp0_status
& ST0_IEO
)
274 if (regs
->cp0_status
& ST0_KUP
)
276 if (regs
->cp0_status
& ST0_IEP
)
278 if (regs
->cp0_status
& ST0_KUC
)
280 if (regs
->cp0_status
& ST0_IEC
)
282 } else if (cpu_has_4kex
) {
283 if (regs
->cp0_status
& ST0_KX
)
285 if (regs
->cp0_status
& ST0_SX
)
287 if (regs
->cp0_status
& ST0_UX
)
289 switch (regs
->cp0_status
& ST0_KSU
) {
294 printk("SUPERVISOR ");
303 if (regs
->cp0_status
& ST0_ERL
)
305 if (regs
->cp0_status
& ST0_EXL
)
307 if (regs
->cp0_status
& ST0_IE
)
312 printk("Cause : %08x\n", cause
);
314 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
315 if (1 <= cause
&& cause
<= 5)
316 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
318 printk("PrId : %08x (%s)\n", read_c0_prid(),
323 * FIXME: really the generic show_regs should take a const pointer argument.
325 void show_regs(struct pt_regs
*regs
)
327 __show_regs((struct pt_regs
*)regs
);
330 void show_registers(struct pt_regs
*regs
)
332 const int field
= 2 * sizeof(unsigned long);
336 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
337 current
->comm
, current
->pid
, current_thread_info(), current
,
338 field
, current_thread_info()->tp_value
);
339 if (cpu_has_userlocal
) {
342 tls
= read_c0_userlocal();
343 if (tls
!= current_thread_info()->tp_value
)
344 printk("*HwTLS: %0*lx\n", field
, tls
);
347 show_stacktrace(current
, regs
);
348 show_code((unsigned int __user
*) regs
->cp0_epc
);
352 static int regs_to_trapnr(struct pt_regs
*regs
)
354 return (regs
->cp0_cause
>> 2) & 0x1f;
357 static DEFINE_RAW_SPINLOCK(die_lock
);
359 void __noreturn
die(const char *str
, struct pt_regs
*regs
)
361 static int die_counter
;
363 #ifdef CONFIG_MIPS_MT_SMTC
364 unsigned long dvpret
;
365 #endif /* CONFIG_MIPS_MT_SMTC */
369 if (notify_die(DIE_OOPS
, str
, regs
, 0, regs_to_trapnr(regs
), SIGSEGV
) == NOTIFY_STOP
)
373 raw_spin_lock_irq(&die_lock
);
374 #ifdef CONFIG_MIPS_MT_SMTC
376 #endif /* CONFIG_MIPS_MT_SMTC */
378 #ifdef CONFIG_MIPS_MT_SMTC
379 mips_mt_regdump(dvpret
);
380 #endif /* CONFIG_MIPS_MT_SMTC */
382 printk("%s[#%d]:\n", str
, ++die_counter
);
383 show_registers(regs
);
384 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
385 raw_spin_unlock_irq(&die_lock
);
390 panic("Fatal exception in interrupt");
393 printk(KERN_EMERG
"Fatal exception: panic in 5 seconds");
395 panic("Fatal exception");
398 if (regs
&& kexec_should_crash(current
))
404 extern struct exception_table_entry __start___dbe_table
[];
405 extern struct exception_table_entry __stop___dbe_table
[];
408 " .section __dbe_table, \"a\"\n"
411 /* Given an address, look for it in the exception tables. */
412 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
414 const struct exception_table_entry
*e
;
416 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
418 e
= search_module_dbetables(addr
);
422 asmlinkage
void do_be(struct pt_regs
*regs
)
424 const int field
= 2 * sizeof(unsigned long);
425 const struct exception_table_entry
*fixup
= NULL
;
426 int data
= regs
->cp0_cause
& 4;
427 int action
= MIPS_BE_FATAL
;
428 enum ctx_state prev_state
;
430 prev_state
= exception_enter();
431 /* XXX For now. Fixme, this searches the wrong table ... */
432 if (data
&& !user_mode(regs
))
433 fixup
= search_dbe_tables(exception_epc(regs
));
436 action
= MIPS_BE_FIXUP
;
438 if (board_be_handler
)
439 action
= board_be_handler(regs
, fixup
!= NULL
);
442 case MIPS_BE_DISCARD
:
446 regs
->cp0_epc
= fixup
->nextinsn
;
455 * Assume it would be too dangerous to continue ...
457 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
458 data
? "Data" : "Instruction",
459 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
460 if (notify_die(DIE_OOPS
, "bus error", regs
, 0, regs_to_trapnr(regs
), SIGBUS
)
464 die_if_kernel("Oops", regs
);
465 force_sig(SIGBUS
, current
);
468 exception_exit(prev_state
);
472 * ll/sc, rdhwr, sync emulation
475 #define OPCODE 0xfc000000
476 #define BASE 0x03e00000
477 #define RT 0x001f0000
478 #define OFFSET 0x0000ffff
479 #define LL 0xc0000000
480 #define SC 0xe0000000
481 #define SPEC0 0x00000000
482 #define SPEC3 0x7c000000
483 #define RD 0x0000f800
484 #define FUNC 0x0000003f
485 #define SYNC 0x0000000f
486 #define RDHWR 0x0000003b
488 /* microMIPS definitions */
489 #define MM_POOL32A_FUNC 0xfc00ffff
490 #define MM_RDHWR 0x00006b3c
491 #define MM_RS 0x001f0000
492 #define MM_RT 0x03e00000
495 * The ll_bit is cleared by r*_switch.S
499 struct task_struct
*ll_task
;
501 static inline int simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
503 unsigned long value
, __user
*vaddr
;
507 * analyse the ll instruction that just caused a ri exception
508 * and put the referenced address to addr.
511 /* sign extend offset */
512 offset
= opcode
& OFFSET
;
516 vaddr
= (unsigned long __user
*)
517 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
519 if ((unsigned long)vaddr
& 3)
521 if (get_user(value
, vaddr
))
526 if (ll_task
== NULL
|| ll_task
== current
) {
535 regs
->regs
[(opcode
& RT
) >> 16] = value
;
540 static inline int simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
542 unsigned long __user
*vaddr
;
547 * analyse the sc instruction that just caused a ri exception
548 * and put the referenced address to addr.
551 /* sign extend offset */
552 offset
= opcode
& OFFSET
;
556 vaddr
= (unsigned long __user
*)
557 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
558 reg
= (opcode
& RT
) >> 16;
560 if ((unsigned long)vaddr
& 3)
565 if (ll_bit
== 0 || ll_task
!= current
) {
573 if (put_user(regs
->regs
[reg
], vaddr
))
582 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
583 * opcodes are supposed to result in coprocessor unusable exceptions if
584 * executed on ll/sc-less processors. That's the theory. In practice a
585 * few processors such as NEC's VR4100 throw reserved instruction exceptions
586 * instead, so we're doing the emulation thing in both exception handlers.
588 static int simulate_llsc(struct pt_regs
*regs
, unsigned int opcode
)
590 if ((opcode
& OPCODE
) == LL
) {
591 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
593 return simulate_ll(regs
, opcode
);
595 if ((opcode
& OPCODE
) == SC
) {
596 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
598 return simulate_sc(regs
, opcode
);
601 return -1; /* Must be something else ... */
605 * Simulate trapping 'rdhwr' instructions to provide user accessible
606 * registers not implemented in hardware.
608 static int simulate_rdhwr(struct pt_regs
*regs
, int rd
, int rt
)
610 struct thread_info
*ti
= task_thread_info(current
);
612 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
615 case 0: /* CPU number */
616 regs
->regs
[rt
] = smp_processor_id();
618 case 1: /* SYNCI length */
619 regs
->regs
[rt
] = min(current_cpu_data
.dcache
.linesz
,
620 current_cpu_data
.icache
.linesz
);
622 case 2: /* Read count register */
623 regs
->regs
[rt
] = read_c0_count();
625 case 3: /* Count register resolution */
626 switch (current_cpu_type()) {
636 regs
->regs
[rt
] = ti
->tp_value
;
643 static int simulate_rdhwr_normal(struct pt_regs
*regs
, unsigned int opcode
)
645 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
646 int rd
= (opcode
& RD
) >> 11;
647 int rt
= (opcode
& RT
) >> 16;
649 simulate_rdhwr(regs
, rd
, rt
);
657 static int simulate_rdhwr_mm(struct pt_regs
*regs
, unsigned short opcode
)
659 if ((opcode
& MM_POOL32A_FUNC
) == MM_RDHWR
) {
660 int rd
= (opcode
& MM_RS
) >> 16;
661 int rt
= (opcode
& MM_RT
) >> 21;
662 simulate_rdhwr(regs
, rd
, rt
);
670 static int simulate_sync(struct pt_regs
*regs
, unsigned int opcode
)
672 if ((opcode
& OPCODE
) == SPEC0
&& (opcode
& FUNC
) == SYNC
) {
673 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
678 return -1; /* Must be something else ... */
681 asmlinkage
void do_ov(struct pt_regs
*regs
)
683 enum ctx_state prev_state
;
686 prev_state
= exception_enter();
687 die_if_kernel("Integer overflow", regs
);
689 info
.si_code
= FPE_INTOVF
;
690 info
.si_signo
= SIGFPE
;
692 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
693 force_sig_info(SIGFPE
, &info
, current
);
694 exception_exit(prev_state
);
697 int process_fpemu_return(int sig
, void __user
*fault_addr
)
699 if (sig
== SIGSEGV
|| sig
== SIGBUS
) {
700 struct siginfo si
= {0};
701 si
.si_addr
= fault_addr
;
703 if (sig
== SIGSEGV
) {
704 if (find_vma(current
->mm
, (unsigned long)fault_addr
))
705 si
.si_code
= SEGV_ACCERR
;
707 si
.si_code
= SEGV_MAPERR
;
709 si
.si_code
= BUS_ADRERR
;
711 force_sig_info(sig
, &si
, current
);
714 force_sig(sig
, current
);
722 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
724 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
726 enum ctx_state prev_state
;
727 siginfo_t info
= {0};
729 prev_state
= exception_enter();
730 if (notify_die(DIE_FP
, "FP exception", regs
, 0, regs_to_trapnr(regs
), SIGFPE
)
733 die_if_kernel("FP exception in kernel code", regs
);
735 if (fcr31
& FPU_CSR_UNI_X
) {
737 void __user
*fault_addr
= NULL
;
740 * Unimplemented operation exception. If we've got the full
741 * software emulator on-board, let's use it...
743 * Force FPU to dump state into task/thread context. We're
744 * moving a lot of data here for what is probably a single
745 * instruction, but the alternative is to pre-decode the FP
746 * register operands before invoking the emulator, which seems
747 * a bit extreme for what should be an infrequent event.
749 /* Ensure 'resume' not overwrite saved fp context again. */
752 /* Run the emulator */
753 sig
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 1,
757 * We can't allow the emulated instruction to leave any of
758 * the cause bit set in $fcr31.
760 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
762 /* Restore the hardware register state */
763 own_fpu(1); /* Using the FPU again. */
765 /* If something went wrong, signal */
766 process_fpemu_return(sig
, fault_addr
);
769 } else if (fcr31
& FPU_CSR_INV_X
)
770 info
.si_code
= FPE_FLTINV
;
771 else if (fcr31
& FPU_CSR_DIV_X
)
772 info
.si_code
= FPE_FLTDIV
;
773 else if (fcr31
& FPU_CSR_OVF_X
)
774 info
.si_code
= FPE_FLTOVF
;
775 else if (fcr31
& FPU_CSR_UDF_X
)
776 info
.si_code
= FPE_FLTUND
;
777 else if (fcr31
& FPU_CSR_INE_X
)
778 info
.si_code
= FPE_FLTRES
;
780 info
.si_code
= __SI_FAULT
;
781 info
.si_signo
= SIGFPE
;
783 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
784 force_sig_info(SIGFPE
, &info
, current
);
787 exception_exit(prev_state
);
790 static void do_trap_or_bp(struct pt_regs
*regs
, unsigned int code
,
796 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
797 if (kgdb_ll_trap(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
799 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
801 if (notify_die(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
805 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
806 * insns, even for trap and break codes that indicate arithmetic
807 * failures. Weird ...
808 * But should we continue the brokenness??? --macro
813 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
814 die_if_kernel(b
, regs
);
815 if (code
== BRK_DIVZERO
)
816 info
.si_code
= FPE_INTDIV
;
818 info
.si_code
= FPE_INTOVF
;
819 info
.si_signo
= SIGFPE
;
821 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
822 force_sig_info(SIGFPE
, &info
, current
);
825 die_if_kernel("Kernel bug detected", regs
);
826 force_sig(SIGTRAP
, current
);
830 * Address errors may be deliberately induced by the FPU
831 * emulator to retake control of the CPU after executing the
832 * instruction in the delay slot of an emulated branch.
834 * Terminate if exception was recognized as a delay slot return
835 * otherwise handle as normal.
837 if (do_dsemulret(regs
))
840 die_if_kernel("Math emu break/trap", regs
);
841 force_sig(SIGTRAP
, current
);
844 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
845 die_if_kernel(b
, regs
);
846 force_sig(SIGTRAP
, current
);
850 asmlinkage
void do_bp(struct pt_regs
*regs
)
852 unsigned int opcode
, bcode
;
853 enum ctx_state prev_state
;
857 prev_state
= exception_enter();
858 if (get_isa16_mode(regs
->cp0_epc
)) {
860 epc
= exception_epc(regs
);
862 if ((__get_user(instr
[0], (u16 __user
*)msk_isa16_mode(epc
)) ||
863 (__get_user(instr
[1], (u16 __user
*)msk_isa16_mode(epc
+ 2)))))
865 opcode
= (instr
[0] << 16) | instr
[1];
868 if (__get_user(instr
[0], (u16 __user
*)msk_isa16_mode(epc
)))
870 bcode
= (instr
[0] >> 6) & 0x3f;
871 do_trap_or_bp(regs
, bcode
, "Break");
875 if (__get_user(opcode
, (unsigned int __user
*) exception_epc(regs
)))
880 * There is the ancient bug in the MIPS assemblers that the break
881 * code starts left to bit 16 instead to bit 6 in the opcode.
882 * Gas is bug-compatible, but not always, grrr...
883 * We handle both cases with a simple heuristics. --macro
885 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
886 if (bcode
>= (1 << 10))
890 * notify the kprobe handlers, if instruction is likely to
895 if (notify_die(DIE_BREAK
, "debug", regs
, bcode
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
899 case BRK_KPROBE_SSTEPBP
:
900 if (notify_die(DIE_SSTEPBP
, "single_step", regs
, bcode
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
908 do_trap_or_bp(regs
, bcode
, "Break");
911 exception_exit(prev_state
);
915 force_sig(SIGSEGV
, current
);
919 asmlinkage
void do_tr(struct pt_regs
*regs
)
921 u32 opcode
, tcode
= 0;
922 enum ctx_state prev_state
;
924 unsigned long epc
= msk_isa16_mode(exception_epc(regs
));
926 prev_state
= exception_enter();
927 if (get_isa16_mode(regs
->cp0_epc
)) {
928 if (__get_user(instr
[0], (u16 __user
*)(epc
+ 0)) ||
929 __get_user(instr
[1], (u16 __user
*)(epc
+ 2)))
931 opcode
= (instr
[0] << 16) | instr
[1];
932 /* Immediate versions don't provide a code. */
933 if (!(opcode
& OPCODE
))
934 tcode
= (opcode
>> 12) & ((1 << 4) - 1);
936 if (__get_user(opcode
, (u32 __user
*)epc
))
938 /* Immediate versions don't provide a code. */
939 if (!(opcode
& OPCODE
))
940 tcode
= (opcode
>> 6) & ((1 << 10) - 1);
943 do_trap_or_bp(regs
, tcode
, "Trap");
946 exception_exit(prev_state
);
950 force_sig(SIGSEGV
, current
);
954 asmlinkage
void do_ri(struct pt_regs
*regs
)
956 unsigned int __user
*epc
= (unsigned int __user
*)exception_epc(regs
);
957 unsigned long old_epc
= regs
->cp0_epc
;
958 unsigned long old31
= regs
->regs
[31];
959 enum ctx_state prev_state
;
960 unsigned int opcode
= 0;
963 prev_state
= exception_enter();
964 if (notify_die(DIE_RI
, "RI Fault", regs
, 0, regs_to_trapnr(regs
), SIGILL
)
968 die_if_kernel("Reserved instruction in kernel code", regs
);
970 if (unlikely(compute_return_epc(regs
) < 0))
973 if (get_isa16_mode(regs
->cp0_epc
)) {
974 unsigned short mmop
[2] = { 0 };
976 if (unlikely(get_user(mmop
[0], epc
) < 0))
978 if (unlikely(get_user(mmop
[1], epc
) < 0))
980 opcode
= (mmop
[0] << 16) | mmop
[1];
983 status
= simulate_rdhwr_mm(regs
, opcode
);
985 if (unlikely(get_user(opcode
, epc
) < 0))
988 if (!cpu_has_llsc
&& status
< 0)
989 status
= simulate_llsc(regs
, opcode
);
992 status
= simulate_rdhwr_normal(regs
, opcode
);
995 status
= simulate_sync(regs
, opcode
);
1001 if (unlikely(status
> 0)) {
1002 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1003 regs
->regs
[31] = old31
;
1004 force_sig(status
, current
);
1008 exception_exit(prev_state
);
1012 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1013 * emulated more than some threshold number of instructions, force migration to
1014 * a "CPU" that has FP support.
1016 static void mt_ase_fp_affinity(void)
1018 #ifdef CONFIG_MIPS_MT_FPAFF
1019 if (mt_fpemul_threshold
> 0 &&
1020 ((current
->thread
.emulated_fp
++ > mt_fpemul_threshold
))) {
1022 * If there's no FPU present, or if the application has already
1023 * restricted the allowed set to exclude any CPUs with FPUs,
1024 * we'll skip the procedure.
1026 if (cpus_intersects(current
->cpus_allowed
, mt_fpu_cpumask
)) {
1029 current
->thread
.user_cpus_allowed
1030 = current
->cpus_allowed
;
1031 cpus_and(tmask
, current
->cpus_allowed
,
1033 set_cpus_allowed_ptr(current
, &tmask
);
1034 set_thread_flag(TIF_FPUBOUND
);
1037 #endif /* CONFIG_MIPS_MT_FPAFF */
1041 * No lock; only written during early bootup by CPU 0.
1043 static RAW_NOTIFIER_HEAD(cu2_chain
);
1045 int __ref
register_cu2_notifier(struct notifier_block
*nb
)
1047 return raw_notifier_chain_register(&cu2_chain
, nb
);
1050 int cu2_notifier_call_chain(unsigned long val
, void *v
)
1052 return raw_notifier_call_chain(&cu2_chain
, val
, v
);
1055 static int default_cu2_call(struct notifier_block
*nfb
, unsigned long action
,
1058 struct pt_regs
*regs
= data
;
1060 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1061 "instruction", regs
);
1062 force_sig(SIGILL
, current
);
1067 asmlinkage
void do_cpu(struct pt_regs
*regs
)
1069 enum ctx_state prev_state
;
1070 unsigned int __user
*epc
;
1071 unsigned long old_epc
, old31
;
1072 unsigned int opcode
;
1075 unsigned long __maybe_unused flags
;
1077 prev_state
= exception_enter();
1078 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
1081 die_if_kernel("do_cpu invoked from kernel context!", regs
);
1085 epc
= (unsigned int __user
*)exception_epc(regs
);
1086 old_epc
= regs
->cp0_epc
;
1087 old31
= regs
->regs
[31];
1091 if (unlikely(compute_return_epc(regs
) < 0))
1094 if (get_isa16_mode(regs
->cp0_epc
)) {
1095 unsigned short mmop
[2] = { 0 };
1097 if (unlikely(get_user(mmop
[0], epc
) < 0))
1099 if (unlikely(get_user(mmop
[1], epc
) < 0))
1101 opcode
= (mmop
[0] << 16) | mmop
[1];
1104 status
= simulate_rdhwr_mm(regs
, opcode
);
1106 if (unlikely(get_user(opcode
, epc
) < 0))
1109 if (!cpu_has_llsc
&& status
< 0)
1110 status
= simulate_llsc(regs
, opcode
);
1113 status
= simulate_rdhwr_normal(regs
, opcode
);
1119 if (unlikely(status
> 0)) {
1120 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1121 regs
->regs
[31] = old31
;
1122 force_sig(status
, current
);
1129 * Old (MIPS I and MIPS II) processors will set this code
1130 * for COP1X opcode instructions that replaced the original
1131 * COP3 space. We don't limit COP1 space instructions in
1132 * the emulator according to the CPU ISA, so we want to
1133 * treat COP1X instructions consistently regardless of which
1134 * code the CPU chose. Therefore we redirect this trap to
1135 * the FP emulator too.
1137 * Then some newer FPU-less processors use this code
1138 * erroneously too, so they are covered by this choice
1141 if (raw_cpu_has_fpu
)
1146 if (used_math()) /* Using the FPU again. */
1148 else { /* First time FPU user. */
1153 if (!raw_cpu_has_fpu
) {
1155 void __user
*fault_addr
= NULL
;
1156 sig
= fpu_emulator_cop1Handler(regs
,
1157 ¤t
->thread
.fpu
,
1159 if (!process_fpemu_return(sig
, fault_addr
))
1160 mt_ase_fp_affinity();
1166 raw_notifier_call_chain(&cu2_chain
, CU2_EXCEPTION
, regs
);
1170 force_sig(SIGILL
, current
);
1173 exception_exit(prev_state
);
1176 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
1178 enum ctx_state prev_state
;
1180 prev_state
= exception_enter();
1181 force_sig(SIGILL
, current
);
1182 exception_exit(prev_state
);
1186 * Called with interrupts disabled.
1188 asmlinkage
void do_watch(struct pt_regs
*regs
)
1190 enum ctx_state prev_state
;
1193 prev_state
= exception_enter();
1195 * Clear WP (bit 22) bit of cause register so we don't loop
1198 cause
= read_c0_cause();
1199 cause
&= ~(1 << 22);
1200 write_c0_cause(cause
);
1203 * If the current thread has the watch registers loaded, save
1204 * their values and send SIGTRAP. Otherwise another thread
1205 * left the registers set, clear them and continue.
1207 if (test_tsk_thread_flag(current
, TIF_LOAD_WATCH
)) {
1208 mips_read_watch_registers();
1210 force_sig(SIGTRAP
, current
);
1212 mips_clear_watch_registers();
1215 exception_exit(prev_state
);
1218 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
1220 const int field
= 2 * sizeof(unsigned long);
1221 int multi_match
= regs
->cp0_status
& ST0_TS
;
1222 enum ctx_state prev_state
;
1224 prev_state
= exception_enter();
1228 printk("Index : %0x\n", read_c0_index());
1229 printk("Pagemask: %0x\n", read_c0_pagemask());
1230 printk("EntryHi : %0*lx\n", field
, read_c0_entryhi());
1231 printk("EntryLo0: %0*lx\n", field
, read_c0_entrylo0());
1232 printk("EntryLo1: %0*lx\n", field
, read_c0_entrylo1());
1237 show_code((unsigned int __user
*) regs
->cp0_epc
);
1240 * Some chips may have other causes of machine check (e.g. SB1
1243 panic("Caught Machine Check exception - %scaused by multiple "
1244 "matching entries in the TLB.",
1245 (multi_match
) ? "" : "not ");
1248 asmlinkage
void do_mt(struct pt_regs
*regs
)
1252 subcode
= (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT
)
1253 >> VPECONTROL_EXCPT_SHIFT
;
1256 printk(KERN_DEBUG
"Thread Underflow\n");
1259 printk(KERN_DEBUG
"Thread Overflow\n");
1262 printk(KERN_DEBUG
"Invalid YIELD Qualifier\n");
1265 printk(KERN_DEBUG
"Gating Storage Exception\n");
1268 printk(KERN_DEBUG
"YIELD Scheduler Exception\n");
1271 printk(KERN_DEBUG
"Gating Storage Scheduler Exception\n");
1274 printk(KERN_DEBUG
"*** UNKNOWN THREAD EXCEPTION %d ***\n",
1278 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
1280 force_sig(SIGILL
, current
);
1284 asmlinkage
void do_dsp(struct pt_regs
*regs
)
1287 panic("Unexpected DSP exception");
1289 force_sig(SIGILL
, current
);
1292 asmlinkage
void do_reserved(struct pt_regs
*regs
)
1295 * Game over - no way to handle this if it ever occurs. Most probably
1296 * caused by a new unknown cpu type or after another deadly
1297 * hard/software error.
1300 panic("Caught reserved exception %ld - should not happen.",
1301 (regs
->cp0_cause
& 0x7f) >> 2);
1304 static int __initdata l1parity
= 1;
1305 static int __init
nol1parity(char *s
)
1310 __setup("nol1par", nol1parity
);
1311 static int __initdata l2parity
= 1;
1312 static int __init
nol2parity(char *s
)
1317 __setup("nol2par", nol2parity
);
1320 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1321 * it different ways.
1323 static inline void parity_protection_init(void)
1325 switch (current_cpu_type()) {
1331 #define ERRCTL_PE 0x80000000
1332 #define ERRCTL_L2P 0x00800000
1333 unsigned long errctl
;
1334 unsigned int l1parity_present
, l2parity_present
;
1336 errctl
= read_c0_ecc();
1337 errctl
&= ~(ERRCTL_PE
|ERRCTL_L2P
);
1339 /* probe L1 parity support */
1340 write_c0_ecc(errctl
| ERRCTL_PE
);
1341 back_to_back_c0_hazard();
1342 l1parity_present
= (read_c0_ecc() & ERRCTL_PE
);
1344 /* probe L2 parity support */
1345 write_c0_ecc(errctl
|ERRCTL_L2P
);
1346 back_to_back_c0_hazard();
1347 l2parity_present
= (read_c0_ecc() & ERRCTL_L2P
);
1349 if (l1parity_present
&& l2parity_present
) {
1351 errctl
|= ERRCTL_PE
;
1352 if (l1parity
^ l2parity
)
1353 errctl
|= ERRCTL_L2P
;
1354 } else if (l1parity_present
) {
1356 errctl
|= ERRCTL_PE
;
1357 } else if (l2parity_present
) {
1359 errctl
|= ERRCTL_L2P
;
1361 /* No parity available */
1364 printk(KERN_INFO
"Writing ErrCtl register=%08lx\n", errctl
);
1366 write_c0_ecc(errctl
);
1367 back_to_back_c0_hazard();
1368 errctl
= read_c0_ecc();
1369 printk(KERN_INFO
"Readback ErrCtl register=%08lx\n", errctl
);
1371 if (l1parity_present
)
1372 printk(KERN_INFO
"Cache parity protection %sabled\n",
1373 (errctl
& ERRCTL_PE
) ? "en" : "dis");
1375 if (l2parity_present
) {
1376 if (l1parity_present
&& l1parity
)
1377 errctl
^= ERRCTL_L2P
;
1378 printk(KERN_INFO
"L2 cache parity protection %sabled\n",
1379 (errctl
& ERRCTL_L2P
) ? "en" : "dis");
1387 write_c0_ecc(0x80000000);
1388 back_to_back_c0_hazard();
1389 /* Set the PE bit (bit 31) in the c0_errctl register. */
1390 printk(KERN_INFO
"Cache parity protection %sabled\n",
1391 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1395 /* Clear the DE bit (bit 16) in the c0_status register. */
1396 printk(KERN_INFO
"Enable cache parity protection for "
1397 "MIPS 20KC/25KF CPUs.\n");
1398 clear_c0_status(ST0_DE
);
1405 asmlinkage
void cache_parity_error(void)
1407 const int field
= 2 * sizeof(unsigned long);
1408 unsigned int reg_val
;
1410 /* For the moment, report the problem and hang. */
1411 printk("Cache error exception:\n");
1412 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1413 reg_val
= read_c0_cacheerr();
1414 printk("c0_cacheerr == %08x\n", reg_val
);
1416 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1417 reg_val
& (1<<30) ? "secondary" : "primary",
1418 reg_val
& (1<<31) ? "data" : "insn");
1419 printk("Error bits: %s%s%s%s%s%s%s\n",
1420 reg_val
& (1<<29) ? "ED " : "",
1421 reg_val
& (1<<28) ? "ET " : "",
1422 reg_val
& (1<<26) ? "EE " : "",
1423 reg_val
& (1<<25) ? "EB " : "",
1424 reg_val
& (1<<24) ? "EI " : "",
1425 reg_val
& (1<<23) ? "E1 " : "",
1426 reg_val
& (1<<22) ? "E0 " : "");
1427 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
1429 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1430 if (reg_val
& (1<<22))
1431 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
1433 if (reg_val
& (1<<23))
1434 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
1437 panic("Can't handle the cache error!");
1441 * SDBBP EJTAG debug exception handler.
1442 * We skip the instruction and return to the next instruction.
1444 void ejtag_exception_handler(struct pt_regs
*regs
)
1446 const int field
= 2 * sizeof(unsigned long);
1447 unsigned long depc
, old_epc
, old_ra
;
1450 printk(KERN_DEBUG
"SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1451 depc
= read_c0_depc();
1452 debug
= read_c0_debug();
1453 printk(KERN_DEBUG
"c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
1454 if (debug
& 0x80000000) {
1456 * In branch delay slot.
1457 * We cheat a little bit here and use EPC to calculate the
1458 * debug return address (DEPC). EPC is restored after the
1461 old_epc
= regs
->cp0_epc
;
1462 old_ra
= regs
->regs
[31];
1463 regs
->cp0_epc
= depc
;
1464 compute_return_epc(regs
);
1465 depc
= regs
->cp0_epc
;
1466 regs
->cp0_epc
= old_epc
;
1467 regs
->regs
[31] = old_ra
;
1470 write_c0_depc(depc
);
1473 printk(KERN_DEBUG
"\n\n----- Enable EJTAG single stepping ----\n\n");
1474 write_c0_debug(debug
| 0x100);
1479 * NMI exception handler.
1480 * No lock; only written during early bootup by CPU 0.
1482 static RAW_NOTIFIER_HEAD(nmi_chain
);
1484 int register_nmi_notifier(struct notifier_block
*nb
)
1486 return raw_notifier_chain_register(&nmi_chain
, nb
);
1489 void __noreturn
nmi_exception_handler(struct pt_regs
*regs
)
1491 raw_notifier_call_chain(&nmi_chain
, 0, regs
);
1493 printk("NMI taken!!!!\n");
1497 #define VECTORSPACING 0x100 /* for EI/VI mode */
1499 unsigned long ebase
;
1500 unsigned long exception_handlers
[32];
1501 unsigned long vi_handlers
[64];
1503 void __init
*set_except_vector(int n
, void *addr
)
1505 unsigned long handler
= (unsigned long) addr
;
1506 unsigned long old_handler
;
1508 #ifdef CONFIG_CPU_MICROMIPS
1510 * Only the TLB handlers are cache aligned with an even
1511 * address. All other handlers are on an odd address and
1512 * require no modification. Otherwise, MIPS32 mode will
1513 * be entered when handling any TLB exceptions. That
1514 * would be bad...since we must stay in microMIPS mode.
1516 if (!(handler
& 0x1))
1519 old_handler
= xchg(&exception_handlers
[n
], handler
);
1521 if (n
== 0 && cpu_has_divec
) {
1522 #ifdef CONFIG_CPU_MICROMIPS
1523 unsigned long jump_mask
= ~((1 << 27) - 1);
1525 unsigned long jump_mask
= ~((1 << 28) - 1);
1527 u32
*buf
= (u32
*)(ebase
+ 0x200);
1528 unsigned int k0
= 26;
1529 if ((handler
& jump_mask
) == ((ebase
+ 0x200) & jump_mask
)) {
1530 uasm_i_j(&buf
, handler
& ~jump_mask
);
1533 UASM_i_LA(&buf
, k0
, handler
);
1534 uasm_i_jr(&buf
, k0
);
1537 local_flush_icache_range(ebase
+ 0x200, (unsigned long)buf
);
1539 return (void *)old_handler
;
1542 static void do_default_vi(void)
1544 show_regs(get_irq_regs());
1545 panic("Caught unexpected vectored interrupt.");
1548 static void *set_vi_srs_handler(int n
, vi_handler_t addr
, int srs
)
1550 unsigned long handler
;
1551 unsigned long old_handler
= vi_handlers
[n
];
1552 int srssets
= current_cpu_data
.srsets
;
1556 BUG_ON(!cpu_has_veic
&& !cpu_has_vint
);
1557 BUG_ON((n
< 0) && (n
> 9));
1560 handler
= (unsigned long) do_default_vi
;
1563 handler
= (unsigned long) addr
;
1564 vi_handlers
[n
] = handler
;
1566 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1569 panic("Shadow register set %d not supported", srs
);
1572 if (board_bind_eic_interrupt
)
1573 board_bind_eic_interrupt(n
, srs
);
1574 } else if (cpu_has_vint
) {
1575 /* SRSMap is only defined if shadow sets are implemented */
1577 change_c0_srsmap(0xf << n
*4, srs
<< n
*4);
1582 * If no shadow set is selected then use the default handler
1583 * that does normal register saving and standard interrupt exit
1585 extern char except_vec_vi
, except_vec_vi_lui
;
1586 extern char except_vec_vi_ori
, except_vec_vi_end
;
1587 extern char rollback_except_vec_vi
;
1588 char *vec_start
= using_rollback_handler() ?
1589 &rollback_except_vec_vi
: &except_vec_vi
;
1590 #ifdef CONFIG_MIPS_MT_SMTC
1592 * We need to provide the SMTC vectored interrupt handler
1593 * not only with the address of the handler, but with the
1594 * Status.IM bit to be masked before going there.
1596 extern char except_vec_vi_mori
;
1597 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1598 const int mori_offset
= &except_vec_vi_mori
- vec_start
+ 2;
1600 const int mori_offset
= &except_vec_vi_mori
- vec_start
;
1602 #endif /* CONFIG_MIPS_MT_SMTC */
1603 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1604 const int lui_offset
= &except_vec_vi_lui
- vec_start
+ 2;
1605 const int ori_offset
= &except_vec_vi_ori
- vec_start
+ 2;
1607 const int lui_offset
= &except_vec_vi_lui
- vec_start
;
1608 const int ori_offset
= &except_vec_vi_ori
- vec_start
;
1610 const int handler_len
= &except_vec_vi_end
- vec_start
;
1612 if (handler_len
> VECTORSPACING
) {
1614 * Sigh... panicing won't help as the console
1615 * is probably not configured :(
1617 panic("VECTORSPACING too small");
1620 set_handler(((unsigned long)b
- ebase
), vec_start
,
1621 #ifdef CONFIG_CPU_MICROMIPS
1626 #ifdef CONFIG_MIPS_MT_SMTC
1627 BUG_ON(n
> 7); /* Vector index %d exceeds SMTC maximum. */
1629 h
= (u16
*)(b
+ mori_offset
);
1631 #endif /* CONFIG_MIPS_MT_SMTC */
1632 h
= (u16
*)(b
+ lui_offset
);
1633 *h
= (handler
>> 16) & 0xffff;
1634 h
= (u16
*)(b
+ ori_offset
);
1635 *h
= (handler
& 0xffff);
1636 local_flush_icache_range((unsigned long)b
,
1637 (unsigned long)(b
+handler_len
));
1641 * In other cases jump directly to the interrupt handler. It
1642 * is the handler's responsibility to save registers if required
1643 * (eg hi/lo) and return from the exception using "eret".
1649 #ifdef CONFIG_CPU_MICROMIPS
1650 insn
= 0xd4000000 | (((u32
)handler
& 0x07ffffff) >> 1);
1652 insn
= 0x08000000 | (((u32
)handler
& 0x0fffffff) >> 2);
1654 h
[0] = (insn
>> 16) & 0xffff;
1655 h
[1] = insn
& 0xffff;
1658 local_flush_icache_range((unsigned long)b
,
1659 (unsigned long)(b
+8));
1662 return (void *)old_handler
;
1665 void *set_vi_handler(int n
, vi_handler_t addr
)
1667 return set_vi_srs_handler(n
, addr
, 0);
1670 extern void tlb_init(void);
1675 int cp0_compare_irq
;
1676 EXPORT_SYMBOL_GPL(cp0_compare_irq
);
1677 int cp0_compare_irq_shift
;
1680 * Performance counter IRQ or -1 if shared with timer
1682 int cp0_perfcount_irq
;
1683 EXPORT_SYMBOL_GPL(cp0_perfcount_irq
);
1687 static int __init
ulri_disable(char *s
)
1689 pr_info("Disabling ulri\n");
1694 __setup("noulri", ulri_disable
);
1696 void per_cpu_trap_init(bool is_boot_cpu
)
1698 unsigned int cpu
= smp_processor_id();
1699 unsigned int status_set
= ST0_CU0
;
1700 unsigned int hwrena
= cpu_hwrena_impl_bits
;
1701 #ifdef CONFIG_MIPS_MT_SMTC
1702 int secondaryTC
= 0;
1703 int bootTC
= (cpu
== 0);
1706 * Only do per_cpu_trap_init() for first TC of Each VPE.
1707 * Note that this hack assumes that the SMTC init code
1708 * assigns TCs consecutively and in ascending order.
1711 if (((read_c0_tcbind() & TCBIND_CURTC
) != 0) &&
1712 ((read_c0_tcbind() & TCBIND_CURVPE
) == cpu_data
[cpu
- 1].vpe_id
))
1714 #endif /* CONFIG_MIPS_MT_SMTC */
1717 * Disable coprocessors and select 32-bit or 64-bit addressing
1718 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1719 * flag that some firmware may have left set and the TS bit (for
1720 * IP27). Set XX for ISA IV code to work.
1723 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
1725 if (current_cpu_data
.isa_level
& MIPS_CPU_ISA_IV
)
1726 status_set
|= ST0_XX
;
1728 status_set
|= ST0_MX
;
1730 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1733 if (cpu_has_mips_r2
)
1734 hwrena
|= 0x0000000f;
1736 if (!noulri
&& cpu_has_userlocal
)
1737 hwrena
|= (1 << 29);
1740 write_c0_hwrena(hwrena
);
1742 #ifdef CONFIG_MIPS_MT_SMTC
1744 #endif /* CONFIG_MIPS_MT_SMTC */
1746 if (cpu_has_veic
|| cpu_has_vint
) {
1747 unsigned long sr
= set_c0_status(ST0_BEV
);
1748 write_c0_ebase(ebase
);
1749 write_c0_status(sr
);
1750 /* Setting vector spacing enables EI/VI mode */
1751 change_c0_intctl(0x3e0, VECTORSPACING
);
1753 if (cpu_has_divec
) {
1754 if (cpu_has_mipsmt
) {
1755 unsigned int vpflags
= dvpe();
1756 set_c0_cause(CAUSEF_IV
);
1759 set_c0_cause(CAUSEF_IV
);
1763 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1765 * o read IntCtl.IPTI to determine the timer interrupt
1766 * o read IntCtl.IPPCI to determine the performance counter interrupt
1768 if (cpu_has_mips_r2
) {
1769 cp0_compare_irq_shift
= CAUSEB_TI
- CAUSEB_IP
;
1770 cp0_compare_irq
= (read_c0_intctl() >> INTCTLB_IPTI
) & 7;
1771 cp0_perfcount_irq
= (read_c0_intctl() >> INTCTLB_IPPCI
) & 7;
1772 if (cp0_perfcount_irq
== cp0_compare_irq
)
1773 cp0_perfcount_irq
= -1;
1775 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
1776 cp0_compare_irq_shift
= CP0_LEGACY_PERFCNT_IRQ
;
1777 cp0_perfcount_irq
= -1;
1780 #ifdef CONFIG_MIPS_MT_SMTC
1782 #endif /* CONFIG_MIPS_MT_SMTC */
1784 if (!cpu_data
[cpu
].asid_cache
)
1785 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
1787 atomic_inc(&init_mm
.mm_count
);
1788 current
->active_mm
= &init_mm
;
1789 BUG_ON(current
->mm
);
1790 enter_lazy_tlb(&init_mm
, current
);
1792 #ifdef CONFIG_MIPS_MT_SMTC
1794 #endif /* CONFIG_MIPS_MT_SMTC */
1795 /* Boot CPU's cache setup in setup_arch(). */
1799 #ifdef CONFIG_MIPS_MT_SMTC
1800 } else if (!secondaryTC
) {
1802 * First TC in non-boot VPE must do subset of tlb_init()
1803 * for MMU countrol registers.
1805 write_c0_pagemask(PM_DEFAULT_MASK
);
1808 #endif /* CONFIG_MIPS_MT_SMTC */
1809 TLBMISS_HANDLER_SETUP();
1812 /* Install CPU exception handler */
1813 void set_handler(unsigned long offset
, void *addr
, unsigned long size
)
1815 #ifdef CONFIG_CPU_MICROMIPS
1816 memcpy((void *)(ebase
+ offset
), ((unsigned char *)addr
- 1), size
);
1818 memcpy((void *)(ebase
+ offset
), addr
, size
);
1820 local_flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
1823 static char panic_null_cerr
[] =
1824 "Trying to set NULL cache error exception handler";
1827 * Install uncached CPU exception handler.
1828 * This is suitable only for the cache error exception which is the only
1829 * exception handler that is being run uncached.
1831 void set_uncached_handler(unsigned long offset
, void *addr
,
1834 unsigned long uncached_ebase
= CKSEG1ADDR(ebase
);
1837 panic(panic_null_cerr
);
1839 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
1842 static int __initdata rdhwr_noopt
;
1843 static int __init
set_rdhwr_noopt(char *str
)
1849 __setup("rdhwr_noopt", set_rdhwr_noopt
);
1851 void __init
trap_init(void)
1853 extern char except_vec3_generic
;
1854 extern char except_vec4
;
1855 extern char except_vec3_r4000
;
1860 #if defined(CONFIG_KGDB)
1861 if (kgdb_early_setup
)
1862 return; /* Already done */
1865 if (cpu_has_veic
|| cpu_has_vint
) {
1866 unsigned long size
= 0x200 + VECTORSPACING
*64;
1867 ebase
= (unsigned long)
1868 __alloc_bootmem(size
, 1 << fls(size
), 0);
1870 #ifdef CONFIG_KVM_GUEST
1871 #define KVM_GUEST_KSEG0 0x40000000
1872 ebase
= KVM_GUEST_KSEG0
;
1876 if (cpu_has_mips_r2
)
1877 ebase
+= (read_c0_ebase() & 0x3ffff000);
1880 if (cpu_has_mmips
) {
1881 unsigned int config3
= read_c0_config3();
1883 if (IS_ENABLED(CONFIG_CPU_MICROMIPS
))
1884 write_c0_config3(config3
| MIPS_CONF3_ISA_OE
);
1886 write_c0_config3(config3
& ~MIPS_CONF3_ISA_OE
);
1889 if (board_ebase_setup
)
1890 board_ebase_setup();
1891 per_cpu_trap_init(true);
1894 * Copy the generic exception handlers to their final destination.
1895 * This will be overriden later as suitable for a particular
1898 set_handler(0x180, &except_vec3_generic
, 0x80);
1901 * Setup default vectors
1903 for (i
= 0; i
<= 31; i
++)
1904 set_except_vector(i
, handle_reserved
);
1907 * Copy the EJTAG debug exception vector handler code to it's final
1910 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
1911 board_ejtag_handler_setup();
1914 * Only some CPUs have the watch exceptions.
1917 set_except_vector(23, handle_watch
);
1920 * Initialise interrupt handlers
1922 if (cpu_has_veic
|| cpu_has_vint
) {
1923 int nvec
= cpu_has_veic
? 64 : 8;
1924 for (i
= 0; i
< nvec
; i
++)
1925 set_vi_handler(i
, NULL
);
1927 else if (cpu_has_divec
)
1928 set_handler(0x200, &except_vec4
, 0x8);
1931 * Some CPUs can enable/disable for cache parity detection, but does
1932 * it different ways.
1934 parity_protection_init();
1937 * The Data Bus Errors / Instruction Bus Errors are signaled
1938 * by external hardware. Therefore these two exceptions
1939 * may have board specific handlers.
1944 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
1946 set_except_vector(1, handle_tlbm
);
1947 set_except_vector(2, handle_tlbl
);
1948 set_except_vector(3, handle_tlbs
);
1950 set_except_vector(4, handle_adel
);
1951 set_except_vector(5, handle_ades
);
1953 set_except_vector(6, handle_ibe
);
1954 set_except_vector(7, handle_dbe
);
1956 set_except_vector(8, handle_sys
);
1957 set_except_vector(9, handle_bp
);
1958 set_except_vector(10, rdhwr_noopt
? handle_ri
:
1959 (cpu_has_vtag_icache
?
1960 handle_ri_rdhwr_vivt
: handle_ri_rdhwr
));
1961 set_except_vector(11, handle_cpu
);
1962 set_except_vector(12, handle_ov
);
1963 set_except_vector(13, handle_tr
);
1965 if (current_cpu_type() == CPU_R6000
||
1966 current_cpu_type() == CPU_R6000A
) {
1968 * The R6000 is the only R-series CPU that features a machine
1969 * check exception (similar to the R4000 cache error) and
1970 * unaligned ldc1/sdc1 exception. The handlers have not been
1971 * written yet. Well, anyway there is no R6000 machine on the
1972 * current list of targets for Linux/MIPS.
1973 * (Duh, crap, there is someone with a triple R6k machine)
1975 //set_except_vector(14, handle_mc);
1976 //set_except_vector(15, handle_ndc);
1980 if (board_nmi_handler_setup
)
1981 board_nmi_handler_setup();
1983 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1984 set_except_vector(15, handle_fpe
);
1986 set_except_vector(22, handle_mdmx
);
1989 set_except_vector(24, handle_mcheck
);
1992 set_except_vector(25, handle_mt
);
1994 set_except_vector(26, handle_dsp
);
1996 if (board_cache_error_setup
)
1997 board_cache_error_setup();
2000 /* Special exception: R4[04]00 uses also the divec space. */
2001 set_handler(0x180, &except_vec3_r4000
, 0x100);
2002 else if (cpu_has_4kex
)
2003 set_handler(0x180, &except_vec3_generic
, 0x80);
2005 set_handler(0x080, &except_vec3_generic
, 0x80);
2007 local_flush_icache_range(ebase
, ebase
+ 0x400);
2009 sort_extable(__start___dbe_table
, __stop___dbe_table
);
2011 cu2_notifier(default_cu2_call
, 0x80000000); /* Run last */