x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / powerpc / platforms / embedded6xx / hlwd-pic.c
blob3006b5117ec6cab1c7737ae12c5aa8a59f5a8fd3
1 /*
2 * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
4 * Nintendo Wii "Hollywood" interrupt controller support.
5 * Copyright (C) 2009 The GameCube Linux Team
6 * Copyright (C) 2009 Albert Herranz
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
14 #define DRV_MODULE_NAME "hlwd-pic"
15 #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/of.h>
21 #include <asm/io.h>
23 #include "hlwd-pic.h"
25 #define HLWD_NR_IRQS 32
28 * Each interrupt has a corresponding bit in both
29 * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
31 * Enabling/disabling an interrupt line involves asserting/clearing
32 * the corresponding bit in IMR. ACK'ing a request simply involves
33 * asserting the corresponding bit in ICR.
35 #define HW_BROADWAY_ICR 0x00
36 #define HW_BROADWAY_IMR 0x04
40 * IRQ chip hooks.
44 static void hlwd_pic_mask_and_ack(struct irq_data *d)
46 int irq = irqd_to_hwirq(d);
47 void __iomem *io_base = irq_data_get_irq_chip_data(d);
48 u32 mask = 1 << irq;
50 clrbits32(io_base + HW_BROADWAY_IMR, mask);
51 out_be32(io_base + HW_BROADWAY_ICR, mask);
54 static void hlwd_pic_ack(struct irq_data *d)
56 int irq = irqd_to_hwirq(d);
57 void __iomem *io_base = irq_data_get_irq_chip_data(d);
59 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
62 static void hlwd_pic_mask(struct irq_data *d)
64 int irq = irqd_to_hwirq(d);
65 void __iomem *io_base = irq_data_get_irq_chip_data(d);
67 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
70 static void hlwd_pic_unmask(struct irq_data *d)
72 int irq = irqd_to_hwirq(d);
73 void __iomem *io_base = irq_data_get_irq_chip_data(d);
75 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
79 static struct irq_chip hlwd_pic = {
80 .name = "hlwd-pic",
81 .irq_ack = hlwd_pic_ack,
82 .irq_mask_ack = hlwd_pic_mask_and_ack,
83 .irq_mask = hlwd_pic_mask,
84 .irq_unmask = hlwd_pic_unmask,
88 * IRQ host hooks.
92 static struct irq_domain *hlwd_irq_host;
94 static int hlwd_pic_map(struct irq_domain *h, unsigned int virq,
95 irq_hw_number_t hwirq)
97 irq_set_chip_data(virq, h->host_data);
98 irq_set_status_flags(virq, IRQ_LEVEL);
99 irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
100 return 0;
103 static const struct irq_domain_ops hlwd_irq_domain_ops = {
104 .map = hlwd_pic_map,
107 static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
109 void __iomem *io_base = h->host_data;
110 int irq;
111 u32 irq_status;
113 irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
114 in_be32(io_base + HW_BROADWAY_IMR);
115 if (irq_status == 0)
116 return NO_IRQ; /* no more IRQs pending */
118 irq = __ffs(irq_status);
119 return irq_linear_revmap(h, irq);
122 static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
123 struct irq_desc *desc)
125 struct irq_chip *chip = irq_desc_get_chip(desc);
126 struct irq_domain *irq_domain = irq_get_handler_data(cascade_virq);
127 unsigned int virq;
129 raw_spin_lock(&desc->lock);
130 chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
131 raw_spin_unlock(&desc->lock);
133 virq = __hlwd_pic_get_irq(irq_domain);
134 if (virq != NO_IRQ)
135 generic_handle_irq(virq);
136 else
137 pr_err("spurious interrupt!\n");
139 raw_spin_lock(&desc->lock);
140 chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
141 if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
142 chip->irq_unmask(&desc->irq_data);
143 raw_spin_unlock(&desc->lock);
147 * Platform hooks.
151 static void __hlwd_quiesce(void __iomem *io_base)
153 /* mask and ack all IRQs */
154 out_be32(io_base + HW_BROADWAY_IMR, 0);
155 out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
158 struct irq_domain *hlwd_pic_init(struct device_node *np)
160 struct irq_domain *irq_domain;
161 struct resource res;
162 void __iomem *io_base;
163 int retval;
165 retval = of_address_to_resource(np, 0, &res);
166 if (retval) {
167 pr_err("no io memory range found\n");
168 return NULL;
170 io_base = ioremap(res.start, resource_size(&res));
171 if (!io_base) {
172 pr_err("ioremap failed\n");
173 return NULL;
176 pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
178 __hlwd_quiesce(io_base);
180 irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS,
181 &hlwd_irq_domain_ops, io_base);
182 if (!irq_domain) {
183 pr_err("failed to allocate irq_domain\n");
184 return NULL;
187 return irq_domain;
190 unsigned int hlwd_pic_get_irq(void)
192 return __hlwd_pic_get_irq(hlwd_irq_host);
196 * Probe function.
200 void hlwd_pic_probe(void)
202 struct irq_domain *host;
203 struct device_node *np;
204 const u32 *interrupts;
205 int cascade_virq;
207 for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
208 interrupts = of_get_property(np, "interrupts", NULL);
209 if (interrupts) {
210 host = hlwd_pic_init(np);
211 BUG_ON(!host);
212 cascade_virq = irq_of_parse_and_map(np, 0);
213 irq_set_handler_data(cascade_virq, host);
214 irq_set_chained_handler(cascade_virq,
215 hlwd_pic_irq_cascade);
216 hlwd_irq_host = host;
217 break;
223 * hlwd_quiesce() - quiesce hollywood irq controller
225 * Mask and ack all interrupt sources.
228 void hlwd_quiesce(void)
230 void __iomem *io_base = hlwd_irq_host->host_data;
232 __hlwd_quiesce(io_base);