4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_eth.h>
16 #include <linux/sh_timer.h>
22 /* interrupt sources */
23 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
24 WDT
, EDMAC
, CMT0
, CMT1
,
27 DMAC0
, DMAC1
, DMAC2
, DMAC3
,
31 static struct intc_vect vectors
[] __initdata
= {
32 INTC_IRQ(IRQ0
, 64), INTC_IRQ(IRQ1
, 65),
33 INTC_IRQ(IRQ2
, 66), INTC_IRQ(IRQ3
, 67),
34 INTC_IRQ(IRQ4
, 80), INTC_IRQ(IRQ5
, 81),
35 INTC_IRQ(IRQ6
, 82), INTC_IRQ(IRQ7
, 83),
36 INTC_IRQ(WDT
, 84), INTC_IRQ(EDMAC
, 85),
37 INTC_IRQ(CMT0
, 86), INTC_IRQ(CMT1
, 87),
38 INTC_IRQ(SCIF0
, 88), INTC_IRQ(SCIF0
, 89),
39 INTC_IRQ(SCIF0
, 90), INTC_IRQ(SCIF0
, 91),
40 INTC_IRQ(SCIF1
, 92), INTC_IRQ(SCIF1
, 93),
41 INTC_IRQ(SCIF1
, 94), INTC_IRQ(SCIF1
, 95),
42 INTC_IRQ(SCIF2
, 96), INTC_IRQ(SCIF2
, 97),
43 INTC_IRQ(SCIF2
, 98), INTC_IRQ(SCIF2
, 99),
44 INTC_IRQ(HIF_HIFI
, 100), INTC_IRQ(HIF_HIFBI
, 101),
45 INTC_IRQ(DMAC0
, 104), INTC_IRQ(DMAC1
, 105),
46 INTC_IRQ(DMAC2
, 106), INTC_IRQ(DMAC3
, 107),
50 static struct intc_prio_reg prio_registers
[] __initdata
= {
51 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
} },
52 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
53 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT
, EDMAC
, CMT0
, CMT1
} },
54 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0
, SCIF1
, SCIF2
} },
55 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI
, HIF_HIFBI
} },
56 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0
, DMAC1
, DMAC2
, DMAC3
} },
57 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF
} },
60 static DECLARE_INTC_DESC(intc_desc
, "sh7619", vectors
, NULL
,
61 NULL
, prio_registers
, NULL
);
63 static struct plat_sci_port scif0_platform_data
= {
64 .mapbase
= 0xf8400000,
65 .flags
= UPF_BOOT_AUTOCONF
,
66 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
,
67 .scbrr_algo_id
= SCBRR_ALGO_2
,
69 .irqs
= SCIx_IRQ_MUXED(88),
72 static struct platform_device scif0_device
= {
76 .platform_data
= &scif0_platform_data
,
80 static struct plat_sci_port scif1_platform_data
= {
81 .mapbase
= 0xf8410000,
82 .flags
= UPF_BOOT_AUTOCONF
,
83 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
,
84 .scbrr_algo_id
= SCBRR_ALGO_2
,
86 .irqs
= SCIx_IRQ_MUXED(92),
89 static struct platform_device scif1_device
= {
93 .platform_data
= &scif1_platform_data
,
97 static struct plat_sci_port scif2_platform_data
= {
98 .mapbase
= 0xf8420000,
99 .flags
= UPF_BOOT_AUTOCONF
,
100 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
,
101 .scbrr_algo_id
= SCBRR_ALGO_2
,
103 .irqs
= SCIx_IRQ_MUXED(96),
106 static struct platform_device scif2_device
= {
110 .platform_data
= &scif2_platform_data
,
114 static struct sh_eth_plat_data eth_platform_data
= {
116 .edmac_endian
= EDMAC_LITTLE_ENDIAN
,
117 .phy_interface
= PHY_INTERFACE_MODE_MII
,
120 static struct resource eth_resources
[] = {
124 .flags
= IORESOURCE_MEM
,
129 .flags
= IORESOURCE_IRQ
,
133 static struct platform_device eth_device
= {
134 .name
= "sh7619-ether",
137 .platform_data
= ð_platform_data
,
139 .num_resources
= ARRAY_SIZE(eth_resources
),
140 .resource
= eth_resources
,
143 static struct sh_timer_config cmt0_platform_data
= {
144 .channel_offset
= 0x02,
146 .clockevent_rating
= 125,
147 .clocksource_rating
= 0, /* disabled due to code generation issues */
150 static struct resource cmt0_resources
[] = {
154 .flags
= IORESOURCE_MEM
,
158 .flags
= IORESOURCE_IRQ
,
162 static struct platform_device cmt0_device
= {
166 .platform_data
= &cmt0_platform_data
,
168 .resource
= cmt0_resources
,
169 .num_resources
= ARRAY_SIZE(cmt0_resources
),
172 static struct sh_timer_config cmt1_platform_data
= {
173 .channel_offset
= 0x08,
175 .clockevent_rating
= 125,
176 .clocksource_rating
= 0, /* disabled due to code generation issues */
179 static struct resource cmt1_resources
[] = {
183 .flags
= IORESOURCE_MEM
,
187 .flags
= IORESOURCE_IRQ
,
191 static struct platform_device cmt1_device
= {
195 .platform_data
= &cmt1_platform_data
,
197 .resource
= cmt1_resources
,
198 .num_resources
= ARRAY_SIZE(cmt1_resources
),
201 static struct platform_device
*sh7619_devices
[] __initdata
= {
210 static int __init
sh7619_devices_setup(void)
212 return platform_add_devices(sh7619_devices
,
213 ARRAY_SIZE(sh7619_devices
));
215 arch_initcall(sh7619_devices_setup
);
217 void __init
plat_irq_setup(void)
219 register_intc_controller(&intc_desc
);
222 static struct platform_device
*sh7619_early_devices
[] __initdata
= {
230 #define STBCR3 0xf80a0000
232 void __init
plat_early_device_setup(void)
234 /* enable CMT clock */
235 __raw_writeb(__raw_readb(STBCR3
) & ~0x10, STBCR3
);
237 early_platform_add_devices(sh7619_early_devices
,
238 ARRAY_SIZE(sh7619_early_devices
));