arch/sh/kernel/cpu/sh2a/setup-sh7269.c

   1 /*
   2  * SH7269 Setup
   3  *
   4  * Copyright (C) 2012  Renesas Electronics Europe Ltd
   5  * Copyright (C) 2012  Phil Edworthy
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/usb/r8a66597.h>
  16 #include <linux/sh_timer.h>
  17 #include <linux/io.h>
  18
  19 enum {
  20         UNUSED = 0,
  21
  22         /* interrupt sources */
  23         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  24         PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  25
  26         DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
  27         DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
  28         USB, VDC4, CMT0, CMT1, BSC, WDT,
  29         MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
  30         MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
  31         PWMT1, PWMT2, ADC_ADI,
  32         SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
  33         RSPDIF,
  34         IIC30, IIC31, IIC32, IIC33,
  35         SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
  36         SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
  37         SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
  38         SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
  39         SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
  40         SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
  41         SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
  42         SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
  43         RCAN0, RCAN1, RCAN2,
  44         RSPIC0, RSPIC1,
  45         IEBC, CD_ROMD,
  46         NFMC,
  47         SDHI0, SDHI1,
  48         RTC,
  49         SRCC0, SRCC1, SRCC2,
  50
  51         /* interrupt groups */
  52         PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
  53 };
  54
  55 static struct intc_vect vectors[] __initdata = {
  56         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  57         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  58         INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  59         INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  60
  61         INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  62         INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  63         INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  64         INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  65
  66         INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
  67         INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
  68         INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
  69         INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
  70         INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
  71         INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
  72         INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
  73         INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
  74         INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
  75         INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
  76         INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
  77         INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
  78         INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
  79         INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
  80         INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
  81         INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
  82
  83         INTC_IRQ(USB, 170),
  84
  85         INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
  86         INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
  87         INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
  88         INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
  89
  90         INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
  91
  92         INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
  93
  94         INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
  95         INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
  96         INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
  97         INTC_IRQ(MTU0_VEF, 198),
  98         INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
  99         INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
 100         INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
 101         INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
 102         INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
 103         INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
 104         INTC_IRQ(MTU3_TCI3V, 211),
 105         INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
 106         INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
 107         INTC_IRQ(MTU4_TCI4V, 216),
 108
 109         INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
 110
 111         INTC_IRQ(ADC_ADI, 223),
 112
 113         INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
 114         INTC_IRQ(SSIF0, 226),
 115         INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
 116         INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
 117         INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
 118         INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
 119         INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
 120
 121         INTC_IRQ(RSPDIF, 237),
 122
 123         INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
 124         INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
 125         INTC_IRQ(IIC30, 242),
 126         INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
 127         INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
 128         INTC_IRQ(IIC31, 247),
 129         INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
 130         INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
 131         INTC_IRQ(IIC32, 252),
 132         INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
 133         INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
 134         INTC_IRQ(IIC33, 257),
 135
 136         INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
 137         INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
 138         INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
 139         INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
 140         INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
 141         INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
 142         INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
 143         INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
 144         INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
 145         INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
 146         INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
 147         INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
 148         INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
 149         INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
 150         INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
 151         INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
 152
 153         INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
 154         INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
 155         INTC_IRQ(RCAN0, 295),
 156         INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
 157         INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
 158         INTC_IRQ(RCAN1, 300),
 159         INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
 160         INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
 161         INTC_IRQ(RCAN2, 305),
 162
 163         INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
 164         INTC_IRQ(RSPIC0, 308),
 165         INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
 166         INTC_IRQ(RSPIC1, 311),
 167
 168         INTC_IRQ(IEBC, 318),
 169
 170         INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
 171         INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
 172         INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
 173
 174         INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
 175         INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
 176
 177         INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
 178         INTC_IRQ(SDHI0, 334),
 179         INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
 180         INTC_IRQ(SDHI1, 337),
 181
 182         INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
 183         INTC_IRQ(RTC, 340),
 184
 185         INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
 186         INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
 187         INTC_IRQ(SRCC0, 345),
 188         INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
 189         INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
 190         INTC_IRQ(SRCC1, 350),
 191         INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
 192         INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
 193         INTC_IRQ(SRCC2, 355),
 194 };
 195
 196 static struct intc_group groups[] __initdata = {
 197         INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 198                    PINT4, PINT5, PINT6, PINT7),
 199         INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
 200         INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
 201         INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
 202         INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
 203         INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
 204         INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
 205         INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
 206         INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
 207 };
 208
 209 static struct intc_prio_reg prio_registers[] __initdata = {
 210         { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 211         { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 212         { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
 213         { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0,  DMAC1, DMAC2,  DMAC3 } },
 214         { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4,  DMAC5, DMAC6,  DMAC7 } },
 215         { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8,  DMAC9,
 216                                               DMAC10, DMAC11 } },
 217         { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
 218                                               DMAC14, DMAC15 } },
 219         { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
 220         { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
 221         { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
 222         { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
 223                                               MTU1_AB, MTU1_VU } },
 224         { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
 225                                               MTU3_ABCD, MTU3_TCI3V } },
 226         { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
 227                                               PWMT1, PWMT2 } },
 228         { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
 229         { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
 230         { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5,  RSPDIF} },
 231         { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
 232         { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
 233         { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
 234         { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
 235         { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
 236         { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
 237         { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
 238         { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
 239 };
 240
 241 static struct intc_mask_reg mask_registers[] __initdata = {
 242         { 0xfffe0808, 0, 16, /* PINTER */
 243           { 0, 0, 0, 0, 0, 0, 0, 0,
 244             PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 245 };
 246
 247 static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
 248                          mask_registers, prio_registers, NULL);
 249
 250 static struct plat_sci_port scif0_platform_data = {
 251         .mapbase        = 0xe8007000,
 252         .flags          = UPF_BOOT_AUTOCONF,
 253         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 254                           SCSCR_REIE | SCSCR_TOIE,
 255         .scbrr_algo_id  = SCBRR_ALGO_2,
 256         .type           = PORT_SCIF,
 257         .irqs           =  { 259, 260, 261, 258 },
 258         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 259 };
 260
 261 static struct platform_device scif0_device = {
 262         .name           = "sh-sci",
 263         .id             = 0,
 264         .dev            = {
 265                 .platform_data  = &scif0_platform_data,
 266         },
 267 };
 268
 269 static struct plat_sci_port scif1_platform_data = {
 270         .mapbase        = 0xe8007800,
 271         .flags          = UPF_BOOT_AUTOCONF,
 272         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 273                           SCSCR_REIE | SCSCR_TOIE,
 274         .scbrr_algo_id  = SCBRR_ALGO_2,
 275         .type           = PORT_SCIF,
 276         .irqs           =  { 263, 264, 265, 262 },
 277         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 278 };
 279
 280 static struct platform_device scif1_device = {
 281         .name           = "sh-sci",
 282         .id             = 1,
 283         .dev            = {
 284                 .platform_data  = &scif1_platform_data,
 285         },
 286 };
 287
 288 static struct plat_sci_port scif2_platform_data = {
 289         .mapbase        = 0xe8008000,
 290         .flags          = UPF_BOOT_AUTOCONF,
 291         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 292                           SCSCR_REIE | SCSCR_TOIE,
 293         .scbrr_algo_id  = SCBRR_ALGO_2,
 294         .type           = PORT_SCIF,
 295         .irqs           =  { 267, 268, 269, 266 },
 296         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 297 };
 298
 299 static struct platform_device scif2_device = {
 300         .name           = "sh-sci",
 301         .id             = 2,
 302         .dev            = {
 303                 .platform_data  = &scif2_platform_data,
 304         },
 305 };
 306
 307 static struct plat_sci_port scif3_platform_data = {
 308         .mapbase        = 0xe8008800,
 309         .flags          = UPF_BOOT_AUTOCONF,
 310         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 311                           SCSCR_REIE | SCSCR_TOIE,
 312         .scbrr_algo_id  = SCBRR_ALGO_2,
 313         .type           = PORT_SCIF,
 314         .irqs           =  { 271, 272, 273, 270 },
 315         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 316 };
 317
 318 static struct platform_device scif3_device = {
 319         .name           = "sh-sci",
 320         .id             = 3,
 321         .dev            = {
 322                 .platform_data  = &scif3_platform_data,
 323         },
 324 };
 325
 326 static struct plat_sci_port scif4_platform_data = {
 327         .mapbase        = 0xe8009000,
 328         .flags          = UPF_BOOT_AUTOCONF,
 329         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 330                           SCSCR_REIE | SCSCR_TOIE,
 331         .scbrr_algo_id  = SCBRR_ALGO_2,
 332         .type           = PORT_SCIF,
 333         .irqs           =  { 275, 276, 277, 274 },
 334         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 335 };
 336
 337 static struct platform_device scif4_device = {
 338         .name           = "sh-sci",
 339         .id             = 4,
 340         .dev            = {
 341                 .platform_data  = &scif4_platform_data,
 342         },
 343 };
 344
 345 static struct plat_sci_port scif5_platform_data = {
 346         .mapbase        = 0xe8009800,
 347         .flags          = UPF_BOOT_AUTOCONF,
 348         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 349                           SCSCR_REIE | SCSCR_TOIE,
 350         .scbrr_algo_id  = SCBRR_ALGO_2,
 351         .type           = PORT_SCIF,
 352         .irqs           =  { 279, 280, 281, 278 },
 353         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 354 };
 355
 356 static struct platform_device scif5_device = {
 357         .name           = "sh-sci",
 358         .id             = 5,
 359         .dev            = {
 360                 .platform_data  = &scif5_platform_data,
 361         },
 362 };
 363
 364 static struct plat_sci_port scif6_platform_data = {
 365         .mapbase        = 0xe800a000,
 366         .flags          = UPF_BOOT_AUTOCONF,
 367         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 368                           SCSCR_REIE | SCSCR_TOIE,
 369         .scbrr_algo_id  = SCBRR_ALGO_2,
 370         .type           = PORT_SCIF,
 371         .irqs           =  { 283, 284, 285, 282 },
 372         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 373 };
 374
 375 static struct platform_device scif6_device = {
 376         .name           = "sh-sci",
 377         .id             = 6,
 378         .dev            = {
 379                 .platform_data  = &scif6_platform_data,
 380         },
 381 };
 382
 383 static struct plat_sci_port scif7_platform_data = {
 384         .mapbase        = 0xe800a800,
 385         .flags          = UPF_BOOT_AUTOCONF,
 386         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
 387                           SCSCR_REIE | SCSCR_TOIE,
 388         .scbrr_algo_id  = SCBRR_ALGO_2,
 389         .type           = PORT_SCIF,
 390         .irqs           =  { 287, 288, 289, 286 },
 391         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 392 };
 393
 394 static struct platform_device scif7_device = {
 395         .name           = "sh-sci",
 396         .id             = 7,
 397         .dev            = {
 398                 .platform_data  = &scif7_platform_data,
 399         },
 400 };
 401
 402 static struct sh_timer_config cmt0_platform_data = {
 403         .channel_offset = 0x02,
 404         .timer_bit = 0,
 405         .clockevent_rating = 125,
 406         .clocksource_rating = 0, /* disabled due to code generation issues */
 407 };
 408
 409 static struct resource cmt0_resources[] = {
 410         [0] = {
 411                 .start  = 0xfffec002,
 412                 .end    = 0xfffec007,
 413                 .flags  = IORESOURCE_MEM,
 414         },
 415         [1] = {
 416                 .start  = 188,
 417                 .flags  = IORESOURCE_IRQ,
 418         },
 419 };
 420
 421 static struct platform_device cmt0_device = {
 422         .name           = "sh_cmt",
 423         .id             = 0,
 424         .dev = {
 425                 .platform_data  = &cmt0_platform_data,
 426         },
 427         .resource       = cmt0_resources,
 428         .num_resources  = ARRAY_SIZE(cmt0_resources),
 429 };
 430
 431 static struct sh_timer_config cmt1_platform_data = {
 432         .channel_offset = 0x08,
 433         .timer_bit = 1,
 434         .clockevent_rating = 125,
 435         .clocksource_rating = 0, /* disabled due to code generation issues */
 436 };
 437
 438 static struct resource cmt1_resources[] = {
 439         [0] = {
 440                 .start  = 0xfffec008,
 441                 .end    = 0xfffec00d,
 442                 .flags  = IORESOURCE_MEM,
 443         },
 444         [1] = {
 445                 .start  = 189,
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448 };
 449
 450 static struct platform_device cmt1_device = {
 451         .name           = "sh_cmt",
 452         .id             = 1,
 453         .dev = {
 454                 .platform_data  = &cmt1_platform_data,
 455         },
 456         .resource       = cmt1_resources,
 457         .num_resources  = ARRAY_SIZE(cmt1_resources),
 458 };
 459
 460 static struct sh_timer_config mtu2_0_platform_data = {
 461         .channel_offset = -0x80,
 462         .timer_bit = 0,
 463         .clockevent_rating = 200,
 464 };
 465
 466 static struct resource mtu2_0_resources[] = {
 467         [0] = {
 468                 .start  = 0xfffe4300,
 469                 .end    = 0xfffe4326,
 470                 .flags  = IORESOURCE_MEM,
 471         },
 472         [1] = {
 473                 .start  = 192,
 474                 .flags  = IORESOURCE_IRQ,
 475         },
 476 };
 477
 478 static struct platform_device mtu2_0_device = {
 479         .name           = "sh_mtu2",
 480         .id             = 0,
 481         .dev = {
 482                 .platform_data  = &mtu2_0_platform_data,
 483         },
 484         .resource       = mtu2_0_resources,
 485         .num_resources  = ARRAY_SIZE(mtu2_0_resources),
 486 };
 487
 488 static struct sh_timer_config mtu2_1_platform_data = {
 489         .channel_offset = -0x100,
 490         .timer_bit = 1,
 491         .clockevent_rating = 200,
 492 };
 493
 494 static struct resource mtu2_1_resources[] = {
 495         [0] = {
 496                 .start  = 0xfffe4380,
 497                 .end    = 0xfffe4390,
 498                 .flags  = IORESOURCE_MEM,
 499         },
 500         [1] = {
 501                 .start  = 203,
 502                 .flags  = IORESOURCE_IRQ,
 503         },
 504 };
 505
 506 static struct platform_device mtu2_1_device = {
 507         .name           = "sh_mtu2",
 508         .id             = 1,
 509         .dev = {
 510                 .platform_data  = &mtu2_1_platform_data,
 511         },
 512         .resource       = mtu2_1_resources,
 513         .num_resources  = ARRAY_SIZE(mtu2_1_resources),
 514 };
 515
 516 static struct resource rtc_resources[] = {
 517         [0] = {
 518                 .start  = 0xfffe6000,
 519                 .end    = 0xfffe6000 + 0x30 - 1,
 520                 .flags  = IORESOURCE_IO,
 521         },
 522         [1] = {
 523                 /* Shared Period/Carry/Alarm IRQ */
 524                 .start  = 338,
 525                 .flags  = IORESOURCE_IRQ,
 526         },
 527 };
 528
 529 static struct platform_device rtc_device = {
 530         .name           = "sh-rtc",
 531         .id             = -1,
 532         .num_resources  = ARRAY_SIZE(rtc_resources),
 533         .resource       = rtc_resources,
 534 };
 535
 536 /* USB Host */
 537 static struct r8a66597_platdata r8a66597_data = {
 538         .on_chip = 1,
 539         .endian = 1,
 540 };
 541
 542 static struct resource r8a66597_usb_host_resources[] = {
 543         [0] = {
 544                 .start  = 0xe8010000,
 545                 .end    = 0xe80100e4,
 546                 .flags  = IORESOURCE_MEM,
 547         },
 548         [1] = {
 549                 .start  = 170,
 550                 .end    = 170,
 551                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 552         },
 553 };
 554
 555 static struct platform_device r8a66597_usb_host_device = {
 556         .name           = "r8a66597_hcd",
 557         .id             = 0,
 558         .dev = {
 559                 .dma_mask               = NULL,         /*  not use dma */
 560                 .coherent_dma_mask      = 0xffffffff,
 561                 .platform_data          = &r8a66597_data,
 562         },
 563         .num_resources  = ARRAY_SIZE(r8a66597_usb_host_resources),
 564         .resource       = r8a66597_usb_host_resources,
 565 };
 566
 567 static struct platform_device *sh7269_devices[] __initdata = {
 568         &scif0_device,
 569         &scif1_device,
 570         &scif2_device,
 571         &scif3_device,
 572         &scif4_device,
 573         &scif5_device,
 574         &scif6_device,
 575         &scif7_device,
 576         &cmt0_device,
 577         &cmt1_device,
 578         &mtu2_0_device,
 579         &mtu2_1_device,
 580         &rtc_device,
 581         &r8a66597_usb_host_device,
 582 };
 583
 584 static int __init sh7269_devices_setup(void)
 585 {
 586         return platform_add_devices(sh7269_devices,
 587                                     ARRAY_SIZE(sh7269_devices));
 588 }
 589 arch_initcall(sh7269_devices_setup);
 590
 591 void __init plat_irq_setup(void)
 592 {
 593         register_intc_controller(&intc_desc);
 594 }
 595
 596 static struct platform_device *sh7269_early_devices[] __initdata = {
 597         &scif0_device,
 598         &scif1_device,
 599         &scif2_device,
 600         &scif3_device,
 601         &scif4_device,
 602         &scif5_device,
 603         &scif6_device,
 604         &scif7_device,
 605         &cmt0_device,
 606         &cmt1_device,
 607         &mtu2_0_device,
 608         &mtu2_1_device,
 609 };
 610
 611 void __init plat_early_device_setup(void)
 612 {
 613         early_platform_add_devices(sh7269_early_devices,
 614                                    ARRAY_SIZE(sh7269_early_devices));
 615 }