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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / x86 / include / asm / uv / uv_bau.h
blob0b46ef261c7755837d770832489e6a6c090fc0ac
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16
17 /*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36 #define MAX_CPUS_PER_UVHUB 64
37 #define MAX_CPUS_PER_SOCKET 32
38 #define ADP_SZ 64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC 8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_DESC_PSHIFT 49
52 #define UV_PAYLOADQ_PNODE_SHIFT 49
53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55 #define UV_BAU_TUNABLES_DIR "sgi_uv"
56 #define UV_BAU_TUNABLES_FILE "bau_tunables"
57 #define WHITESPACE " \t\n"
58 #define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59 #define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60 #define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
62
63 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
64 /*
65 * UV2: Bit 19 selects between
66 * (0): 10 microsecond timebase and
67 * (1): 80 microseconds
68 * we're using 560us, similar to UV1: 65 units of 10us
69 */
70 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77 #define BAU_MISC_CONTROL_MULT_MASK 3
78
79 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80 /* [30:28] URGENCY_7 an index into a table of times */
81 #define BAU_URGENCY_7_SHIFT 28
82 #define BAU_URGENCY_7_MASK 7
83
84 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
86 #define BAU_TRANS_SHIFT 40
87 #define BAU_TRANS_MASK 0x3f
88
89 /*
90 * shorten some awkward names
91 */
92 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96 #define write_gmmr uv_write_global_mmr64
97 #define write_lmmr uv_write_local_mmr
98 #define read_lmmr uv_read_local_mmr
99 #define read_gmmr uv_read_global_mmr64
100
101 /*
102 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
103 */
104 #define DS_IDLE 0
105 #define DS_ACTIVE 1
106 #define DS_DESTINATION_TIMEOUT 2
107 #define DS_SOURCE_TIMEOUT 3
108 /*
109 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
110 * values 1 and 3 will not occur
111 * Decoded meaning ERROR BUSY AUX ERR
112 * ------------------------------- ---- ----- -------
113 * IDLE 0 0 0
114 * BUSY (active) 0 1 0
115 * SW Ack Timeout (destination) 1 0 0
116 * SW Ack INTD rejected (strong NACK) 1 0 1
117 * Source Side Time Out Detected 1 1 0
118 * Destination Side PUT Failed 1 1 1
119 */
120 #define UV2H_DESC_IDLE 0
121 #define UV2H_DESC_BUSY 2
122 #define UV2H_DESC_DEST_TIMEOUT 4
123 #define UV2H_DESC_DEST_STRONG_NACK 5
124 #define UV2H_DESC_SOURCE_TIMEOUT 6
125 #define UV2H_DESC_DEST_PUT_ERR 7
126
127 /*
128 * delay for 'plugged' timeout retries, in microseconds
129 */
130 #define PLUGGED_DELAY 10
131
132 /*
133 * threshholds at which to use IPI to free resources
134 */
135 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
136 #define PLUGSB4RESET 100
137 /* after this many consecutive timeouts, use IPI to release resources */
138 #define TIMEOUTSB4RESET 1
139 /* at this number uses of IPI to release resources, giveup the request */
140 #define IPI_RESET_LIMIT 1
141 /* after this # consecutive successes, bump up the throttle if it was lowered */
142 #define COMPLETE_THRESHOLD 5
143 /* after this # of giveups (fall back to kernel IPI's) disable the use of
144 the BAU for a period of time */
145 #define GIVEUP_LIMIT 100
146
147 #define UV_LB_SUBNODEID 0x10
148
149 /* these two are the same for UV1 and UV2: */
150 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
151 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
152 /* 4 bits of software ack period */
153 #define UV2_ACK_MASK 0x7UL
154 #define UV2_ACK_UNITS_SHFT 3
155 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
156
157 /*
158 * number of entries in the destination side payload queue
159 */
160 #define DEST_Q_SIZE 20
161 /*
162 * number of destination side software ack resources
163 */
164 #define DEST_NUM_RESOURCES 8
165 /*
166 * completion statuses for sending a TLB flush message
167 */
168 #define FLUSH_RETRY_PLUGGED 1
169 #define FLUSH_RETRY_TIMEOUT 2
170 #define FLUSH_GIVEUP 3
171 #define FLUSH_COMPLETE 4
172
173 /*
174 * tuning the action when the numalink network is extremely delayed
175 */
176 #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
177 microseconds */
178 #define CONGESTED_REPS 10 /* long delays averaged over
179 this many broadcasts */
180 #define DISABLED_PERIOD 10 /* time for the bau to be
181 disabled, in seconds */
182 /* see msg_type: */
183 #define MSG_NOOP 0
184 #define MSG_REGULAR 1
185 #define MSG_RETRY 2
186
187 /*
188 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
189 * If the 'multilevel' flag in the header portion of the descriptor
190 * has been set to 0, then endpoint multi-unicast mode is selected.
191 * The distribution specification (32 bytes) is interpreted as a 256-bit
192 * distribution vector. Adjacent bits correspond to consecutive even numbered
193 * nodeIDs. The result of adding the index of a given bit to the 15-bit
194 * 'base_dest_nasid' field of the header corresponds to the
195 * destination nodeID associated with that specified bit.
196 */
197 struct pnmask {
198 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
199 };
200
201 /*
202 * mask of cpu's on a uvhub
203 * (during initialization we need to check that unsigned long has
204 * enough bits for max. cpu's per uvhub)
205 */
206 struct bau_local_cpumask {
207 unsigned long bits;
208 };
209
210 /*
211 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
212 * only 12 bytes (96 bits) of the payload area are usable.
213 * An additional 3 bytes (bits 27:4) of the header address are carried
214 * to the next bytes of the destination payload queue.
215 * And an additional 2 bytes of the header Suppl_A field are also
216 * carried to the destination payload queue.
217 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
218 * of the destination payload queue, which is written by the hardware
219 * with the s/w ack resource bit vector.
220 * [ effective message contents (16 bytes (128 bits) maximum), not counting
221 * the s/w ack bit vector ]
222 */
223
224 /*
225 * The payload is software-defined for INTD transactions
226 */
227 struct bau_msg_payload {
228 unsigned long address; /* signifies a page or all
229 TLB's of the cpu */
230 /* 64 bits */
231 unsigned short sending_cpu; /* filled in by sender */
232 /* 16 bits */
233 unsigned short acknowledge_count; /* filled in by destination */
234 /* 16 bits */
235 unsigned int reserved1:32; /* not usable */
236 };
237
238
239 /*
240 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
241 * see table 4.2.3.0.1 in broacast_assist spec.
242 */
243 struct uv1_bau_msg_header {
244 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
245 /* bits 5:0 */
246 unsigned int base_dest_nasid:15; /* nasid of the first bit */
247 /* bits 20:6 */ /* in uvhub map */
248 unsigned int command:8; /* message type */
249 /* bits 28:21 */
250 /* 0x38: SN3net EndPoint Message */
251 unsigned int rsvd_1:3; /* must be zero */
252 /* bits 31:29 */
253 /* int will align on 32 bits */
254 unsigned int rsvd_2:9; /* must be zero */
255 /* bits 40:32 */
256 /* Suppl_A is 56-41 */
257 unsigned int sequence:16; /* message sequence number */
258 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
259 /* Address field (96:57) is
260 never used as an address
261 (these are address bits
262 42:3) */
263
264 unsigned int rsvd_3:1; /* must be zero */
265 /* bit 57 */
266 /* address bits 27:4 are payload */
267 /* these next 24 (58-81) bits become bytes 12-14 of msg */
268 /* bits 65:58 land in byte 12 */
269 unsigned int replied_to:1; /* sent as 0 by the source to
270 byte 12 */
271 /* bit 58 */
272 unsigned int msg_type:3; /* software type of the
273 message */
274 /* bits 61:59 */
275 unsigned int canceled:1; /* message canceled, resource
276 is to be freed*/
277 /* bit 62 */
278 unsigned int payload_1a:1; /* not currently used */
279 /* bit 63 */
280 unsigned int payload_1b:2; /* not currently used */
281 /* bits 65:64 */
282
283 /* bits 73:66 land in byte 13 */
284 unsigned int payload_1ca:6; /* not currently used */
285 /* bits 71:66 */
286 unsigned int payload_1c:2; /* not currently used */
287 /* bits 73:72 */
288
289 /* bits 81:74 land in byte 14 */
290 unsigned int payload_1d:6; /* not currently used */
291 /* bits 79:74 */
292 unsigned int payload_1e:2; /* not currently used */
293 /* bits 81:80 */
294
295 unsigned int rsvd_4:7; /* must be zero */
296 /* bits 88:82 */
297 unsigned int swack_flag:1; /* software acknowledge flag */
298 /* bit 89 */
299 /* INTD trasactions at
300 destination are to wait for
301 software acknowledge */
302 unsigned int rsvd_5:6; /* must be zero */
303 /* bits 95:90 */
304 unsigned int rsvd_6:5; /* must be zero */
305 /* bits 100:96 */
306 unsigned int int_both:1; /* if 1, interrupt both sockets
307 on the uvhub */
308 /* bit 101*/
309 unsigned int fairness:3; /* usually zero */
310 /* bits 104:102 */
311 unsigned int multilevel:1; /* multi-level multicast
312 format */
313 /* bit 105 */
314 /* 0 for TLB: endpoint multi-unicast messages */
315 unsigned int chaining:1; /* next descriptor is part of
316 this activation*/
317 /* bit 106 */
318 unsigned int rsvd_7:21; /* must be zero */
319 /* bits 127:107 */
320 };
321
322 /*
323 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
324 * see figure 9-2 of harp_sys.pdf
325 */
326 struct uv2_bau_msg_header {
327 unsigned int base_dest_nasid:15; /* nasid of the first bit */
328 /* bits 14:0 */ /* in uvhub map */
329 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
330 /* bits 19:15 */
331 unsigned int rsvd_1:1; /* must be zero */
332 /* bit 20 */
333 /* Address bits 59:21 */
334 /* bits 25:2 of address (44:21) are payload */
335 /* these next 24 bits become bytes 12-14 of msg */
336 /* bits 28:21 land in byte 12 */
337 unsigned int replied_to:1; /* sent as 0 by the source to
338 byte 12 */
339 /* bit 21 */
340 unsigned int msg_type:3; /* software type of the
341 message */
342 /* bits 24:22 */
343 unsigned int canceled:1; /* message canceled, resource
344 is to be freed*/
345 /* bit 25 */
346 unsigned int payload_1:3; /* not currently used */
347 /* bits 28:26 */
348
349 /* bits 36:29 land in byte 13 */
350 unsigned int payload_2a:3; /* not currently used */
351 unsigned int payload_2b:5; /* not currently used */
352 /* bits 36:29 */
353
354 /* bits 44:37 land in byte 14 */
355 unsigned int payload_3:8; /* not currently used */
356 /* bits 44:37 */
357
358 unsigned int rsvd_2:7; /* reserved */
359 /* bits 51:45 */
360 unsigned int swack_flag:1; /* software acknowledge flag */
361 /* bit 52 */
362 unsigned int rsvd_3a:3; /* must be zero */
363 unsigned int rsvd_3b:8; /* must be zero */
364 unsigned int rsvd_3c:8; /* must be zero */
365 unsigned int rsvd_3d:3; /* must be zero */
366 /* bits 74:53 */
367 unsigned int fairness:3; /* usually zero */
368 /* bits 77:75 */
369
370 unsigned int sequence:16; /* message sequence number */
371 /* bits 93:78 Suppl_A */
372 unsigned int chaining:1; /* next descriptor is part of
373 this activation*/
374 /* bit 94 */
375 unsigned int multilevel:1; /* multi-level multicast
376 format */
377 /* bit 95 */
378 unsigned int rsvd_4:24; /* ordered / source node /
379 source subnode / aging
380 must be zero */
381 /* bits 119:96 */
382 unsigned int command:8; /* message type */
383 /* bits 127:120 */
384 };
385
386 /*
387 * The activation descriptor:
388 * The format of the message to send, plus all accompanying control
389 * Should be 64 bytes
390 */
391 struct bau_desc {
392 struct pnmask distribution;
393 /*
394 * message template, consisting of header and payload:
395 */
396 union bau_msg_header {
397 struct uv1_bau_msg_header uv1_hdr;
398 struct uv2_bau_msg_header uv2_hdr;
399 } header;
400
401 struct bau_msg_payload payload;
402 };
403 /* UV1:
404 * -payload-- ---------header------
405 * bytes 0-11 bits 41-56 bits 58-81
406 * A B (2) C (3)
407 *
408 * A/B/C are moved to:
409 * A C B
410 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
411 * ------------payload queue-----------
412 */
413 /* UV2:
414 * -payload-- ---------header------
415 * bytes 0-11 bits 70-78 bits 21-44
416 * A B (2) C (3)
417 *
418 * A/B/C are moved to:
419 * A C B
420 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
421 * ------------payload queue-----------
422 */
423
424 /*
425 * The payload queue on the destination side is an array of these.
426 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
427 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
428 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
429 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
430 * swack_vec and payload_2)
431 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
432 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
433 * operation."
434 */
435 struct bau_pq_entry {
436 unsigned long address; /* signifies a page or all TLB's
437 of the cpu */
438 /* 64 bits, bytes 0-7 */
439 unsigned short sending_cpu; /* cpu that sent the message */
440 /* 16 bits, bytes 8-9 */
441 unsigned short acknowledge_count; /* filled in by destination */
442 /* 16 bits, bytes 10-11 */
443 /* these next 3 bytes come from bits 58-81 of the message header */
444 unsigned short replied_to:1; /* sent as 0 by the source */
445 unsigned short msg_type:3; /* software message type */
446 unsigned short canceled:1; /* sent as 0 by the source */
447 unsigned short unused1:3; /* not currently using */
448 /* byte 12 */
449 unsigned char unused2a; /* not currently using */
450 /* byte 13 */
451 unsigned char unused2; /* not currently using */
452 /* byte 14 */
453 unsigned char swack_vec; /* filled in by the hardware */
454 /* byte 15 (bits 127:120) */
455 unsigned short sequence; /* message sequence number */
456 /* bytes 16-17 */
457 unsigned char unused4[2]; /* not currently using bytes 18-19 */
458 /* bytes 18-19 */
459 int number_of_cpus; /* filled in at destination */
460 /* 32 bits, bytes 20-23 (aligned) */
461 unsigned char unused5[8]; /* not using */
462 /* bytes 24-31 */
463 };
464
465 struct msg_desc {
466 struct bau_pq_entry *msg;
467 int msg_slot;
468 struct bau_pq_entry *queue_first;
469 struct bau_pq_entry *queue_last;
470 };
471
472 struct reset_args {
473 int sender;
474 };
475
476 /*
477 * This structure is allocated per_cpu for UV TLB shootdown statistics.
478 */
479 struct ptc_stats {
480 /* sender statistics */
481 unsigned long s_giveup; /* number of fall backs to
482 IPI-style flushes */
483 unsigned long s_requestor; /* number of shootdown
484 requests */
485 unsigned long s_stimeout; /* source side timeouts */
486 unsigned long s_dtimeout; /* destination side timeouts */
487 unsigned long s_strongnacks; /* number of strong nack's */
488 unsigned long s_time; /* time spent in sending side */
489 unsigned long s_retriesok; /* successful retries */
490 unsigned long s_ntargcpu; /* total number of cpu's
491 targeted */
492 unsigned long s_ntargself; /* times the sending cpu was
493 targeted */
494 unsigned long s_ntarglocals; /* targets of cpus on the local
495 blade */
496 unsigned long s_ntargremotes; /* targets of cpus on remote
497 blades */
498 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
499 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
500 unsigned long s_ntarguvhub; /* total number of uvhubs
501 targeted */
502 unsigned long s_ntarguvhub16; /* number of times target
503 hubs >= 16*/
504 unsigned long s_ntarguvhub8; /* number of times target
505 hubs >= 8 */
506 unsigned long s_ntarguvhub4; /* number of times target
507 hubs >= 4 */
508 unsigned long s_ntarguvhub2; /* number of times target
509 hubs >= 2 */
510 unsigned long s_ntarguvhub1; /* number of times target
511 hubs == 1 */
512 unsigned long s_resets_plug; /* ipi-style resets from plug
513 state */
514 unsigned long s_resets_timeout; /* ipi-style resets from
515 timeouts */
516 unsigned long s_busy; /* status stayed busy past
517 s/w timer */
518 unsigned long s_throttles; /* waits in throttle */
519 unsigned long s_retry_messages; /* retry broadcasts */
520 unsigned long s_bau_reenabled; /* for bau enable/disable */
521 unsigned long s_bau_disabled; /* for bau enable/disable */
522 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
523 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
524 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
525 unsigned long s_overipilimit; /* over the ipi reset limit */
526 unsigned long s_giveuplimit; /* disables, over giveup limit*/
527 unsigned long s_enters; /* entries to the driver */
528 unsigned long s_ipifordisabled; /* fall back to IPI; disabled */
529 unsigned long s_plugged; /* plugged by h/w bug*/
530 unsigned long s_congested; /* giveup on long wait */
531 /* destination statistics */
532 unsigned long d_alltlb; /* times all tlb's on this
533 cpu were flushed */
534 unsigned long d_onetlb; /* times just one tlb on this
535 cpu was flushed */
536 unsigned long d_multmsg; /* interrupts with multiple
537 messages */
538 unsigned long d_nomsg; /* interrupts with no message */
539 unsigned long d_time; /* time spent on destination
540 side */
541 unsigned long d_requestee; /* number of messages
542 processed */
543 unsigned long d_retries; /* number of retry messages
544 processed */
545 unsigned long d_canceled; /* number of messages canceled
546 by retries */
547 unsigned long d_nocanceled; /* retries that found nothing
548 to cancel */
549 unsigned long d_resets; /* number of ipi-style requests
550 processed */
551 unsigned long d_rcanceled; /* number of messages canceled
552 by resets */
553 };
554
555 struct tunables {
556 int *tunp;
557 int deflt;
558 };
559
560 struct hub_and_pnode {
561 short uvhub;
562 short pnode;
563 };
564
565 struct socket_desc {
566 short num_cpus;
567 short cpu_number[MAX_CPUS_PER_SOCKET];
568 };
569
570 struct uvhub_desc {
571 unsigned short socket_mask;
572 short num_cpus;
573 short uvhub;
574 short pnode;
575 struct socket_desc socket[2];
576 };
577
578 /*
579 * one per-cpu; to locate the software tables
580 */
581 struct bau_control {
582 struct bau_desc *descriptor_base;
583 struct bau_pq_entry *queue_first;
584 struct bau_pq_entry *queue_last;
585 struct bau_pq_entry *bau_msg_head;
586 struct bau_control *uvhub_master;
587 struct bau_control *socket_master;
588 struct ptc_stats *statp;
589 cpumask_t *cpumask;
590 unsigned long timeout_interval;
591 unsigned long set_bau_on_time;
592 atomic_t active_descriptor_count;
593 int plugged_tries;
594 int timeout_tries;
595 int ipi_attempts;
596 int conseccompletes;
597 short nobau;
598 short baudisabled;
599 short cpu;
600 short osnode;
601 short uvhub_cpu;
602 short uvhub;
603 short uvhub_version;
604 short cpus_in_socket;
605 short cpus_in_uvhub;
606 short partition_base_pnode;
607 short busy; /* all were busy (war) */
608 unsigned short message_number;
609 unsigned short uvhub_quiesce;
610 short socket_acknowledge_count[DEST_Q_SIZE];
611 cycles_t send_message;
612 cycles_t period_end;
613 cycles_t period_time;
614 spinlock_t uvhub_lock;
615 spinlock_t queue_lock;
616 spinlock_t disable_lock;
617 /* tunables */
618 int max_concurr;
619 int max_concurr_const;
620 int plugged_delay;
621 int plugsb4reset;
622 int timeoutsb4reset;
623 int ipi_reset_limit;
624 int complete_threshold;
625 int cong_response_us;
626 int cong_reps;
627 cycles_t disabled_period;
628 int period_giveups;
629 int giveup_limit;
630 long period_requests;
631 struct hub_and_pnode *thp;
632 };
633
634 static inline unsigned long read_mmr_uv2_status(void)
635 {
636 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
637 }
638
639 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
640 {
641 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
642 }
643
644 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
645 {
646 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
647 }
648
649 static inline void write_mmr_activation(unsigned long index)
650 {
651 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
652 }
653
654 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
655 {
656 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
657 }
658
659 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
660 {
661 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
662 }
663
664 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
665 {
666 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
667 }
668
669 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
670 {
671 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
672 }
673
674 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
675 {
676 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
677 }
678
679 static inline unsigned long read_mmr_misc_control(int pnode)
680 {
681 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
682 }
683
684 static inline void write_mmr_sw_ack(unsigned long mr)
685 {
686 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
687 }
688
689 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
690 {
691 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
692 }
693
694 static inline unsigned long read_mmr_sw_ack(void)
695 {
696 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
697 }
698
699 static inline unsigned long read_gmmr_sw_ack(int pnode)
700 {
701 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
702 }
703
704 static inline void write_mmr_data_config(int pnode, unsigned long mr)
705 {
706 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
707 }
708
709 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
710 {
711 return constant_test_bit(uvhub, &dstp->bits[0]);
712 }
713 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
714 {
715 __set_bit(pnode, &dstp->bits[0]);
716 }
717 static inline void bau_uvhubs_clear(struct pnmask *dstp,
718 int nbits)
719 {
720 bitmap_zero(&dstp->bits[0], nbits);
721 }
722 static inline int bau_uvhub_weight(struct pnmask *dstp)
723 {
724 return bitmap_weight((unsigned long *)&dstp->bits[0],
725 UV_DISTRIBUTION_SIZE);
726 }
727
728 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
729 {
730 bitmap_zero(&dstp->bits, nbits);
731 }
732
733 extern void uv_bau_message_intr1(void);
734 #ifdef CONFIG_TRACING
735 #define trace_uv_bau_message_intr1 uv_bau_message_intr1
736 #endif
737 extern void uv_bau_timeout_intr1(void);
738
739 struct atomic_short {
740 short counter;
741 };
742
743 /*
744 * atomic_read_short - read a short atomic variable
745 * @v: pointer of type atomic_short
746 *
747 * Atomically reads the value of @v.
748 */
749 static inline int atomic_read_short(const struct atomic_short *v)
750 {
751 return v->counter;
752 }
753
754 /*
755 * atom_asr - add and return a short int
756 * @i: short value to add
757 * @v: pointer of type atomic_short
758 *
759 * Atomically adds @i to @v and returns @i + @v
760 */
761 static inline int atom_asr(short i, struct atomic_short *v)
762 {
763 return i + xadd(&v->counter, i);
764 }
765
766 /*
767 * conditionally add 1 to *v, unless *v is >= u
768 * return 0 if we cannot add 1 to *v because it is >= u
769 * return 1 if we can add 1 to *v because it is < u
770 * the add is atomic
771 *
772 * This is close to atomic_add_unless(), but this allows the 'u' value
773 * to be lowered below the current 'v'. atomic_add_unless can only stop
774 * on equal.
775 */
776 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
777 {
778 spin_lock(lock);
779 if (atomic_read(v) >= u) {
780 spin_unlock(lock);
781 return 0;
782 }
783 atomic_inc(v);
784 spin_unlock(lock);
785 return 1;
786 }
787
788 #endif /* _ASM_X86_UV_UV_BAU_H */
Linux with added FPC-III support