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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / ata / ahci.c
blobefa328bf672479ff5199027a7961f059e0501649
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
58 };
59
60 enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_noncq,
65 board_ahci_nosntf,
66 board_ahci_yes_fbs,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
70 board_ahci_mcp77,
71 board_ahci_mcp89,
72 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 #ifdef CONFIG_PM
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
92 #endif
93
94 static struct scsi_host_template ahci_sht = {
95 AHCI_SHT("ahci"),
96 };
97
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
101 };
102
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
106 };
107
108 static const struct ata_port_info ahci_port_info[] = {
109 /* by features */
110 [board_ahci] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
115 },
116 [board_ahci_ign_iferr] = {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
122 },
123 [board_ahci_noncq] = {
124 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
130 [board_ahci_nosntf] = {
131 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_yes_fbs] = {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 /* by chipsets */
145 [board_ahci_mcp65] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 AHCI_HFLAG_YES_NCQ),
148 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_mcp77] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
160 [board_ahci_mcp89] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_mv] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
175 [board_ahci_sb600] = {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
183 },
184 [board_ahci_sb700] = { /* for SB700 and SB800 */
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_pmp_retry_srst_ops,
190 },
191 [board_ahci_vt8251] = {
192 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_vt8251_ops,
197 },
198 };
199
200 static const struct pci_device_id ahci_pci_tbl[] = {
201 /* Intel */
202 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
203 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
204 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
205 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
206 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
207 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
208 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
209 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
212 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
213 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
216 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
230 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
232 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
237 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
245 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
249 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
250 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
253 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
256 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
261 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
263 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
269 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
271 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
295 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
299 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
303 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
305 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
307
308 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
309 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
310 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
311 /* JMicron 362B and 362C have an AHCI function with IDE class code */
312 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
313 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
314
315 /* ATI */
316 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
317 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
323
324 /* AMD */
325 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
326 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
327 /* AMD is using RAID class only for ahci controllers */
328 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
329 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
330
331 /* VIA */
332 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
333 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
334
335 /* NVIDIA */
336 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
420
421 /* SiS */
422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
425
426 /* ST Microelectronics */
427 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
428
429 /* Marvell */
430 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
431 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
433 .class = PCI_CLASS_STORAGE_SATA_AHCI,
434 .class_mask = 0xffffff,
435 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
438 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
439 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
440 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
442 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
448 .driver_data = board_ahci_yes_fbs },
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
450 .driver_data = board_ahci_yes_fbs },
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
452 .driver_data = board_ahci_yes_fbs },
453 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
454 .driver_data = board_ahci_yes_fbs },
455
456 /* Promise */
457 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
458 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
459
460 /* Asmedia */
461 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
462 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
463 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
464 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
465
466 /*
467 * Samsung SSDs found on some macbooks. NCQ times out.
468 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
469 */
470 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
471
472 /* Enmotus */
473 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
474
475 /* Generic, PCI class code for AHCI */
476 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
477 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
478
479 { } /* terminate list */
480 };
481
482
483 static struct pci_driver ahci_pci_driver = {
484 .name = DRV_NAME,
485 .id_table = ahci_pci_tbl,
486 .probe = ahci_init_one,
487 .remove = ata_pci_remove_one,
488 #ifdef CONFIG_PM
489 .suspend = ahci_pci_device_suspend,
490 .resume = ahci_pci_device_resume,
491 #endif
492 };
493
494 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
495 static int marvell_enable;
496 #else
497 static int marvell_enable = 1;
498 #endif
499 module_param(marvell_enable, int, 0644);
500 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
501
502
503 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
504 struct ahci_host_priv *hpriv)
505 {
506 unsigned int force_port_map = 0;
507 unsigned int mask_port_map = 0;
508
509 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
510 dev_info(&pdev->dev, "JMB361 has only one port\n");
511 force_port_map = 1;
512 }
513
514 /*
515 * Temporary Marvell 6145 hack: PATA port presence
516 * is asserted through the standard AHCI port
517 * presence register, as bit 4 (counting from 0)
518 */
519 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
520 if (pdev->device == 0x6121)
521 mask_port_map = 0x3;
522 else
523 mask_port_map = 0xf;
524 dev_info(&pdev->dev,
525 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
526 }
527
528 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
529 mask_port_map);
530 }
531
532 static int ahci_pci_reset_controller(struct ata_host *host)
533 {
534 struct pci_dev *pdev = to_pci_dev(host->dev);
535
536 ahci_reset_controller(host);
537
538 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
539 struct ahci_host_priv *hpriv = host->private_data;
540 u16 tmp16;
541
542 /* configure PCS */
543 pci_read_config_word(pdev, 0x92, &tmp16);
544 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
545 tmp16 |= hpriv->port_map;
546 pci_write_config_word(pdev, 0x92, tmp16);
547 }
548 }
549
550 return 0;
551 }
552
553 static void ahci_pci_init_controller(struct ata_host *host)
554 {
555 struct ahci_host_priv *hpriv = host->private_data;
556 struct pci_dev *pdev = to_pci_dev(host->dev);
557 void __iomem *port_mmio;
558 u32 tmp;
559 int mv;
560
561 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
562 if (pdev->device == 0x6121)
563 mv = 2;
564 else
565 mv = 4;
566 port_mmio = __ahci_port_base(host, mv);
567
568 writel(0, port_mmio + PORT_IRQ_MASK);
569
570 /* clear port IRQ */
571 tmp = readl(port_mmio + PORT_IRQ_STAT);
572 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
573 if (tmp)
574 writel(tmp, port_mmio + PORT_IRQ_STAT);
575 }
576
577 ahci_init_controller(host);
578 }
579
580 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
581 unsigned long deadline)
582 {
583 struct ata_port *ap = link->ap;
584 bool online;
585 int rc;
586
587 DPRINTK("ENTER\n");
588
589 ahci_stop_engine(ap);
590
591 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
592 deadline, &online, NULL);
593
594 ahci_start_engine(ap);
595
596 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
597
598 /* vt8251 doesn't clear BSY on signature FIS reception,
599 * request follow-up softreset.
600 */
601 return online ? -EAGAIN : rc;
602 }
603
604 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
605 unsigned long deadline)
606 {
607 struct ata_port *ap = link->ap;
608 struct ahci_port_priv *pp = ap->private_data;
609 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
610 struct ata_taskfile tf;
611 bool online;
612 int rc;
613
614 ahci_stop_engine(ap);
615
616 /* clear D2H reception area to properly wait for D2H FIS */
617 ata_tf_init(link->device, &tf);
618 tf.command = ATA_BUSY;
619 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
620
621 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
622 deadline, &online, NULL);
623
624 ahci_start_engine(ap);
625
626 /* The pseudo configuration device on SIMG4726 attached to
627 * ASUS P5W-DH Deluxe doesn't send signature FIS after
628 * hardreset if no device is attached to the first downstream
629 * port && the pseudo device locks up on SRST w/ PMP==0. To
630 * work around this, wait for !BSY only briefly. If BSY isn't
631 * cleared, perform CLO and proceed to IDENTIFY (achieved by
632 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
633 *
634 * Wait for two seconds. Devices attached to downstream port
635 * which can't process the following IDENTIFY after this will
636 * have to be reset again. For most cases, this should
637 * suffice while making probing snappish enough.
638 */
639 if (online) {
640 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
641 ahci_check_ready);
642 if (rc)
643 ahci_kick_engine(ap);
644 }
645 return rc;
646 }
647
648 #ifdef CONFIG_PM
649 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
650 {
651 struct ata_host *host = pci_get_drvdata(pdev);
652 struct ahci_host_priv *hpriv = host->private_data;
653 void __iomem *mmio = hpriv->mmio;
654 u32 ctl;
655
656 if (mesg.event & PM_EVENT_SUSPEND &&
657 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
658 dev_err(&pdev->dev,
659 "BIOS update required for suspend/resume\n");
660 return -EIO;
661 }
662
663 if (mesg.event & PM_EVENT_SLEEP) {
664 /* AHCI spec rev1.1 section 8.3.3:
665 * Software must disable interrupts prior to requesting a
666 * transition of the HBA to D3 state.
667 */
668 ctl = readl(mmio + HOST_CTL);
669 ctl &= ~HOST_IRQ_EN;
670 writel(ctl, mmio + HOST_CTL);
671 readl(mmio + HOST_CTL); /* flush */
672 }
673
674 return ata_pci_device_suspend(pdev, mesg);
675 }
676
677 static int ahci_pci_device_resume(struct pci_dev *pdev)
678 {
679 struct ata_host *host = pci_get_drvdata(pdev);
680 int rc;
681
682 rc = ata_pci_device_do_resume(pdev);
683 if (rc)
684 return rc;
685
686 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
687 rc = ahci_pci_reset_controller(host);
688 if (rc)
689 return rc;
690
691 ahci_pci_init_controller(host);
692 }
693
694 ata_host_resume(host);
695
696 return 0;
697 }
698 #endif
699
700 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
701 {
702 int rc;
703
704 /*
705 * If the device fixup already set the dma_mask to some non-standard
706 * value, don't extend it here. This happens on STA2X11, for example.
707 */
708 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
709 return 0;
710
711 if (using_dac &&
712 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
713 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
714 if (rc) {
715 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
716 if (rc) {
717 dev_err(&pdev->dev,
718 "64-bit DMA enable failed\n");
719 return rc;
720 }
721 }
722 } else {
723 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
724 if (rc) {
725 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
726 return rc;
727 }
728 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
729 if (rc) {
730 dev_err(&pdev->dev,
731 "32-bit consistent DMA enable failed\n");
732 return rc;
733 }
734 }
735 return 0;
736 }
737
738 static void ahci_pci_print_info(struct ata_host *host)
739 {
740 struct pci_dev *pdev = to_pci_dev(host->dev);
741 u16 cc;
742 const char *scc_s;
743
744 pci_read_config_word(pdev, 0x0a, &cc);
745 if (cc == PCI_CLASS_STORAGE_IDE)
746 scc_s = "IDE";
747 else if (cc == PCI_CLASS_STORAGE_SATA)
748 scc_s = "SATA";
749 else if (cc == PCI_CLASS_STORAGE_RAID)
750 scc_s = "RAID";
751 else
752 scc_s = "unknown";
753
754 ahci_print_info(host, scc_s);
755 }
756
757 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
758 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
759 * support PMP and the 4726 either directly exports the device
760 * attached to the first downstream port or acts as a hardware storage
761 * controller and emulate a single ATA device (can be RAID 0/1 or some
762 * other configuration).
763 *
764 * When there's no device attached to the first downstream port of the
765 * 4726, "Config Disk" appears, which is a pseudo ATA device to
766 * configure the 4726. However, ATA emulation of the device is very
767 * lame. It doesn't send signature D2H Reg FIS after the initial
768 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
769 *
770 * The following function works around the problem by always using
771 * hardreset on the port and not depending on receiving signature FIS
772 * afterward. If signature FIS isn't received soon, ATA class is
773 * assumed without follow-up softreset.
774 */
775 static void ahci_p5wdh_workaround(struct ata_host *host)
776 {
777 static struct dmi_system_id sysids[] = {
778 {
779 .ident = "P5W DH Deluxe",
780 .matches = {
781 DMI_MATCH(DMI_SYS_VENDOR,
782 "ASUSTEK COMPUTER INC"),
783 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
784 },
785 },
786 { }
787 };
788 struct pci_dev *pdev = to_pci_dev(host->dev);
789
790 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
791 dmi_check_system(sysids)) {
792 struct ata_port *ap = host->ports[1];
793
794 dev_info(&pdev->dev,
795 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
796
797 ap->ops = &ahci_p5wdh_ops;
798 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
799 }
800 }
801
802 /* only some SB600 ahci controllers can do 64bit DMA */
803 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
804 {
805 static const struct dmi_system_id sysids[] = {
806 /*
807 * The oldest version known to be broken is 0901 and
808 * working is 1501 which was released on 2007-10-26.
809 * Enable 64bit DMA on 1501 and anything newer.
810 *
811 * Please read bko#9412 for more info.
812 */
813 {
814 .ident = "ASUS M2A-VM",
815 .matches = {
816 DMI_MATCH(DMI_BOARD_VENDOR,
817 "ASUSTeK Computer INC."),
818 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
819 },
820 .driver_data = "20071026", /* yyyymmdd */
821 },
822 /*
823 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
824 * support 64bit DMA.
825 *
826 * BIOS versions earlier than 1.5 had the Manufacturer DMI
827 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
828 * This spelling mistake was fixed in BIOS version 1.5, so
829 * 1.5 and later have the Manufacturer as
830 * "MICRO-STAR INTERNATIONAL CO.,LTD".
831 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
832 *
833 * BIOS versions earlier than 1.9 had a Board Product Name
834 * DMI field of "MS-7376". This was changed to be
835 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
836 * match on DMI_BOARD_NAME of "MS-7376".
837 */
838 {
839 .ident = "MSI K9A2 Platinum",
840 .matches = {
841 DMI_MATCH(DMI_BOARD_VENDOR,
842 "MICRO-STAR INTER"),
843 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
844 },
845 },
846 /*
847 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
848 * 64bit DMA.
849 *
850 * This board also had the typo mentioned above in the
851 * Manufacturer DMI field (fixed in BIOS version 1.5), so
852 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
853 */
854 {
855 .ident = "MSI K9AGM2",
856 .matches = {
857 DMI_MATCH(DMI_BOARD_VENDOR,
858 "MICRO-STAR INTER"),
859 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
860 },
861 },
862 /*
863 * All BIOS versions for the Asus M3A support 64bit DMA.
864 * (all release versions from 0301 to 1206 were tested)
865 */
866 {
867 .ident = "ASUS M3A",
868 .matches = {
869 DMI_MATCH(DMI_BOARD_VENDOR,
870 "ASUSTeK Computer INC."),
871 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
872 },
873 },
874 { }
875 };
876 const struct dmi_system_id *match;
877 int year, month, date;
878 char buf[9];
879
880 match = dmi_first_match(sysids);
881 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
882 !match)
883 return false;
884
885 if (!match->driver_data)
886 goto enable_64bit;
887
888 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
889 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
890
891 if (strcmp(buf, match->driver_data) >= 0)
892 goto enable_64bit;
893 else {
894 dev_warn(&pdev->dev,
895 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
896 match->ident);
897 return false;
898 }
899
900 enable_64bit:
901 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
902 return true;
903 }
904
905 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
906 {
907 static const struct dmi_system_id broken_systems[] = {
908 {
909 .ident = "HP Compaq nx6310",
910 .matches = {
911 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
912 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
913 },
914 /* PCI slot number of the controller */
915 .driver_data = (void *)0x1FUL,
916 },
917 {
918 .ident = "HP Compaq 6720s",
919 .matches = {
920 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
921 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
922 },
923 /* PCI slot number of the controller */
924 .driver_data = (void *)0x1FUL,
925 },
926
927 { } /* terminate list */
928 };
929 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
930
931 if (dmi) {
932 unsigned long slot = (unsigned long)dmi->driver_data;
933 /* apply the quirk only to on-board controllers */
934 return slot == PCI_SLOT(pdev->devfn);
935 }
936
937 return false;
938 }
939
940 static bool ahci_broken_suspend(struct pci_dev *pdev)
941 {
942 static const struct dmi_system_id sysids[] = {
943 /*
944 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
945 * to the harddisk doesn't become online after
946 * resuming from STR. Warn and fail suspend.
947 *
948 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
949 *
950 * Use dates instead of versions to match as HP is
951 * apparently recycling both product and version
952 * strings.
953 *
954 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
955 */
956 {
957 .ident = "dv4",
958 .matches = {
959 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
960 DMI_MATCH(DMI_PRODUCT_NAME,
961 "HP Pavilion dv4 Notebook PC"),
962 },
963 .driver_data = "20090105", /* F.30 */
964 },
965 {
966 .ident = "dv5",
967 .matches = {
968 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
969 DMI_MATCH(DMI_PRODUCT_NAME,
970 "HP Pavilion dv5 Notebook PC"),
971 },
972 .driver_data = "20090506", /* F.16 */
973 },
974 {
975 .ident = "dv6",
976 .matches = {
977 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
978 DMI_MATCH(DMI_PRODUCT_NAME,
979 "HP Pavilion dv6 Notebook PC"),
980 },
981 .driver_data = "20090423", /* F.21 */
982 },
983 {
984 .ident = "HDX18",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
987 DMI_MATCH(DMI_PRODUCT_NAME,
988 "HP HDX18 Notebook PC"),
989 },
990 .driver_data = "20090430", /* F.23 */
991 },
992 /*
993 * Acer eMachines G725 has the same problem. BIOS
994 * V1.03 is known to be broken. V3.04 is known to
995 * work. Between, there are V1.06, V2.06 and V3.03
996 * that we don't have much idea about. For now,
997 * blacklist anything older than V3.04.
998 *
999 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1000 */
1001 {
1002 .ident = "G725",
1003 .matches = {
1004 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1005 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1006 },
1007 .driver_data = "20091216", /* V3.04 */
1008 },
1009 { } /* terminate list */
1010 };
1011 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1012 int year, month, date;
1013 char buf[9];
1014
1015 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1016 return false;
1017
1018 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1019 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1020
1021 return strcmp(buf, dmi->driver_data) < 0;
1022 }
1023
1024 static bool ahci_broken_online(struct pci_dev *pdev)
1025 {
1026 #define ENCODE_BUSDEVFN(bus, slot, func) \
1027 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1028 static const struct dmi_system_id sysids[] = {
1029 /*
1030 * There are several gigabyte boards which use
1031 * SIMG5723s configured as hardware RAID. Certain
1032 * 5723 firmware revisions shipped there keep the link
1033 * online but fail to answer properly to SRST or
1034 * IDENTIFY when no device is attached downstream
1035 * causing libata to retry quite a few times leading
1036 * to excessive detection delay.
1037 *
1038 * As these firmwares respond to the second reset try
1039 * with invalid device signature, considering unknown
1040 * sig as offline works around the problem acceptably.
1041 */
1042 {
1043 .ident = "EP45-DQ6",
1044 .matches = {
1045 DMI_MATCH(DMI_BOARD_VENDOR,
1046 "Gigabyte Technology Co., Ltd."),
1047 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1048 },
1049 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1050 },
1051 {
1052 .ident = "EP45-DS5",
1053 .matches = {
1054 DMI_MATCH(DMI_BOARD_VENDOR,
1055 "Gigabyte Technology Co., Ltd."),
1056 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1057 },
1058 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1059 },
1060 { } /* terminate list */
1061 };
1062 #undef ENCODE_BUSDEVFN
1063 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1064 unsigned int val;
1065
1066 if (!dmi)
1067 return false;
1068
1069 val = (unsigned long)dmi->driver_data;
1070
1071 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1072 }
1073
1074 #ifdef CONFIG_ATA_ACPI
1075 static void ahci_gtf_filter_workaround(struct ata_host *host)
1076 {
1077 static const struct dmi_system_id sysids[] = {
1078 /*
1079 * Aspire 3810T issues a bunch of SATA enable commands
1080 * via _GTF including an invalid one and one which is
1081 * rejected by the device. Among the successful ones
1082 * is FPDMA non-zero offset enable which when enabled
1083 * only on the drive side leads to NCQ command
1084 * failures. Filter it out.
1085 */
1086 {
1087 .ident = "Aspire 3810T",
1088 .matches = {
1089 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1090 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1091 },
1092 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1093 },
1094 { }
1095 };
1096 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1097 unsigned int filter;
1098 int i;
1099
1100 if (!dmi)
1101 return;
1102
1103 filter = (unsigned long)dmi->driver_data;
1104 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1105 filter, dmi->ident);
1106
1107 for (i = 0; i < host->n_ports; i++) {
1108 struct ata_port *ap = host->ports[i];
1109 struct ata_link *link;
1110 struct ata_device *dev;
1111
1112 ata_for_each_link(link, ap, EDGE)
1113 ata_for_each_dev(dev, link, ALL)
1114 dev->gtf_filter |= filter;
1115 }
1116 }
1117 #else
1118 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1119 {}
1120 #endif
1121
1122 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1123 {
1124 int rc;
1125 unsigned int maxvec;
1126
1127 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1128 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1129 if (rc > 0) {
1130 if ((rc == maxvec) || (rc == 1))
1131 return rc;
1132 /*
1133 * Assume that advantage of multipe MSIs is negated,
1134 * so fallback to single MSI mode to save resources
1135 */
1136 pci_disable_msi(pdev);
1137 if (!pci_enable_msi(pdev))
1138 return 1;
1139 }
1140 }
1141
1142 pci_intx(pdev, 1);
1143 return 0;
1144 }
1145
1146 /**
1147 * ahci_host_activate - start AHCI host, request IRQs and register it
1148 * @host: target ATA host
1149 * @irq: base IRQ number to request
1150 * @n_msis: number of MSIs allocated for this host
1151 * @irq_handler: irq_handler used when requesting IRQs
1152 * @irq_flags: irq_flags used when requesting IRQs
1153 *
1154 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1155 * when multiple MSIs were allocated. That is one MSI per port, starting
1156 * from @irq.
1157 *
1158 * LOCKING:
1159 * Inherited from calling layer (may sleep).
1160 *
1161 * RETURNS:
1162 * 0 on success, -errno otherwise.
1163 */
1164 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1165 {
1166 int i, rc;
1167
1168 /* Sharing Last Message among several ports is not supported */
1169 if (n_msis < host->n_ports)
1170 return -EINVAL;
1171
1172 rc = ata_host_start(host);
1173 if (rc)
1174 return rc;
1175
1176 for (i = 0; i < host->n_ports; i++) {
1177 struct ahci_port_priv *pp = host->ports[i]->private_data;
1178
1179 /* Do not receive interrupts sent by dummy ports */
1180 if (!pp) {
1181 disable_irq(irq + i);
1182 continue;
1183 }
1184
1185 rc = devm_request_threaded_irq(host->dev, irq + i,
1186 ahci_hw_interrupt,
1187 ahci_thread_fn, IRQF_SHARED,
1188 pp->irq_desc, host->ports[i]);
1189 if (rc)
1190 goto out_free_irqs;
1191 }
1192
1193 for (i = 0; i < host->n_ports; i++)
1194 ata_port_desc(host->ports[i], "irq %d", irq + i);
1195
1196 rc = ata_host_register(host, &ahci_sht);
1197 if (rc)
1198 goto out_free_all_irqs;
1199
1200 return 0;
1201
1202 out_free_all_irqs:
1203 i = host->n_ports;
1204 out_free_irqs:
1205 for (i--; i >= 0; i--)
1206 devm_free_irq(host->dev, irq + i, host->ports[i]);
1207
1208 return rc;
1209 }
1210
1211 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1212 {
1213 unsigned int board_id = ent->driver_data;
1214 struct ata_port_info pi = ahci_port_info[board_id];
1215 const struct ata_port_info *ppi[] = { &pi, NULL };
1216 struct device *dev = &pdev->dev;
1217 struct ahci_host_priv *hpriv;
1218 struct ata_host *host;
1219 int n_ports, n_msis, i, rc;
1220 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1221
1222 VPRINTK("ENTER\n");
1223
1224 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1225
1226 ata_print_version_once(&pdev->dev, DRV_VERSION);
1227
1228 /* The AHCI driver can only drive the SATA ports, the PATA driver
1229 can drive them all so if both drivers are selected make sure
1230 AHCI stays out of the way */
1231 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1232 return -ENODEV;
1233
1234 /*
1235 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1236 * ahci, use ata_generic instead.
1237 */
1238 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1239 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1240 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1241 pdev->subsystem_device == 0xcb89)
1242 return -ENODEV;
1243
1244 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1245 * At the moment, we can only use the AHCI mode. Let the users know
1246 * that for SAS drives they're out of luck.
1247 */
1248 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1249 dev_info(&pdev->dev,
1250 "PDC42819 can only drive SATA devices with this driver\n");
1251
1252 /* Both Connext and Enmotus devices use non-standard BARs */
1253 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1254 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1255 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1256 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1257
1258 /* acquire resources */
1259 rc = pcim_enable_device(pdev);
1260 if (rc)
1261 return rc;
1262
1263 /* AHCI controllers often implement SFF compatible interface.
1264 * Grab all PCI BARs just in case.
1265 */
1266 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1267 if (rc == -EBUSY)
1268 pcim_pin_device(pdev);
1269 if (rc)
1270 return rc;
1271
1272 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1273 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1274 u8 map;
1275
1276 /* ICH6s share the same PCI ID for both piix and ahci
1277 * modes. Enabling ahci mode while MAP indicates
1278 * combined mode is a bad idea. Yield to ata_piix.
1279 */
1280 pci_read_config_byte(pdev, ICH_MAP, &map);
1281 if (map & 0x3) {
1282 dev_info(&pdev->dev,
1283 "controller is in combined mode, can't enable AHCI mode\n");
1284 return -ENODEV;
1285 }
1286 }
1287
1288 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1289 if (!hpriv)
1290 return -ENOMEM;
1291 hpriv->flags |= (unsigned long)pi.private_data;
1292
1293 /* MCP65 revision A1 and A2 can't do MSI */
1294 if (board_id == board_ahci_mcp65 &&
1295 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1296 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1297
1298 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1299 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1300 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1301
1302 /* only some SB600s can do 64bit DMA */
1303 if (ahci_sb600_enable_64bit(pdev))
1304 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1305
1306 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1307
1308 n_msis = ahci_init_interrupts(pdev, hpriv);
1309 if (n_msis > 1)
1310 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1311
1312 /* save initial config */
1313 ahci_pci_save_initial_config(pdev, hpriv);
1314
1315 /* prepare host */
1316 if (hpriv->cap & HOST_CAP_NCQ) {
1317 pi.flags |= ATA_FLAG_NCQ;
1318 /*
1319 * Auto-activate optimization is supposed to be
1320 * supported on all AHCI controllers indicating NCQ
1321 * capability, but it seems to be broken on some
1322 * chipsets including NVIDIAs.
1323 */
1324 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1325 pi.flags |= ATA_FLAG_FPDMA_AA;
1326
1327 /*
1328 * All AHCI controllers should be forward-compatible
1329 * with the new auxiliary field. This code should be
1330 * conditionalized if any buggy AHCI controllers are
1331 * encountered.
1332 */
1333 pi.flags |= ATA_FLAG_FPDMA_AUX;
1334 }
1335
1336 if (hpriv->cap & HOST_CAP_PMP)
1337 pi.flags |= ATA_FLAG_PMP;
1338
1339 ahci_set_em_messages(hpriv, &pi);
1340
1341 if (ahci_broken_system_poweroff(pdev)) {
1342 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1343 dev_info(&pdev->dev,
1344 "quirky BIOS, skipping spindown on poweroff\n");
1345 }
1346
1347 if (ahci_broken_suspend(pdev)) {
1348 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1349 dev_warn(&pdev->dev,
1350 "BIOS update required for suspend/resume\n");
1351 }
1352
1353 if (ahci_broken_online(pdev)) {
1354 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1355 dev_info(&pdev->dev,
1356 "online status unreliable, applying workaround\n");
1357 }
1358
1359 /* CAP.NP sometimes indicate the index of the last enabled
1360 * port, at other times, that of the last possible port, so
1361 * determining the maximum port number requires looking at
1362 * both CAP.NP and port_map.
1363 */
1364 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1365
1366 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1367 if (!host)
1368 return -ENOMEM;
1369 host->private_data = hpriv;
1370
1371 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1372 host->flags |= ATA_HOST_PARALLEL_SCAN;
1373 else
1374 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1375
1376 if (pi.flags & ATA_FLAG_EM)
1377 ahci_reset_em(host);
1378
1379 for (i = 0; i < host->n_ports; i++) {
1380 struct ata_port *ap = host->ports[i];
1381
1382 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1383 ata_port_pbar_desc(ap, ahci_pci_bar,
1384 0x100 + ap->port_no * 0x80, "port");
1385
1386 /* set enclosure management message type */
1387 if (ap->flags & ATA_FLAG_EM)
1388 ap->em_message_type = hpriv->em_msg_type;
1389
1390
1391 /* disabled/not-implemented port */
1392 if (!(hpriv->port_map & (1 << i)))
1393 ap->ops = &ata_dummy_port_ops;
1394 }
1395
1396 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1397 ahci_p5wdh_workaround(host);
1398
1399 /* apply gtf filter quirk */
1400 ahci_gtf_filter_workaround(host);
1401
1402 /* initialize adapter */
1403 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1404 if (rc)
1405 return rc;
1406
1407 rc = ahci_pci_reset_controller(host);
1408 if (rc)
1409 return rc;
1410
1411 ahci_pci_init_controller(host);
1412 ahci_pci_print_info(host);
1413
1414 pci_set_master(pdev);
1415
1416 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1417 return ahci_host_activate(host, pdev->irq, n_msis);
1418
1419 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1420 &ahci_sht);
1421 }
1422
1423 module_pci_driver(ahci_pci_driver);
1424
1425 MODULE_AUTHOR("Jeff Garzik");
1426 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1427 MODULE_LICENSE("GPL");
1428 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1429 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support