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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / ata / sata_mv.c
blobdc9d4b1ea4ec8ebe4d794346f84bc174a39533c9
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
42
43 /*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <linux/of.h>
69 #include <linux/of_irq.h>
70 #include <scsi/scsi_host.h>
71 #include <scsi/scsi_cmnd.h>
72 #include <scsi/scsi_device.h>
73 #include <linux/libata.h>
74
75 #define DRV_NAME "sata_mv"
76 #define DRV_VERSION "1.28"
77
78 /*
79 * module options
80 */
81
82 #ifdef CONFIG_PCI
83 static int msi;
84 module_param(msi, int, S_IRUGO);
85 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
86 #endif
87
88 static int irq_coalescing_io_count;
89 module_param(irq_coalescing_io_count, int, S_IRUGO);
90 MODULE_PARM_DESC(irq_coalescing_io_count,
91 "IRQ coalescing I/O count threshold (0..255)");
92
93 static int irq_coalescing_usecs;
94 module_param(irq_coalescing_usecs, int, S_IRUGO);
95 MODULE_PARM_DESC(irq_coalescing_usecs,
96 "IRQ coalescing time threshold in usecs");
97
98 enum {
99 /* BAR's are enumerated in terms of pci_resource_start() terms */
100 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
101 MV_IO_BAR = 2, /* offset 0x18: IO space */
102 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
103
104 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
105 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
106
107 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
108 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
109 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
110 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
111
112 MV_PCI_REG_BASE = 0,
113
114 /*
115 * Per-chip ("all ports") interrupt coalescing feature.
116 * This is only for GEN_II / GEN_IIE hardware.
117 *
118 * Coalescing defers the interrupt until either the IO_THRESHOLD
119 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
120 */
121 COAL_REG_BASE = 0x18000,
122 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
123 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
124
125 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
126 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
127
128 /*
129 * Registers for the (unused here) transaction coalescing feature:
130 */
131 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
132 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
133
134 SATAHC0_REG_BASE = 0x20000,
135 FLASH_CTL = 0x1046c,
136 GPIO_PORT_CTL = 0x104f0,
137 RESET_CFG = 0x180d8,
138
139 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
140 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
141 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
142 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
143
144 MV_MAX_Q_DEPTH = 32,
145 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
146
147 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
148 * CRPB needs alignment on a 256B boundary. Size == 256B
149 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
150 */
151 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
152 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
153 MV_MAX_SG_CT = 256,
154 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
155
156 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
157 MV_PORT_HC_SHIFT = 2,
158 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
159 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
160 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
161
162 /* Host Flags */
163 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
164
165 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
166
167 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
168
169 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
170 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
171
172 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
173
174 CRQB_FLAG_READ = (1 << 0),
175 CRQB_TAG_SHIFT = 1,
176 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
177 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
178 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
179 CRQB_CMD_ADDR_SHIFT = 8,
180 CRQB_CMD_CS = (0x2 << 11),
181 CRQB_CMD_LAST = (1 << 15),
182
183 CRPB_FLAG_STATUS_SHIFT = 8,
184 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
185 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
186
187 EPRD_FLAG_END_OF_TBL = (1 << 31),
188
189 /* PCI interface registers */
190
191 MV_PCI_COMMAND = 0xc00,
192 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
193 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
194
195 PCI_MAIN_CMD_STS = 0xd30,
196 STOP_PCI_MASTER = (1 << 2),
197 PCI_MASTER_EMPTY = (1 << 3),
198 GLOB_SFT_RST = (1 << 4),
199
200 MV_PCI_MODE = 0xd00,
201 MV_PCI_MODE_MASK = 0x30,
202
203 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
204 MV_PCI_DISC_TIMER = 0xd04,
205 MV_PCI_MSI_TRIGGER = 0xc38,
206 MV_PCI_SERR_MASK = 0xc28,
207 MV_PCI_XBAR_TMOUT = 0x1d04,
208 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
209 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
210 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
211 MV_PCI_ERR_COMMAND = 0x1d50,
212
213 PCI_IRQ_CAUSE = 0x1d58,
214 PCI_IRQ_MASK = 0x1d5c,
215 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
216
217 PCIE_IRQ_CAUSE = 0x1900,
218 PCIE_IRQ_MASK = 0x1910,
219 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
220
221 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
222 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
223 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
224 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
225 SOC_HC_MAIN_IRQ_MASK = 0x20024,
226 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
227 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
228 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
229 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
230 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
231 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
232 PCI_ERR = (1 << 18),
233 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
234 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
235 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
236 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
237 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
238 GPIO_INT = (1 << 22),
239 SELF_INT = (1 << 23),
240 TWSI_INT = (1 << 24),
241 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
242 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
243 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
244
245 /* SATAHC registers */
246 HC_CFG = 0x00,
247
248 HC_IRQ_CAUSE = 0x14,
249 DMA_IRQ = (1 << 0), /* shift by port # */
250 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
251 DEV_IRQ = (1 << 8), /* shift by port # */
252
253 /*
254 * Per-HC (Host-Controller) interrupt coalescing feature.
255 * This is present on all chip generations.
256 *
257 * Coalescing defers the interrupt until either the IO_THRESHOLD
258 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
259 */
260 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
261 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
262
263 SOC_LED_CTRL = 0x2c,
264 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
265 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
266 /* with dev activity LED */
267
268 /* Shadow block registers */
269 SHD_BLK = 0x100,
270 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
271
272 /* SATA registers */
273 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
274 SATA_ACTIVE = 0x350,
275 FIS_IRQ_CAUSE = 0x364,
276 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
277
278 LTMODE = 0x30c, /* requires read-after-write */
279 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
280
281 PHY_MODE2 = 0x330,
282 PHY_MODE3 = 0x310,
283
284 PHY_MODE4 = 0x314, /* requires read-after-write */
285 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
286 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
287 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
288 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
289
290 SATA_IFCTL = 0x344,
291 SATA_TESTCTL = 0x348,
292 SATA_IFSTAT = 0x34c,
293 VENDOR_UNIQUE_FIS = 0x35c,
294
295 FISCFG = 0x360,
296 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
297 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
298
299 PHY_MODE9_GEN2 = 0x398,
300 PHY_MODE9_GEN1 = 0x39c,
301 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
302
303 MV5_PHY_MODE = 0x74,
304 MV5_LTMODE = 0x30,
305 MV5_PHY_CTL = 0x0C,
306 SATA_IFCFG = 0x050,
307 LP_PHY_CTL = 0x058,
308
309 MV_M2_PREAMP_MASK = 0x7e0,
310
311 /* Port registers */
312 EDMA_CFG = 0,
313 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
314 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
315 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
316 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
317 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
318 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
319 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
320
321 EDMA_ERR_IRQ_CAUSE = 0x8,
322 EDMA_ERR_IRQ_MASK = 0xc,
323 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
324 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
325 EDMA_ERR_DEV = (1 << 2), /* device error */
326 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
327 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
328 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
329 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
330 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
331 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
332 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
333 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
334 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
335 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
336 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
337
338 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
339 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
340 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
341 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
342 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
343
344 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
345
346 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
347 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
348 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
349 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
350 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
351 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
352
353 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
354
355 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
356 EDMA_ERR_OVERRUN_5 = (1 << 5),
357 EDMA_ERR_UNDERRUN_5 = (1 << 6),
358
359 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
360 EDMA_ERR_LNK_CTRL_RX_1 |
361 EDMA_ERR_LNK_CTRL_RX_3 |
362 EDMA_ERR_LNK_CTRL_TX,
363
364 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
365 EDMA_ERR_PRD_PAR |
366 EDMA_ERR_DEV_DCON |
367 EDMA_ERR_DEV_CON |
368 EDMA_ERR_SERR |
369 EDMA_ERR_SELF_DIS |
370 EDMA_ERR_CRQB_PAR |
371 EDMA_ERR_CRPB_PAR |
372 EDMA_ERR_INTRL_PAR |
373 EDMA_ERR_IORDY |
374 EDMA_ERR_LNK_CTRL_RX_2 |
375 EDMA_ERR_LNK_DATA_RX |
376 EDMA_ERR_LNK_DATA_TX |
377 EDMA_ERR_TRANS_PROTO,
378
379 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
380 EDMA_ERR_PRD_PAR |
381 EDMA_ERR_DEV_DCON |
382 EDMA_ERR_DEV_CON |
383 EDMA_ERR_OVERRUN_5 |
384 EDMA_ERR_UNDERRUN_5 |
385 EDMA_ERR_SELF_DIS_5 |
386 EDMA_ERR_CRQB_PAR |
387 EDMA_ERR_CRPB_PAR |
388 EDMA_ERR_INTRL_PAR |
389 EDMA_ERR_IORDY,
390
391 EDMA_REQ_Q_BASE_HI = 0x10,
392 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
393
394 EDMA_REQ_Q_OUT_PTR = 0x18,
395 EDMA_REQ_Q_PTR_SHIFT = 5,
396
397 EDMA_RSP_Q_BASE_HI = 0x1c,
398 EDMA_RSP_Q_IN_PTR = 0x20,
399 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
400 EDMA_RSP_Q_PTR_SHIFT = 3,
401
402 EDMA_CMD = 0x28, /* EDMA command register */
403 EDMA_EN = (1 << 0), /* enable EDMA */
404 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
405 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
406
407 EDMA_STATUS = 0x30, /* EDMA engine status */
408 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
409 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
410
411 EDMA_IORDY_TMOUT = 0x34,
412 EDMA_ARB_CFG = 0x38,
413
414 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
415 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
416
417 BMDMA_CMD = 0x224, /* bmdma command register */
418 BMDMA_STATUS = 0x228, /* bmdma status register */
419 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
420 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
421
422 /* Host private flags (hp_flags) */
423 MV_HP_FLAG_MSI = (1 << 0),
424 MV_HP_ERRATA_50XXB0 = (1 << 1),
425 MV_HP_ERRATA_50XXB2 = (1 << 2),
426 MV_HP_ERRATA_60X1B2 = (1 << 3),
427 MV_HP_ERRATA_60X1C0 = (1 << 4),
428 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
429 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
430 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
431 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
432 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
433 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
434 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
435 MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */
436
437 /* Port private flags (pp_flags) */
438 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
439 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
440 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
441 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
442 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
443 };
444
445 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
446 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
447 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
448 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
449 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
450
451 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
452 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
453
454 enum {
455 /* DMA boundary 0xffff is required by the s/g splitting
456 * we need on /length/ in mv_fill-sg().
457 */
458 MV_DMA_BOUNDARY = 0xffffU,
459
460 /* mask of register bits containing lower 32 bits
461 * of EDMA request queue DMA address
462 */
463 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
464
465 /* ditto, for response queue */
466 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
467 };
468
469 enum chip_type {
470 chip_504x,
471 chip_508x,
472 chip_5080,
473 chip_604x,
474 chip_608x,
475 chip_6042,
476 chip_7042,
477 chip_soc,
478 };
479
480 /* Command ReQuest Block: 32B */
481 struct mv_crqb {
482 __le32 sg_addr;
483 __le32 sg_addr_hi;
484 __le16 ctrl_flags;
485 __le16 ata_cmd[11];
486 };
487
488 struct mv_crqb_iie {
489 __le32 addr;
490 __le32 addr_hi;
491 __le32 flags;
492 __le32 len;
493 __le32 ata_cmd[4];
494 };
495
496 /* Command ResPonse Block: 8B */
497 struct mv_crpb {
498 __le16 id;
499 __le16 flags;
500 __le32 tmstmp;
501 };
502
503 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
504 struct mv_sg {
505 __le32 addr;
506 __le32 flags_size;
507 __le32 addr_hi;
508 __le32 reserved;
509 };
510
511 /*
512 * We keep a local cache of a few frequently accessed port
513 * registers here, to avoid having to read them (very slow)
514 * when switching between EDMA and non-EDMA modes.
515 */
516 struct mv_cached_regs {
517 u32 fiscfg;
518 u32 ltmode;
519 u32 haltcond;
520 u32 unknown_rsvd;
521 };
522
523 struct mv_port_priv {
524 struct mv_crqb *crqb;
525 dma_addr_t crqb_dma;
526 struct mv_crpb *crpb;
527 dma_addr_t crpb_dma;
528 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
529 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
530
531 unsigned int req_idx;
532 unsigned int resp_idx;
533
534 u32 pp_flags;
535 struct mv_cached_regs cached;
536 unsigned int delayed_eh_pmp_map;
537 };
538
539 struct mv_port_signal {
540 u32 amps;
541 u32 pre;
542 };
543
544 struct mv_host_priv {
545 u32 hp_flags;
546 unsigned int board_idx;
547 u32 main_irq_mask;
548 struct mv_port_signal signal[8];
549 const struct mv_hw_ops *ops;
550 int n_ports;
551 void __iomem *base;
552 void __iomem *main_irq_cause_addr;
553 void __iomem *main_irq_mask_addr;
554 u32 irq_cause_offset;
555 u32 irq_mask_offset;
556 u32 unmask_all_irqs;
557
558 /*
559 * Needed on some devices that require their clocks to be enabled.
560 * These are optional: if the platform device does not have any
561 * clocks, they won't be used. Also, if the underlying hardware
562 * does not support the common clock framework (CONFIG_HAVE_CLK=n),
563 * all the clock operations become no-ops (see clk.h).
564 */
565 struct clk *clk;
566 struct clk **port_clks;
567 /*
568 * These consistent DMA memory pools give us guaranteed
569 * alignment for hardware-accessed data structures,
570 * and less memory waste in accomplishing the alignment.
571 */
572 struct dma_pool *crqb_pool;
573 struct dma_pool *crpb_pool;
574 struct dma_pool *sg_tbl_pool;
575 };
576
577 struct mv_hw_ops {
578 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 unsigned int port);
580 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
581 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
582 void __iomem *mmio);
583 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
584 unsigned int n_hc);
585 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
586 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
587 };
588
589 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
590 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
591 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
592 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
593 static int mv_port_start(struct ata_port *ap);
594 static void mv_port_stop(struct ata_port *ap);
595 static int mv_qc_defer(struct ata_queued_cmd *qc);
596 static void mv_qc_prep(struct ata_queued_cmd *qc);
597 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
598 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
599 static int mv_hardreset(struct ata_link *link, unsigned int *class,
600 unsigned long deadline);
601 static void mv_eh_freeze(struct ata_port *ap);
602 static void mv_eh_thaw(struct ata_port *ap);
603 static void mv6_dev_config(struct ata_device *dev);
604
605 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 unsigned int port);
607 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
608 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
609 void __iomem *mmio);
610 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
611 unsigned int n_hc);
612 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
613 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
614
615 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
616 unsigned int port);
617 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
618 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
619 void __iomem *mmio);
620 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
621 unsigned int n_hc);
622 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
623 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
624 void __iomem *mmio);
625 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
626 void __iomem *mmio);
627 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
628 void __iomem *mmio, unsigned int n_hc);
629 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
630 void __iomem *mmio);
631 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
632 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
633 void __iomem *mmio, unsigned int port);
634 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
635 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
636 unsigned int port_no);
637 static int mv_stop_edma(struct ata_port *ap);
638 static int mv_stop_edma_engine(void __iomem *port_mmio);
639 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
640
641 static void mv_pmp_select(struct ata_port *ap, int pmp);
642 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
643 unsigned long deadline);
644 static int mv_softreset(struct ata_link *link, unsigned int *class,
645 unsigned long deadline);
646 static void mv_pmp_error_handler(struct ata_port *ap);
647 static void mv_process_crpb_entries(struct ata_port *ap,
648 struct mv_port_priv *pp);
649
650 static void mv_sff_irq_clear(struct ata_port *ap);
651 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
652 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
653 static void mv_bmdma_start(struct ata_queued_cmd *qc);
654 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
655 static u8 mv_bmdma_status(struct ata_port *ap);
656 static u8 mv_sff_check_status(struct ata_port *ap);
657
658 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
659 * because we have to allow room for worst case splitting of
660 * PRDs for 64K boundaries in mv_fill_sg().
661 */
662 #ifdef CONFIG_PCI
663 static struct scsi_host_template mv5_sht = {
664 ATA_BASE_SHT(DRV_NAME),
665 .sg_tablesize = MV_MAX_SG_CT / 2,
666 .dma_boundary = MV_DMA_BOUNDARY,
667 };
668 #endif
669 static struct scsi_host_template mv6_sht = {
670 ATA_NCQ_SHT(DRV_NAME),
671 .can_queue = MV_MAX_Q_DEPTH - 1,
672 .sg_tablesize = MV_MAX_SG_CT / 2,
673 .dma_boundary = MV_DMA_BOUNDARY,
674 };
675
676 static struct ata_port_operations mv5_ops = {
677 .inherits = &ata_sff_port_ops,
678
679 .lost_interrupt = ATA_OP_NULL,
680
681 .qc_defer = mv_qc_defer,
682 .qc_prep = mv_qc_prep,
683 .qc_issue = mv_qc_issue,
684
685 .freeze = mv_eh_freeze,
686 .thaw = mv_eh_thaw,
687 .hardreset = mv_hardreset,
688
689 .scr_read = mv5_scr_read,
690 .scr_write = mv5_scr_write,
691
692 .port_start = mv_port_start,
693 .port_stop = mv_port_stop,
694 };
695
696 static struct ata_port_operations mv6_ops = {
697 .inherits = &ata_bmdma_port_ops,
698
699 .lost_interrupt = ATA_OP_NULL,
700
701 .qc_defer = mv_qc_defer,
702 .qc_prep = mv_qc_prep,
703 .qc_issue = mv_qc_issue,
704
705 .dev_config = mv6_dev_config,
706
707 .freeze = mv_eh_freeze,
708 .thaw = mv_eh_thaw,
709 .hardreset = mv_hardreset,
710 .softreset = mv_softreset,
711 .pmp_hardreset = mv_pmp_hardreset,
712 .pmp_softreset = mv_softreset,
713 .error_handler = mv_pmp_error_handler,
714
715 .scr_read = mv_scr_read,
716 .scr_write = mv_scr_write,
717
718 .sff_check_status = mv_sff_check_status,
719 .sff_irq_clear = mv_sff_irq_clear,
720 .check_atapi_dma = mv_check_atapi_dma,
721 .bmdma_setup = mv_bmdma_setup,
722 .bmdma_start = mv_bmdma_start,
723 .bmdma_stop = mv_bmdma_stop,
724 .bmdma_status = mv_bmdma_status,
725
726 .port_start = mv_port_start,
727 .port_stop = mv_port_stop,
728 };
729
730 static struct ata_port_operations mv_iie_ops = {
731 .inherits = &mv6_ops,
732 .dev_config = ATA_OP_NULL,
733 .qc_prep = mv_qc_prep_iie,
734 };
735
736 static const struct ata_port_info mv_port_info[] = {
737 { /* chip_504x */
738 .flags = MV_GEN_I_FLAGS,
739 .pio_mask = ATA_PIO4,
740 .udma_mask = ATA_UDMA6,
741 .port_ops = &mv5_ops,
742 },
743 { /* chip_508x */
744 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
745 .pio_mask = ATA_PIO4,
746 .udma_mask = ATA_UDMA6,
747 .port_ops = &mv5_ops,
748 },
749 { /* chip_5080 */
750 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
751 .pio_mask = ATA_PIO4,
752 .udma_mask = ATA_UDMA6,
753 .port_ops = &mv5_ops,
754 },
755 { /* chip_604x */
756 .flags = MV_GEN_II_FLAGS,
757 .pio_mask = ATA_PIO4,
758 .udma_mask = ATA_UDMA6,
759 .port_ops = &mv6_ops,
760 },
761 { /* chip_608x */
762 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
763 .pio_mask = ATA_PIO4,
764 .udma_mask = ATA_UDMA6,
765 .port_ops = &mv6_ops,
766 },
767 { /* chip_6042 */
768 .flags = MV_GEN_IIE_FLAGS,
769 .pio_mask = ATA_PIO4,
770 .udma_mask = ATA_UDMA6,
771 .port_ops = &mv_iie_ops,
772 },
773 { /* chip_7042 */
774 .flags = MV_GEN_IIE_FLAGS,
775 .pio_mask = ATA_PIO4,
776 .udma_mask = ATA_UDMA6,
777 .port_ops = &mv_iie_ops,
778 },
779 { /* chip_soc */
780 .flags = MV_GEN_IIE_FLAGS,
781 .pio_mask = ATA_PIO4,
782 .udma_mask = ATA_UDMA6,
783 .port_ops = &mv_iie_ops,
784 },
785 };
786
787 static const struct pci_device_id mv_pci_tbl[] = {
788 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
789 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
790 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
791 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
792 /* RocketRAID 1720/174x have different identifiers */
793 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
794 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
795 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
796
797 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
798 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
799 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
800 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
801 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
802
803 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
804
805 /* Adaptec 1430SA */
806 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
807
808 /* Marvell 7042 support */
809 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
810
811 /* Highpoint RocketRAID PCIe series */
812 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
813 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
814
815 { } /* terminate list */
816 };
817
818 static const struct mv_hw_ops mv5xxx_ops = {
819 .phy_errata = mv5_phy_errata,
820 .enable_leds = mv5_enable_leds,
821 .read_preamp = mv5_read_preamp,
822 .reset_hc = mv5_reset_hc,
823 .reset_flash = mv5_reset_flash,
824 .reset_bus = mv5_reset_bus,
825 };
826
827 static const struct mv_hw_ops mv6xxx_ops = {
828 .phy_errata = mv6_phy_errata,
829 .enable_leds = mv6_enable_leds,
830 .read_preamp = mv6_read_preamp,
831 .reset_hc = mv6_reset_hc,
832 .reset_flash = mv6_reset_flash,
833 .reset_bus = mv_reset_pci_bus,
834 };
835
836 static const struct mv_hw_ops mv_soc_ops = {
837 .phy_errata = mv6_phy_errata,
838 .enable_leds = mv_soc_enable_leds,
839 .read_preamp = mv_soc_read_preamp,
840 .reset_hc = mv_soc_reset_hc,
841 .reset_flash = mv_soc_reset_flash,
842 .reset_bus = mv_soc_reset_bus,
843 };
844
845 static const struct mv_hw_ops mv_soc_65n_ops = {
846 .phy_errata = mv_soc_65n_phy_errata,
847 .enable_leds = mv_soc_enable_leds,
848 .reset_hc = mv_soc_reset_hc,
849 .reset_flash = mv_soc_reset_flash,
850 .reset_bus = mv_soc_reset_bus,
851 };
852
853 /*
854 * Functions
855 */
856
857 static inline void writelfl(unsigned long data, void __iomem *addr)
858 {
859 writel(data, addr);
860 (void) readl(addr); /* flush to avoid PCI posted write */
861 }
862
863 static inline unsigned int mv_hc_from_port(unsigned int port)
864 {
865 return port >> MV_PORT_HC_SHIFT;
866 }
867
868 static inline unsigned int mv_hardport_from_port(unsigned int port)
869 {
870 return port & MV_PORT_MASK;
871 }
872
873 /*
874 * Consolidate some rather tricky bit shift calculations.
875 * This is hot-path stuff, so not a function.
876 * Simple code, with two return values, so macro rather than inline.
877 *
878 * port is the sole input, in range 0..7.
879 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
880 * hardport is the other output, in range 0..3.
881 *
882 * Note that port and hardport may be the same variable in some cases.
883 */
884 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
885 { \
886 shift = mv_hc_from_port(port) * HC_SHIFT; \
887 hardport = mv_hardport_from_port(port); \
888 shift += hardport * 2; \
889 }
890
891 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
892 {
893 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
894 }
895
896 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
897 unsigned int port)
898 {
899 return mv_hc_base(base, mv_hc_from_port(port));
900 }
901
902 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
903 {
904 return mv_hc_base_from_port(base, port) +
905 MV_SATAHC_ARBTR_REG_SZ +
906 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
907 }
908
909 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
910 {
911 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
912 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
913
914 return hc_mmio + ofs;
915 }
916
917 static inline void __iomem *mv_host_base(struct ata_host *host)
918 {
919 struct mv_host_priv *hpriv = host->private_data;
920 return hpriv->base;
921 }
922
923 static inline void __iomem *mv_ap_base(struct ata_port *ap)
924 {
925 return mv_port_base(mv_host_base(ap->host), ap->port_no);
926 }
927
928 static inline int mv_get_hc_count(unsigned long port_flags)
929 {
930 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
931 }
932
933 /**
934 * mv_save_cached_regs - (re-)initialize cached port registers
935 * @ap: the port whose registers we are caching
936 *
937 * Initialize the local cache of port registers,
938 * so that reading them over and over again can
939 * be avoided on the hotter paths of this driver.
940 * This saves a few microseconds each time we switch
941 * to/from EDMA mode to perform (eg.) a drive cache flush.
942 */
943 static void mv_save_cached_regs(struct ata_port *ap)
944 {
945 void __iomem *port_mmio = mv_ap_base(ap);
946 struct mv_port_priv *pp = ap->private_data;
947
948 pp->cached.fiscfg = readl(port_mmio + FISCFG);
949 pp->cached.ltmode = readl(port_mmio + LTMODE);
950 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
951 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
952 }
953
954 /**
955 * mv_write_cached_reg - write to a cached port register
956 * @addr: hardware address of the register
957 * @old: pointer to cached value of the register
958 * @new: new value for the register
959 *
960 * Write a new value to a cached register,
961 * but only if the value is different from before.
962 */
963 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
964 {
965 if (new != *old) {
966 unsigned long laddr;
967 *old = new;
968 /*
969 * Workaround for 88SX60x1-B2 FEr SATA#13:
970 * Read-after-write is needed to prevent generating 64-bit
971 * write cycles on the PCI bus for SATA interface registers
972 * at offsets ending in 0x4 or 0xc.
973 *
974 * Looks like a lot of fuss, but it avoids an unnecessary
975 * +1 usec read-after-write delay for unaffected registers.
976 */
977 laddr = (long)addr & 0xffff;
978 if (laddr >= 0x300 && laddr <= 0x33c) {
979 laddr &= 0x000f;
980 if (laddr == 0x4 || laddr == 0xc) {
981 writelfl(new, addr); /* read after write */
982 return;
983 }
984 }
985 writel(new, addr); /* unaffected by the errata */
986 }
987 }
988
989 static void mv_set_edma_ptrs(void __iomem *port_mmio,
990 struct mv_host_priv *hpriv,
991 struct mv_port_priv *pp)
992 {
993 u32 index;
994
995 /*
996 * initialize request queue
997 */
998 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
999 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1000
1001 WARN_ON(pp->crqb_dma & 0x3ff);
1002 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
1003 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
1004 port_mmio + EDMA_REQ_Q_IN_PTR);
1005 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
1006
1007 /*
1008 * initialize response queue
1009 */
1010 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1011 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1012
1013 WARN_ON(pp->crpb_dma & 0xff);
1014 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1015 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1016 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
1017 port_mmio + EDMA_RSP_Q_OUT_PTR);
1018 }
1019
1020 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1021 {
1022 /*
1023 * When writing to the main_irq_mask in hardware,
1024 * we must ensure exclusivity between the interrupt coalescing bits
1025 * and the corresponding individual port DONE_IRQ bits.
1026 *
1027 * Note that this register is really an "IRQ enable" register,
1028 * not an "IRQ mask" register as Marvell's naming might suggest.
1029 */
1030 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1031 mask &= ~DONE_IRQ_0_3;
1032 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1033 mask &= ~DONE_IRQ_4_7;
1034 writelfl(mask, hpriv->main_irq_mask_addr);
1035 }
1036
1037 static void mv_set_main_irq_mask(struct ata_host *host,
1038 u32 disable_bits, u32 enable_bits)
1039 {
1040 struct mv_host_priv *hpriv = host->private_data;
1041 u32 old_mask, new_mask;
1042
1043 old_mask = hpriv->main_irq_mask;
1044 new_mask = (old_mask & ~disable_bits) | enable_bits;
1045 if (new_mask != old_mask) {
1046 hpriv->main_irq_mask = new_mask;
1047 mv_write_main_irq_mask(new_mask, hpriv);
1048 }
1049 }
1050
1051 static void mv_enable_port_irqs(struct ata_port *ap,
1052 unsigned int port_bits)
1053 {
1054 unsigned int shift, hardport, port = ap->port_no;
1055 u32 disable_bits, enable_bits;
1056
1057 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1058
1059 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1060 enable_bits = port_bits << shift;
1061 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1062 }
1063
1064 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1065 void __iomem *port_mmio,
1066 unsigned int port_irqs)
1067 {
1068 struct mv_host_priv *hpriv = ap->host->private_data;
1069 int hardport = mv_hardport_from_port(ap->port_no);
1070 void __iomem *hc_mmio = mv_hc_base_from_port(
1071 mv_host_base(ap->host), ap->port_no);
1072 u32 hc_irq_cause;
1073
1074 /* clear EDMA event indicators, if any */
1075 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1076
1077 /* clear pending irq events */
1078 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1079 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1080
1081 /* clear FIS IRQ Cause */
1082 if (IS_GEN_IIE(hpriv))
1083 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1084
1085 mv_enable_port_irqs(ap, port_irqs);
1086 }
1087
1088 static void mv_set_irq_coalescing(struct ata_host *host,
1089 unsigned int count, unsigned int usecs)
1090 {
1091 struct mv_host_priv *hpriv = host->private_data;
1092 void __iomem *mmio = hpriv->base, *hc_mmio;
1093 u32 coal_enable = 0;
1094 unsigned long flags;
1095 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1096 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1097 ALL_PORTS_COAL_DONE;
1098
1099 /* Disable IRQ coalescing if either threshold is zero */
1100 if (!usecs || !count) {
1101 clks = count = 0;
1102 } else {
1103 /* Respect maximum limits of the hardware */
1104 clks = usecs * COAL_CLOCKS_PER_USEC;
1105 if (clks > MAX_COAL_TIME_THRESHOLD)
1106 clks = MAX_COAL_TIME_THRESHOLD;
1107 if (count > MAX_COAL_IO_COUNT)
1108 count = MAX_COAL_IO_COUNT;
1109 }
1110
1111 spin_lock_irqsave(&host->lock, flags);
1112 mv_set_main_irq_mask(host, coal_disable, 0);
1113
1114 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1115 /*
1116 * GEN_II/GEN_IIE with dual host controllers:
1117 * one set of global thresholds for the entire chip.
1118 */
1119 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1120 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1121 /* clear leftover coal IRQ bit */
1122 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1123 if (count)
1124 coal_enable = ALL_PORTS_COAL_DONE;
1125 clks = count = 0; /* force clearing of regular regs below */
1126 }
1127
1128 /*
1129 * All chips: independent thresholds for each HC on the chip.
1130 */
1131 hc_mmio = mv_hc_base_from_port(mmio, 0);
1132 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1133 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1134 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1135 if (count)
1136 coal_enable |= PORTS_0_3_COAL_DONE;
1137 if (is_dual_hc) {
1138 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1139 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1140 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1141 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1142 if (count)
1143 coal_enable |= PORTS_4_7_COAL_DONE;
1144 }
1145
1146 mv_set_main_irq_mask(host, 0, coal_enable);
1147 spin_unlock_irqrestore(&host->lock, flags);
1148 }
1149
1150 /**
1151 * mv_start_edma - Enable eDMA engine
1152 * @base: port base address
1153 * @pp: port private data
1154 *
1155 * Verify the local cache of the eDMA state is accurate with a
1156 * WARN_ON.
1157 *
1158 * LOCKING:
1159 * Inherited from caller.
1160 */
1161 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1162 struct mv_port_priv *pp, u8 protocol)
1163 {
1164 int want_ncq = (protocol == ATA_PROT_NCQ);
1165
1166 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1167 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1168 if (want_ncq != using_ncq)
1169 mv_stop_edma(ap);
1170 }
1171 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1172 struct mv_host_priv *hpriv = ap->host->private_data;
1173
1174 mv_edma_cfg(ap, want_ncq, 1);
1175
1176 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1177 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1178
1179 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1180 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1181 }
1182 }
1183
1184 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1185 {
1186 void __iomem *port_mmio = mv_ap_base(ap);
1187 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1188 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1189 int i;
1190
1191 /*
1192 * Wait for the EDMA engine to finish transactions in progress.
1193 * No idea what a good "timeout" value might be, but measurements
1194 * indicate that it often requires hundreds of microseconds
1195 * with two drives in-use. So we use the 15msec value above
1196 * as a rough guess at what even more drives might require.
1197 */
1198 for (i = 0; i < timeout; ++i) {
1199 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1200 if ((edma_stat & empty_idle) == empty_idle)
1201 break;
1202 udelay(per_loop);
1203 }
1204 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
1205 }
1206
1207 /**
1208 * mv_stop_edma_engine - Disable eDMA engine
1209 * @port_mmio: io base address
1210 *
1211 * LOCKING:
1212 * Inherited from caller.
1213 */
1214 static int mv_stop_edma_engine(void __iomem *port_mmio)
1215 {
1216 int i;
1217
1218 /* Disable eDMA. The disable bit auto clears. */
1219 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1220
1221 /* Wait for the chip to confirm eDMA is off. */
1222 for (i = 10000; i > 0; i--) {
1223 u32 reg = readl(port_mmio + EDMA_CMD);
1224 if (!(reg & EDMA_EN))
1225 return 0;
1226 udelay(10);
1227 }
1228 return -EIO;
1229 }
1230
1231 static int mv_stop_edma(struct ata_port *ap)
1232 {
1233 void __iomem *port_mmio = mv_ap_base(ap);
1234 struct mv_port_priv *pp = ap->private_data;
1235 int err = 0;
1236
1237 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1238 return 0;
1239 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1240 mv_wait_for_edma_empty_idle(ap);
1241 if (mv_stop_edma_engine(port_mmio)) {
1242 ata_port_err(ap, "Unable to stop eDMA\n");
1243 err = -EIO;
1244 }
1245 mv_edma_cfg(ap, 0, 0);
1246 return err;
1247 }
1248
1249 #ifdef ATA_DEBUG
1250 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1251 {
1252 int b, w;
1253 for (b = 0; b < bytes; ) {
1254 DPRINTK("%p: ", start + b);
1255 for (w = 0; b < bytes && w < 4; w++) {
1256 printk("%08x ", readl(start + b));
1257 b += sizeof(u32);
1258 }
1259 printk("\n");
1260 }
1261 }
1262 #endif
1263 #if defined(ATA_DEBUG) || defined(CONFIG_PCI)
1264 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1265 {
1266 #ifdef ATA_DEBUG
1267 int b, w;
1268 u32 dw;
1269 for (b = 0; b < bytes; ) {
1270 DPRINTK("%02x: ", b);
1271 for (w = 0; b < bytes && w < 4; w++) {
1272 (void) pci_read_config_dword(pdev, b, &dw);
1273 printk("%08x ", dw);
1274 b += sizeof(u32);
1275 }
1276 printk("\n");
1277 }
1278 #endif
1279 }
1280 #endif
1281 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1282 struct pci_dev *pdev)
1283 {
1284 #ifdef ATA_DEBUG
1285 void __iomem *hc_base = mv_hc_base(mmio_base,
1286 port >> MV_PORT_HC_SHIFT);
1287 void __iomem *port_base;
1288 int start_port, num_ports, p, start_hc, num_hcs, hc;
1289
1290 if (0 > port) {
1291 start_hc = start_port = 0;
1292 num_ports = 8; /* shld be benign for 4 port devs */
1293 num_hcs = 2;
1294 } else {
1295 start_hc = port >> MV_PORT_HC_SHIFT;
1296 start_port = port;
1297 num_ports = num_hcs = 1;
1298 }
1299 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1300 num_ports > 1 ? num_ports - 1 : start_port);
1301
1302 if (NULL != pdev) {
1303 DPRINTK("PCI config space regs:\n");
1304 mv_dump_pci_cfg(pdev, 0x68);
1305 }
1306 DPRINTK("PCI regs:\n");
1307 mv_dump_mem(mmio_base+0xc00, 0x3c);
1308 mv_dump_mem(mmio_base+0xd00, 0x34);
1309 mv_dump_mem(mmio_base+0xf00, 0x4);
1310 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1311 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1312 hc_base = mv_hc_base(mmio_base, hc);
1313 DPRINTK("HC regs (HC %i):\n", hc);
1314 mv_dump_mem(hc_base, 0x1c);
1315 }
1316 for (p = start_port; p < start_port + num_ports; p++) {
1317 port_base = mv_port_base(mmio_base, p);
1318 DPRINTK("EDMA regs (port %i):\n", p);
1319 mv_dump_mem(port_base, 0x54);
1320 DPRINTK("SATA regs (port %i):\n", p);
1321 mv_dump_mem(port_base+0x300, 0x60);
1322 }
1323 #endif
1324 }
1325
1326 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1327 {
1328 unsigned int ofs;
1329
1330 switch (sc_reg_in) {
1331 case SCR_STATUS:
1332 case SCR_CONTROL:
1333 case SCR_ERROR:
1334 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1335 break;
1336 case SCR_ACTIVE:
1337 ofs = SATA_ACTIVE; /* active is not with the others */
1338 break;
1339 default:
1340 ofs = 0xffffffffU;
1341 break;
1342 }
1343 return ofs;
1344 }
1345
1346 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1347 {
1348 unsigned int ofs = mv_scr_offset(sc_reg_in);
1349
1350 if (ofs != 0xffffffffU) {
1351 *val = readl(mv_ap_base(link->ap) + ofs);
1352 return 0;
1353 } else
1354 return -EINVAL;
1355 }
1356
1357 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1358 {
1359 unsigned int ofs = mv_scr_offset(sc_reg_in);
1360
1361 if (ofs != 0xffffffffU) {
1362 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1363 struct mv_host_priv *hpriv = link->ap->host->private_data;
1364 if (sc_reg_in == SCR_CONTROL) {
1365 /*
1366 * Workaround for 88SX60x1 FEr SATA#26:
1367 *
1368 * COMRESETs have to take care not to accidentally
1369 * put the drive to sleep when writing SCR_CONTROL.
1370 * Setting bits 12..15 prevents this problem.
1371 *
1372 * So if we see an outbound COMMRESET, set those bits.
1373 * Ditto for the followup write that clears the reset.
1374 *
1375 * The proprietary driver does this for
1376 * all chip versions, and so do we.
1377 */
1378 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1379 val |= 0xf000;
1380
1381 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
1382 void __iomem *lp_phy_addr =
1383 mv_ap_base(link->ap) + LP_PHY_CTL;
1384 /*
1385 * Set PHY speed according to SControl speed.
1386 */
1387 if ((val & 0xf0) == 0x10)
1388 writelfl(0x7, lp_phy_addr);
1389 else
1390 writelfl(0x227, lp_phy_addr);
1391 }
1392 }
1393 writelfl(val, addr);
1394 return 0;
1395 } else
1396 return -EINVAL;
1397 }
1398
1399 static void mv6_dev_config(struct ata_device *adev)
1400 {
1401 /*
1402 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1403 *
1404 * Gen-II does not support NCQ over a port multiplier
1405 * (no FIS-based switching).
1406 */
1407 if (adev->flags & ATA_DFLAG_NCQ) {
1408 if (sata_pmp_attached(adev->link->ap)) {
1409 adev->flags &= ~ATA_DFLAG_NCQ;
1410 ata_dev_info(adev,
1411 "NCQ disabled for command-based switching\n");
1412 }
1413 }
1414 }
1415
1416 static int mv_qc_defer(struct ata_queued_cmd *qc)
1417 {
1418 struct ata_link *link = qc->dev->link;
1419 struct ata_port *ap = link->ap;
1420 struct mv_port_priv *pp = ap->private_data;
1421
1422 /*
1423 * Don't allow new commands if we're in a delayed EH state
1424 * for NCQ and/or FIS-based switching.
1425 */
1426 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1427 return ATA_DEFER_PORT;
1428
1429 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1430 * can run concurrently.
1431 * set excl_link when we want to send a PIO command in DMA mode
1432 * or a non-NCQ command in NCQ mode.
1433 * When we receive a command from that link, and there are no
1434 * outstanding commands, mark a flag to clear excl_link and let
1435 * the command go through.
1436 */
1437 if (unlikely(ap->excl_link)) {
1438 if (link == ap->excl_link) {
1439 if (ap->nr_active_links)
1440 return ATA_DEFER_PORT;
1441 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1442 return 0;
1443 } else
1444 return ATA_DEFER_PORT;
1445 }
1446
1447 /*
1448 * If the port is completely idle, then allow the new qc.
1449 */
1450 if (ap->nr_active_links == 0)
1451 return 0;
1452
1453 /*
1454 * The port is operating in host queuing mode (EDMA) with NCQ
1455 * enabled, allow multiple NCQ commands. EDMA also allows
1456 * queueing multiple DMA commands but libata core currently
1457 * doesn't allow it.
1458 */
1459 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1460 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1461 if (ata_is_ncq(qc->tf.protocol))
1462 return 0;
1463 else {
1464 ap->excl_link = link;
1465 return ATA_DEFER_PORT;
1466 }
1467 }
1468
1469 return ATA_DEFER_PORT;
1470 }
1471
1472 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1473 {
1474 struct mv_port_priv *pp = ap->private_data;
1475 void __iomem *port_mmio;
1476
1477 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1478 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1479 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1480
1481 ltmode = *old_ltmode & ~LTMODE_BIT8;
1482 haltcond = *old_haltcond | EDMA_ERR_DEV;
1483
1484 if (want_fbs) {
1485 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1486 ltmode = *old_ltmode | LTMODE_BIT8;
1487 if (want_ncq)
1488 haltcond &= ~EDMA_ERR_DEV;
1489 else
1490 fiscfg |= FISCFG_WAIT_DEV_ERR;
1491 } else {
1492 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1493 }
1494
1495 port_mmio = mv_ap_base(ap);
1496 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1497 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1498 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1499 }
1500
1501 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1502 {
1503 struct mv_host_priv *hpriv = ap->host->private_data;
1504 u32 old, new;
1505
1506 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1507 old = readl(hpriv->base + GPIO_PORT_CTL);
1508 if (want_ncq)
1509 new = old | (1 << 22);
1510 else
1511 new = old & ~(1 << 22);
1512 if (new != old)
1513 writel(new, hpriv->base + GPIO_PORT_CTL);
1514 }
1515
1516 /**
1517 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1518 * @ap: Port being initialized
1519 *
1520 * There are two DMA modes on these chips: basic DMA, and EDMA.
1521 *
1522 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1523 * of basic DMA on the GEN_IIE versions of the chips.
1524 *
1525 * This bit survives EDMA resets, and must be set for basic DMA
1526 * to function, and should be cleared when EDMA is active.
1527 */
1528 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1529 {
1530 struct mv_port_priv *pp = ap->private_data;
1531 u32 new, *old = &pp->cached.unknown_rsvd;
1532
1533 if (enable_bmdma)
1534 new = *old | 1;
1535 else
1536 new = *old & ~1;
1537 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1538 }
1539
1540 /*
1541 * SOC chips have an issue whereby the HDD LEDs don't always blink
1542 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1543 * of the SOC takes care of it, generating a steady blink rate when
1544 * any drive on the chip is active.
1545 *
1546 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1547 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1548 *
1549 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1550 * LED operation works then, and provides better (more accurate) feedback.
1551 *
1552 * Note that this code assumes that an SOC never has more than one HC onboard.
1553 */
1554 static void mv_soc_led_blink_enable(struct ata_port *ap)
1555 {
1556 struct ata_host *host = ap->host;
1557 struct mv_host_priv *hpriv = host->private_data;
1558 void __iomem *hc_mmio;
1559 u32 led_ctrl;
1560
1561 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1562 return;
1563 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1564 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1565 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1566 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1567 }
1568
1569 static void mv_soc_led_blink_disable(struct ata_port *ap)
1570 {
1571 struct ata_host *host = ap->host;
1572 struct mv_host_priv *hpriv = host->private_data;
1573 void __iomem *hc_mmio;
1574 u32 led_ctrl;
1575 unsigned int port;
1576
1577 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1578 return;
1579
1580 /* disable led-blink only if no ports are using NCQ */
1581 for (port = 0; port < hpriv->n_ports; port++) {
1582 struct ata_port *this_ap = host->ports[port];
1583 struct mv_port_priv *pp = this_ap->private_data;
1584
1585 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1586 return;
1587 }
1588
1589 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1590 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1591 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1592 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1593 }
1594
1595 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1596 {
1597 u32 cfg;
1598 struct mv_port_priv *pp = ap->private_data;
1599 struct mv_host_priv *hpriv = ap->host->private_data;
1600 void __iomem *port_mmio = mv_ap_base(ap);
1601
1602 /* set up non-NCQ EDMA configuration */
1603 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1604 pp->pp_flags &=
1605 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1606
1607 if (IS_GEN_I(hpriv))
1608 cfg |= (1 << 8); /* enab config burst size mask */
1609
1610 else if (IS_GEN_II(hpriv)) {
1611 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1612 mv_60x1_errata_sata25(ap, want_ncq);
1613
1614 } else if (IS_GEN_IIE(hpriv)) {
1615 int want_fbs = sata_pmp_attached(ap);
1616 /*
1617 * Possible future enhancement:
1618 *
1619 * The chip can use FBS with non-NCQ, if we allow it,
1620 * But first we need to have the error handling in place
1621 * for this mode (datasheet section 7.3.15.4.2.3).
1622 * So disallow non-NCQ FBS for now.
1623 */
1624 want_fbs &= want_ncq;
1625
1626 mv_config_fbs(ap, want_ncq, want_fbs);
1627
1628 if (want_fbs) {
1629 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1630 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1631 }
1632
1633 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1634 if (want_edma) {
1635 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1636 if (!IS_SOC(hpriv))
1637 cfg |= (1 << 18); /* enab early completion */
1638 }
1639 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1640 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1641 mv_bmdma_enable_iie(ap, !want_edma);
1642
1643 if (IS_SOC(hpriv)) {
1644 if (want_ncq)
1645 mv_soc_led_blink_enable(ap);
1646 else
1647 mv_soc_led_blink_disable(ap);
1648 }
1649 }
1650
1651 if (want_ncq) {
1652 cfg |= EDMA_CFG_NCQ;
1653 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1654 }
1655
1656 writelfl(cfg, port_mmio + EDMA_CFG);
1657 }
1658
1659 static void mv_port_free_dma_mem(struct ata_port *ap)
1660 {
1661 struct mv_host_priv *hpriv = ap->host->private_data;
1662 struct mv_port_priv *pp = ap->private_data;
1663 int tag;
1664
1665 if (pp->crqb) {
1666 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1667 pp->crqb = NULL;
1668 }
1669 if (pp->crpb) {
1670 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1671 pp->crpb = NULL;
1672 }
1673 /*
1674 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1675 * For later hardware, we have one unique sg_tbl per NCQ tag.
1676 */
1677 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1678 if (pp->sg_tbl[tag]) {
1679 if (tag == 0 || !IS_GEN_I(hpriv))
1680 dma_pool_free(hpriv->sg_tbl_pool,
1681 pp->sg_tbl[tag],
1682 pp->sg_tbl_dma[tag]);
1683 pp->sg_tbl[tag] = NULL;
1684 }
1685 }
1686 }
1687
1688 /**
1689 * mv_port_start - Port specific init/start routine.
1690 * @ap: ATA channel to manipulate
1691 *
1692 * Allocate and point to DMA memory, init port private memory,
1693 * zero indices.
1694 *
1695 * LOCKING:
1696 * Inherited from caller.
1697 */
1698 static int mv_port_start(struct ata_port *ap)
1699 {
1700 struct device *dev = ap->host->dev;
1701 struct mv_host_priv *hpriv = ap->host->private_data;
1702 struct mv_port_priv *pp;
1703 unsigned long flags;
1704 int tag;
1705
1706 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1707 if (!pp)
1708 return -ENOMEM;
1709 ap->private_data = pp;
1710
1711 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1712 if (!pp->crqb)
1713 return -ENOMEM;
1714 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1715
1716 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1717 if (!pp->crpb)
1718 goto out_port_free_dma_mem;
1719 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1720
1721 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1722 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1723 ap->flags |= ATA_FLAG_AN;
1724 /*
1725 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1726 * For later hardware, we need one unique sg_tbl per NCQ tag.
1727 */
1728 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1729 if (tag == 0 || !IS_GEN_I(hpriv)) {
1730 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1731 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1732 if (!pp->sg_tbl[tag])
1733 goto out_port_free_dma_mem;
1734 } else {
1735 pp->sg_tbl[tag] = pp->sg_tbl[0];
1736 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1737 }
1738 }
1739
1740 spin_lock_irqsave(ap->lock, flags);
1741 mv_save_cached_regs(ap);
1742 mv_edma_cfg(ap, 0, 0);
1743 spin_unlock_irqrestore(ap->lock, flags);
1744
1745 return 0;
1746
1747 out_port_free_dma_mem:
1748 mv_port_free_dma_mem(ap);
1749 return -ENOMEM;
1750 }
1751
1752 /**
1753 * mv_port_stop - Port specific cleanup/stop routine.
1754 * @ap: ATA channel to manipulate
1755 *
1756 * Stop DMA, cleanup port memory.
1757 *
1758 * LOCKING:
1759 * This routine uses the host lock to protect the DMA stop.
1760 */
1761 static void mv_port_stop(struct ata_port *ap)
1762 {
1763 unsigned long flags;
1764
1765 spin_lock_irqsave(ap->lock, flags);
1766 mv_stop_edma(ap);
1767 mv_enable_port_irqs(ap, 0);
1768 spin_unlock_irqrestore(ap->lock, flags);
1769 mv_port_free_dma_mem(ap);
1770 }
1771
1772 /**
1773 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1774 * @qc: queued command whose SG list to source from
1775 *
1776 * Populate the SG list and mark the last entry.
1777 *
1778 * LOCKING:
1779 * Inherited from caller.
1780 */
1781 static void mv_fill_sg(struct ata_queued_cmd *qc)
1782 {
1783 struct mv_port_priv *pp = qc->ap->private_data;
1784 struct scatterlist *sg;
1785 struct mv_sg *mv_sg, *last_sg = NULL;
1786 unsigned int si;
1787
1788 mv_sg = pp->sg_tbl[qc->tag];
1789 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1790 dma_addr_t addr = sg_dma_address(sg);
1791 u32 sg_len = sg_dma_len(sg);
1792
1793 while (sg_len) {
1794 u32 offset = addr & 0xffff;
1795 u32 len = sg_len;
1796
1797 if (offset + len > 0x10000)
1798 len = 0x10000 - offset;
1799
1800 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1801 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1802 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1803 mv_sg->reserved = 0;
1804
1805 sg_len -= len;
1806 addr += len;
1807
1808 last_sg = mv_sg;
1809 mv_sg++;
1810 }
1811 }
1812
1813 if (likely(last_sg))
1814 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1815 mb(); /* ensure data structure is visible to the chipset */
1816 }
1817
1818 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1819 {
1820 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1821 (last ? CRQB_CMD_LAST : 0);
1822 *cmdw = cpu_to_le16(tmp);
1823 }
1824
1825 /**
1826 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1827 * @ap: Port associated with this ATA transaction.
1828 *
1829 * We need this only for ATAPI bmdma transactions,
1830 * as otherwise we experience spurious interrupts
1831 * after libata-sff handles the bmdma interrupts.
1832 */
1833 static void mv_sff_irq_clear(struct ata_port *ap)
1834 {
1835 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1836 }
1837
1838 /**
1839 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1840 * @qc: queued command to check for chipset/DMA compatibility.
1841 *
1842 * The bmdma engines cannot handle speculative data sizes
1843 * (bytecount under/over flow). So only allow DMA for
1844 * data transfer commands with known data sizes.
1845 *
1846 * LOCKING:
1847 * Inherited from caller.
1848 */
1849 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1850 {
1851 struct scsi_cmnd *scmd = qc->scsicmd;
1852
1853 if (scmd) {
1854 switch (scmd->cmnd[0]) {
1855 case READ_6:
1856 case READ_10:
1857 case READ_12:
1858 case WRITE_6:
1859 case WRITE_10:
1860 case WRITE_12:
1861 case GPCMD_READ_CD:
1862 case GPCMD_SEND_DVD_STRUCTURE:
1863 case GPCMD_SEND_CUE_SHEET:
1864 return 0; /* DMA is safe */
1865 }
1866 }
1867 return -EOPNOTSUPP; /* use PIO instead */
1868 }
1869
1870 /**
1871 * mv_bmdma_setup - Set up BMDMA transaction
1872 * @qc: queued command to prepare DMA for.
1873 *
1874 * LOCKING:
1875 * Inherited from caller.
1876 */
1877 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1878 {
1879 struct ata_port *ap = qc->ap;
1880 void __iomem *port_mmio = mv_ap_base(ap);
1881 struct mv_port_priv *pp = ap->private_data;
1882
1883 mv_fill_sg(qc);
1884
1885 /* clear all DMA cmd bits */
1886 writel(0, port_mmio + BMDMA_CMD);
1887
1888 /* load PRD table addr. */
1889 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1890 port_mmio + BMDMA_PRD_HIGH);
1891 writelfl(pp->sg_tbl_dma[qc->tag],
1892 port_mmio + BMDMA_PRD_LOW);
1893
1894 /* issue r/w command */
1895 ap->ops->sff_exec_command(ap, &qc->tf);
1896 }
1897
1898 /**
1899 * mv_bmdma_start - Start a BMDMA transaction
1900 * @qc: queued command to start DMA on.
1901 *
1902 * LOCKING:
1903 * Inherited from caller.
1904 */
1905 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1906 {
1907 struct ata_port *ap = qc->ap;
1908 void __iomem *port_mmio = mv_ap_base(ap);
1909 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1910 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1911
1912 /* start host DMA transaction */
1913 writelfl(cmd, port_mmio + BMDMA_CMD);
1914 }
1915
1916 /**
1917 * mv_bmdma_stop - Stop BMDMA transfer
1918 * @qc: queued command to stop DMA on.
1919 *
1920 * Clears the ATA_DMA_START flag in the bmdma control register
1921 *
1922 * LOCKING:
1923 * Inherited from caller.
1924 */
1925 static void mv_bmdma_stop_ap(struct ata_port *ap)
1926 {
1927 void __iomem *port_mmio = mv_ap_base(ap);
1928 u32 cmd;
1929
1930 /* clear start/stop bit */
1931 cmd = readl(port_mmio + BMDMA_CMD);
1932 if (cmd & ATA_DMA_START) {
1933 cmd &= ~ATA_DMA_START;
1934 writelfl(cmd, port_mmio + BMDMA_CMD);
1935
1936 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1937 ata_sff_dma_pause(ap);
1938 }
1939 }
1940
1941 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1942 {
1943 mv_bmdma_stop_ap(qc->ap);
1944 }
1945
1946 /**
1947 * mv_bmdma_status - Read BMDMA status
1948 * @ap: port for which to retrieve DMA status.
1949 *
1950 * Read and return equivalent of the sff BMDMA status register.
1951 *
1952 * LOCKING:
1953 * Inherited from caller.
1954 */
1955 static u8 mv_bmdma_status(struct ata_port *ap)
1956 {
1957 void __iomem *port_mmio = mv_ap_base(ap);
1958 u32 reg, status;
1959
1960 /*
1961 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1962 * and the ATA_DMA_INTR bit doesn't exist.
1963 */
1964 reg = readl(port_mmio + BMDMA_STATUS);
1965 if (reg & ATA_DMA_ACTIVE)
1966 status = ATA_DMA_ACTIVE;
1967 else if (reg & ATA_DMA_ERR)
1968 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1969 else {
1970 /*
1971 * Just because DMA_ACTIVE is 0 (DMA completed),
1972 * this does _not_ mean the device is "done".
1973 * So we should not yet be signalling ATA_DMA_INTR
1974 * in some cases. Eg. DSM/TRIM, and perhaps others.
1975 */
1976 mv_bmdma_stop_ap(ap);
1977 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1978 status = 0;
1979 else
1980 status = ATA_DMA_INTR;
1981 }
1982 return status;
1983 }
1984
1985 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1986 {
1987 struct ata_taskfile *tf = &qc->tf;
1988 /*
1989 * Workaround for 88SX60x1 FEr SATA#24.
1990 *
1991 * Chip may corrupt WRITEs if multi_count >= 4kB.
1992 * Note that READs are unaffected.
1993 *
1994 * It's not clear if this errata really means "4K bytes",
1995 * or if it always happens for multi_count > 7
1996 * regardless of device sector_size.
1997 *
1998 * So, for safety, any write with multi_count > 7
1999 * gets converted here into a regular PIO write instead:
2000 */
2001 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
2002 if (qc->dev->multi_count > 7) {
2003 switch (tf->command) {
2004 case ATA_CMD_WRITE_MULTI:
2005 tf->command = ATA_CMD_PIO_WRITE;
2006 break;
2007 case ATA_CMD_WRITE_MULTI_FUA_EXT:
2008 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
2009 /* fall through */
2010 case ATA_CMD_WRITE_MULTI_EXT:
2011 tf->command = ATA_CMD_PIO_WRITE_EXT;
2012 break;
2013 }
2014 }
2015 }
2016 }
2017
2018 /**
2019 * mv_qc_prep - Host specific command preparation.
2020 * @qc: queued command to prepare
2021 *
2022 * This routine simply redirects to the general purpose routine
2023 * if command is not DMA. Else, it handles prep of the CRQB
2024 * (command request block), does some sanity checking, and calls
2025 * the SG load routine.
2026 *
2027 * LOCKING:
2028 * Inherited from caller.
2029 */
2030 static void mv_qc_prep(struct ata_queued_cmd *qc)
2031 {
2032 struct ata_port *ap = qc->ap;
2033 struct mv_port_priv *pp = ap->private_data;
2034 __le16 *cw;
2035 struct ata_taskfile *tf = &qc->tf;
2036 u16 flags = 0;
2037 unsigned in_index;
2038
2039 switch (tf->protocol) {
2040 case ATA_PROT_DMA:
2041 if (tf->command == ATA_CMD_DSM)
2042 return;
2043 /* fall-thru */
2044 case ATA_PROT_NCQ:
2045 break; /* continue below */
2046 case ATA_PROT_PIO:
2047 mv_rw_multi_errata_sata24(qc);
2048 return;
2049 default:
2050 return;
2051 }
2052
2053 /* Fill in command request block
2054 */
2055 if (!(tf->flags & ATA_TFLAG_WRITE))
2056 flags |= CRQB_FLAG_READ;
2057 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2058 flags |= qc->tag << CRQB_TAG_SHIFT;
2059 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2060
2061 /* get current queue index from software */
2062 in_index = pp->req_idx;
2063
2064 pp->crqb[in_index].sg_addr =
2065 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2066 pp->crqb[in_index].sg_addr_hi =
2067 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2068 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2069
2070 cw = &pp->crqb[in_index].ata_cmd[0];
2071
2072 /* Sadly, the CRQB cannot accommodate all registers--there are
2073 * only 11 bytes...so we must pick and choose required
2074 * registers based on the command. So, we drop feature and
2075 * hob_feature for [RW] DMA commands, but they are needed for
2076 * NCQ. NCQ will drop hob_nsect, which is not needed there
2077 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2078 */
2079 switch (tf->command) {
2080 case ATA_CMD_READ:
2081 case ATA_CMD_READ_EXT:
2082 case ATA_CMD_WRITE:
2083 case ATA_CMD_WRITE_EXT:
2084 case ATA_CMD_WRITE_FUA_EXT:
2085 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2086 break;
2087 case ATA_CMD_FPDMA_READ:
2088 case ATA_CMD_FPDMA_WRITE:
2089 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2090 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2091 break;
2092 default:
2093 /* The only other commands EDMA supports in non-queued and
2094 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2095 * of which are defined/used by Linux. If we get here, this
2096 * driver needs work.
2097 *
2098 * FIXME: modify libata to give qc_prep a return value and
2099 * return error here.
2100 */
2101 BUG_ON(tf->command);
2102 break;
2103 }
2104 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2105 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2106 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2107 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2108 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2109 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2110 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2111 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2112 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2113
2114 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2115 return;
2116 mv_fill_sg(qc);
2117 }
2118
2119 /**
2120 * mv_qc_prep_iie - Host specific command preparation.
2121 * @qc: queued command to prepare
2122 *
2123 * This routine simply redirects to the general purpose routine
2124 * if command is not DMA. Else, it handles prep of the CRQB
2125 * (command request block), does some sanity checking, and calls
2126 * the SG load routine.
2127 *
2128 * LOCKING:
2129 * Inherited from caller.
2130 */
2131 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2132 {
2133 struct ata_port *ap = qc->ap;
2134 struct mv_port_priv *pp = ap->private_data;
2135 struct mv_crqb_iie *crqb;
2136 struct ata_taskfile *tf = &qc->tf;
2137 unsigned in_index;
2138 u32 flags = 0;
2139
2140 if ((tf->protocol != ATA_PROT_DMA) &&
2141 (tf->protocol != ATA_PROT_NCQ))
2142 return;
2143 if (tf->command == ATA_CMD_DSM)
2144 return; /* use bmdma for this */
2145
2146 /* Fill in Gen IIE command request block */
2147 if (!(tf->flags & ATA_TFLAG_WRITE))
2148 flags |= CRQB_FLAG_READ;
2149
2150 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2151 flags |= qc->tag << CRQB_TAG_SHIFT;
2152 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2153 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2154
2155 /* get current queue index from software */
2156 in_index = pp->req_idx;
2157
2158 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2159 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2160 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2161 crqb->flags = cpu_to_le32(flags);
2162
2163 crqb->ata_cmd[0] = cpu_to_le32(
2164 (tf->command << 16) |
2165 (tf->feature << 24)
2166 );
2167 crqb->ata_cmd[1] = cpu_to_le32(
2168 (tf->lbal << 0) |
2169 (tf->lbam << 8) |
2170 (tf->lbah << 16) |
2171 (tf->device << 24)
2172 );
2173 crqb->ata_cmd[2] = cpu_to_le32(
2174 (tf->hob_lbal << 0) |
2175 (tf->hob_lbam << 8) |
2176 (tf->hob_lbah << 16) |
2177 (tf->hob_feature << 24)
2178 );
2179 crqb->ata_cmd[3] = cpu_to_le32(
2180 (tf->nsect << 0) |
2181 (tf->hob_nsect << 8)
2182 );
2183
2184 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2185 return;
2186 mv_fill_sg(qc);
2187 }
2188
2189 /**
2190 * mv_sff_check_status - fetch device status, if valid
2191 * @ap: ATA port to fetch status from
2192 *
2193 * When using command issue via mv_qc_issue_fis(),
2194 * the initial ATA_BUSY state does not show up in the
2195 * ATA status (shadow) register. This can confuse libata!
2196 *
2197 * So we have a hook here to fake ATA_BUSY for that situation,
2198 * until the first time a BUSY, DRQ, or ERR bit is seen.
2199 *
2200 * The rest of the time, it simply returns the ATA status register.
2201 */
2202 static u8 mv_sff_check_status(struct ata_port *ap)
2203 {
2204 u8 stat = ioread8(ap->ioaddr.status_addr);
2205 struct mv_port_priv *pp = ap->private_data;
2206
2207 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2208 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2209 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2210 else
2211 stat = ATA_BUSY;
2212 }
2213 return stat;
2214 }
2215
2216 /**
2217 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2218 * @fis: fis to be sent
2219 * @nwords: number of 32-bit words in the fis
2220 */
2221 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2222 {
2223 void __iomem *port_mmio = mv_ap_base(ap);
2224 u32 ifctl, old_ifctl, ifstat;
2225 int i, timeout = 200, final_word = nwords - 1;
2226
2227 /* Initiate FIS transmission mode */
2228 old_ifctl = readl(port_mmio + SATA_IFCTL);
2229 ifctl = 0x100 | (old_ifctl & 0xf);
2230 writelfl(ifctl, port_mmio + SATA_IFCTL);
2231
2232 /* Send all words of the FIS except for the final word */
2233 for (i = 0; i < final_word; ++i)
2234 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2235
2236 /* Flag end-of-transmission, and then send the final word */
2237 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2238 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2239
2240 /*
2241 * Wait for FIS transmission to complete.
2242 * This typically takes just a single iteration.
2243 */
2244 do {
2245 ifstat = readl(port_mmio + SATA_IFSTAT);
2246 } while (!(ifstat & 0x1000) && --timeout);
2247
2248 /* Restore original port configuration */
2249 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2250
2251 /* See if it worked */
2252 if ((ifstat & 0x3000) != 0x1000) {
2253 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2254 __func__, ifstat);
2255 return AC_ERR_OTHER;
2256 }
2257 return 0;
2258 }
2259
2260 /**
2261 * mv_qc_issue_fis - Issue a command directly as a FIS
2262 * @qc: queued command to start
2263 *
2264 * Note that the ATA shadow registers are not updated
2265 * after command issue, so the device will appear "READY"
2266 * if polled, even while it is BUSY processing the command.
2267 *
2268 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2269 *
2270 * Note: we don't get updated shadow regs on *completion*
2271 * of non-data commands. So avoid sending them via this function,
2272 * as they will appear to have completed immediately.
2273 *
2274 * GEN_IIE has special registers that we could get the result tf from,
2275 * but earlier chipsets do not. For now, we ignore those registers.
2276 */
2277 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2278 {
2279 struct ata_port *ap = qc->ap;
2280 struct mv_port_priv *pp = ap->private_data;
2281 struct ata_link *link = qc->dev->link;
2282 u32 fis[5];
2283 int err = 0;
2284
2285 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2286 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2287 if (err)
2288 return err;
2289
2290 switch (qc->tf.protocol) {
2291 case ATAPI_PROT_PIO:
2292 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2293 /* fall through */
2294 case ATAPI_PROT_NODATA:
2295 ap->hsm_task_state = HSM_ST_FIRST;
2296 break;
2297 case ATA_PROT_PIO:
2298 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2299 if (qc->tf.flags & ATA_TFLAG_WRITE)
2300 ap->hsm_task_state = HSM_ST_FIRST;
2301 else
2302 ap->hsm_task_state = HSM_ST;
2303 break;
2304 default:
2305 ap->hsm_task_state = HSM_ST_LAST;
2306 break;
2307 }
2308
2309 if (qc->tf.flags & ATA_TFLAG_POLLING)
2310 ata_sff_queue_pio_task(link, 0);
2311 return 0;
2312 }
2313
2314 /**
2315 * mv_qc_issue - Initiate a command to the host
2316 * @qc: queued command to start
2317 *
2318 * This routine simply redirects to the general purpose routine
2319 * if command is not DMA. Else, it sanity checks our local
2320 * caches of the request producer/consumer indices then enables
2321 * DMA and bumps the request producer index.
2322 *
2323 * LOCKING:
2324 * Inherited from caller.
2325 */
2326 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2327 {
2328 static int limit_warnings = 10;
2329 struct ata_port *ap = qc->ap;
2330 void __iomem *port_mmio = mv_ap_base(ap);
2331 struct mv_port_priv *pp = ap->private_data;
2332 u32 in_index;
2333 unsigned int port_irqs;
2334
2335 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2336
2337 switch (qc->tf.protocol) {
2338 case ATA_PROT_DMA:
2339 if (qc->tf.command == ATA_CMD_DSM) {
2340 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2341 return AC_ERR_OTHER;
2342 break; /* use bmdma for this */
2343 }
2344 /* fall thru */
2345 case ATA_PROT_NCQ:
2346 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2347 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2348 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2349
2350 /* Write the request in pointer to kick the EDMA to life */
2351 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2352 port_mmio + EDMA_REQ_Q_IN_PTR);
2353 return 0;
2354
2355 case ATA_PROT_PIO:
2356 /*
2357 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2358 *
2359 * Someday, we might implement special polling workarounds
2360 * for these, but it all seems rather unnecessary since we
2361 * normally use only DMA for commands which transfer more
2362 * than a single block of data.
2363 *
2364 * Much of the time, this could just work regardless.
2365 * So for now, just log the incident, and allow the attempt.
2366 */
2367 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2368 --limit_warnings;
2369 ata_link_warn(qc->dev->link, DRV_NAME
2370 ": attempting PIO w/multiple DRQ: "
2371 "this may fail due to h/w errata\n");
2372 }
2373 /* drop through */
2374 case ATA_PROT_NODATA:
2375 case ATAPI_PROT_PIO:
2376 case ATAPI_PROT_NODATA:
2377 if (ap->flags & ATA_FLAG_PIO_POLLING)
2378 qc->tf.flags |= ATA_TFLAG_POLLING;
2379 break;
2380 }
2381
2382 if (qc->tf.flags & ATA_TFLAG_POLLING)
2383 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2384 else
2385 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2386
2387 /*
2388 * We're about to send a non-EDMA capable command to the
2389 * port. Turn off EDMA so there won't be problems accessing
2390 * shadow block, etc registers.
2391 */
2392 mv_stop_edma(ap);
2393 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2394 mv_pmp_select(ap, qc->dev->link->pmp);
2395
2396 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2397 struct mv_host_priv *hpriv = ap->host->private_data;
2398 /*
2399 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2400 *
2401 * After any NCQ error, the READ_LOG_EXT command
2402 * from libata-eh *must* use mv_qc_issue_fis().
2403 * Otherwise it might fail, due to chip errata.
2404 *
2405 * Rather than special-case it, we'll just *always*
2406 * use this method here for READ_LOG_EXT, making for
2407 * easier testing.
2408 */
2409 if (IS_GEN_II(hpriv))
2410 return mv_qc_issue_fis(qc);
2411 }
2412 return ata_bmdma_qc_issue(qc);
2413 }
2414
2415 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2416 {
2417 struct mv_port_priv *pp = ap->private_data;
2418 struct ata_queued_cmd *qc;
2419
2420 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2421 return NULL;
2422 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2423 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2424 return qc;
2425 return NULL;
2426 }
2427
2428 static void mv_pmp_error_handler(struct ata_port *ap)
2429 {
2430 unsigned int pmp, pmp_map;
2431 struct mv_port_priv *pp = ap->private_data;
2432
2433 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2434 /*
2435 * Perform NCQ error analysis on failed PMPs
2436 * before we freeze the port entirely.
2437 *
2438 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2439 */
2440 pmp_map = pp->delayed_eh_pmp_map;
2441 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2442 for (pmp = 0; pmp_map != 0; pmp++) {
2443 unsigned int this_pmp = (1 << pmp);
2444 if (pmp_map & this_pmp) {
2445 struct ata_link *link = &ap->pmp_link[pmp];
2446 pmp_map &= ~this_pmp;
2447 ata_eh_analyze_ncq_error(link);
2448 }
2449 }
2450 ata_port_freeze(ap);
2451 }
2452 sata_pmp_error_handler(ap);
2453 }
2454
2455 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2456 {
2457 void __iomem *port_mmio = mv_ap_base(ap);
2458
2459 return readl(port_mmio + SATA_TESTCTL) >> 16;
2460 }
2461
2462 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2463 {
2464 struct ata_eh_info *ehi;
2465 unsigned int pmp;
2466
2467 /*
2468 * Initialize EH info for PMPs which saw device errors
2469 */
2470 ehi = &ap->link.eh_info;
2471 for (pmp = 0; pmp_map != 0; pmp++) {
2472 unsigned int this_pmp = (1 << pmp);
2473 if (pmp_map & this_pmp) {
2474 struct ata_link *link = &ap->pmp_link[pmp];
2475
2476 pmp_map &= ~this_pmp;
2477 ehi = &link->eh_info;
2478 ata_ehi_clear_desc(ehi);
2479 ata_ehi_push_desc(ehi, "dev err");
2480 ehi->err_mask |= AC_ERR_DEV;
2481 ehi->action |= ATA_EH_RESET;
2482 ata_link_abort(link);
2483 }
2484 }
2485 }
2486
2487 static int mv_req_q_empty(struct ata_port *ap)
2488 {
2489 void __iomem *port_mmio = mv_ap_base(ap);
2490 u32 in_ptr, out_ptr;
2491
2492 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2493 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2494 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2495 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2496 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2497 }
2498
2499 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2500 {
2501 struct mv_port_priv *pp = ap->private_data;
2502 int failed_links;
2503 unsigned int old_map, new_map;
2504
2505 /*
2506 * Device error during FBS+NCQ operation:
2507 *
2508 * Set a port flag to prevent further I/O being enqueued.
2509 * Leave the EDMA running to drain outstanding commands from this port.
2510 * Perform the post-mortem/EH only when all responses are complete.
2511 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2512 */
2513 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2514 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2515 pp->delayed_eh_pmp_map = 0;
2516 }
2517 old_map = pp->delayed_eh_pmp_map;
2518 new_map = old_map | mv_get_err_pmp_map(ap);
2519
2520 if (old_map != new_map) {
2521 pp->delayed_eh_pmp_map = new_map;
2522 mv_pmp_eh_prep(ap, new_map & ~old_map);
2523 }
2524 failed_links = hweight16(new_map);
2525
2526 ata_port_info(ap,
2527 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2528 __func__, pp->delayed_eh_pmp_map,
2529 ap->qc_active, failed_links,
2530 ap->nr_active_links);
2531
2532 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2533 mv_process_crpb_entries(ap, pp);
2534 mv_stop_edma(ap);
2535 mv_eh_freeze(ap);
2536 ata_port_info(ap, "%s: done\n", __func__);
2537 return 1; /* handled */
2538 }
2539 ata_port_info(ap, "%s: waiting\n", __func__);
2540 return 1; /* handled */
2541 }
2542
2543 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2544 {
2545 /*
2546 * Possible future enhancement:
2547 *
2548 * FBS+non-NCQ operation is not yet implemented.
2549 * See related notes in mv_edma_cfg().
2550 *
2551 * Device error during FBS+non-NCQ operation:
2552 *
2553 * We need to snapshot the shadow registers for each failed command.
2554 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2555 */
2556 return 0; /* not handled */
2557 }
2558
2559 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2560 {
2561 struct mv_port_priv *pp = ap->private_data;
2562
2563 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2564 return 0; /* EDMA was not active: not handled */
2565 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2566 return 0; /* FBS was not active: not handled */
2567
2568 if (!(edma_err_cause & EDMA_ERR_DEV))
2569 return 0; /* non DEV error: not handled */
2570 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2571 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2572 return 0; /* other problems: not handled */
2573
2574 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2575 /*
2576 * EDMA should NOT have self-disabled for this case.
2577 * If it did, then something is wrong elsewhere,
2578 * and we cannot handle it here.
2579 */
2580 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2581 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2582 __func__, edma_err_cause, pp->pp_flags);
2583 return 0; /* not handled */
2584 }
2585 return mv_handle_fbs_ncq_dev_err(ap);
2586 } else {
2587 /*
2588 * EDMA should have self-disabled for this case.
2589 * If it did not, then something is wrong elsewhere,
2590 * and we cannot handle it here.
2591 */
2592 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2593 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2594 __func__, edma_err_cause, pp->pp_flags);
2595 return 0; /* not handled */
2596 }
2597 return mv_handle_fbs_non_ncq_dev_err(ap);
2598 }
2599 return 0; /* not handled */
2600 }
2601
2602 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2603 {
2604 struct ata_eh_info *ehi = &ap->link.eh_info;
2605 char *when = "idle";
2606
2607 ata_ehi_clear_desc(ehi);
2608 if (edma_was_enabled) {
2609 when = "EDMA enabled";
2610 } else {
2611 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2612 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2613 when = "polling";
2614 }
2615 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2616 ehi->err_mask |= AC_ERR_OTHER;
2617 ehi->action |= ATA_EH_RESET;
2618 ata_port_freeze(ap);
2619 }
2620
2621 /**
2622 * mv_err_intr - Handle error interrupts on the port
2623 * @ap: ATA channel to manipulate
2624 *
2625 * Most cases require a full reset of the chip's state machine,
2626 * which also performs a COMRESET.
2627 * Also, if the port disabled DMA, update our cached copy to match.
2628 *
2629 * LOCKING:
2630 * Inherited from caller.
2631 */
2632 static void mv_err_intr(struct ata_port *ap)
2633 {
2634 void __iomem *port_mmio = mv_ap_base(ap);
2635 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2636 u32 fis_cause = 0;
2637 struct mv_port_priv *pp = ap->private_data;
2638 struct mv_host_priv *hpriv = ap->host->private_data;
2639 unsigned int action = 0, err_mask = 0;
2640 struct ata_eh_info *ehi = &ap->link.eh_info;
2641 struct ata_queued_cmd *qc;
2642 int abort = 0;
2643
2644 /*
2645 * Read and clear the SError and err_cause bits.
2646 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2647 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2648 */
2649 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2650 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2651
2652 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2653 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2654 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2655 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2656 }
2657 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2658
2659 if (edma_err_cause & EDMA_ERR_DEV) {
2660 /*
2661 * Device errors during FIS-based switching operation
2662 * require special handling.
2663 */
2664 if (mv_handle_dev_err(ap, edma_err_cause))
2665 return;
2666 }
2667
2668 qc = mv_get_active_qc(ap);
2669 ata_ehi_clear_desc(ehi);
2670 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2671 edma_err_cause, pp->pp_flags);
2672
2673 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2674 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2675 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2676 u32 ec = edma_err_cause &
2677 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2678 sata_async_notification(ap);
2679 if (!ec)
2680 return; /* Just an AN; no need for the nukes */
2681 ata_ehi_push_desc(ehi, "SDB notify");
2682 }
2683 }
2684 /*
2685 * All generations share these EDMA error cause bits:
2686 */
2687 if (edma_err_cause & EDMA_ERR_DEV) {
2688 err_mask |= AC_ERR_DEV;
2689 action |= ATA_EH_RESET;
2690 ata_ehi_push_desc(ehi, "dev error");
2691 }
2692 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2693 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2694 EDMA_ERR_INTRL_PAR)) {
2695 err_mask |= AC_ERR_ATA_BUS;
2696 action |= ATA_EH_RESET;
2697 ata_ehi_push_desc(ehi, "parity error");
2698 }
2699 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2700 ata_ehi_hotplugged(ehi);
2701 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2702 "dev disconnect" : "dev connect");
2703 action |= ATA_EH_RESET;
2704 }
2705
2706 /*
2707 * Gen-I has a different SELF_DIS bit,
2708 * different FREEZE bits, and no SERR bit:
2709 */
2710 if (IS_GEN_I(hpriv)) {
2711 eh_freeze_mask = EDMA_EH_FREEZE_5;
2712 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2713 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2714 ata_ehi_push_desc(ehi, "EDMA self-disable");
2715 }
2716 } else {
2717 eh_freeze_mask = EDMA_EH_FREEZE;
2718 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2719 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2720 ata_ehi_push_desc(ehi, "EDMA self-disable");
2721 }
2722 if (edma_err_cause & EDMA_ERR_SERR) {
2723 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2724 err_mask |= AC_ERR_ATA_BUS;
2725 action |= ATA_EH_RESET;
2726 }
2727 }
2728
2729 if (!err_mask) {
2730 err_mask = AC_ERR_OTHER;
2731 action |= ATA_EH_RESET;
2732 }
2733
2734 ehi->serror |= serr;
2735 ehi->action |= action;
2736
2737 if (qc)
2738 qc->err_mask |= err_mask;
2739 else
2740 ehi->err_mask |= err_mask;
2741
2742 if (err_mask == AC_ERR_DEV) {
2743 /*
2744 * Cannot do ata_port_freeze() here,
2745 * because it would kill PIO access,
2746 * which is needed for further diagnosis.
2747 */
2748 mv_eh_freeze(ap);
2749 abort = 1;
2750 } else if (edma_err_cause & eh_freeze_mask) {
2751 /*
2752 * Note to self: ata_port_freeze() calls ata_port_abort()
2753 */
2754 ata_port_freeze(ap);
2755 } else {
2756 abort = 1;
2757 }
2758
2759 if (abort) {
2760 if (qc)
2761 ata_link_abort(qc->dev->link);
2762 else
2763 ata_port_abort(ap);
2764 }
2765 }
2766
2767 static bool mv_process_crpb_response(struct ata_port *ap,
2768 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2769 {
2770 u8 ata_status;
2771 u16 edma_status = le16_to_cpu(response->flags);
2772
2773 /*
2774 * edma_status from a response queue entry:
2775 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2776 * MSB is saved ATA status from command completion.
2777 */
2778 if (!ncq_enabled) {
2779 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2780 if (err_cause) {
2781 /*
2782 * Error will be seen/handled by
2783 * mv_err_intr(). So do nothing at all here.
2784 */
2785 return false;
2786 }
2787 }
2788 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2789 if (!ac_err_mask(ata_status))
2790 return true;
2791 /* else: leave it for mv_err_intr() */
2792 return false;
2793 }
2794
2795 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2796 {
2797 void __iomem *port_mmio = mv_ap_base(ap);
2798 struct mv_host_priv *hpriv = ap->host->private_data;
2799 u32 in_index;
2800 bool work_done = false;
2801 u32 done_mask = 0;
2802 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2803
2804 /* Get the hardware queue position index */
2805 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2806 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2807
2808 /* Process new responses from since the last time we looked */
2809 while (in_index != pp->resp_idx) {
2810 unsigned int tag;
2811 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2812
2813 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2814
2815 if (IS_GEN_I(hpriv)) {
2816 /* 50xx: no NCQ, only one command active at a time */
2817 tag = ap->link.active_tag;
2818 } else {
2819 /* Gen II/IIE: get command tag from CRPB entry */
2820 tag = le16_to_cpu(response->id) & 0x1f;
2821 }
2822 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2823 done_mask |= 1 << tag;
2824 work_done = true;
2825 }
2826
2827 if (work_done) {
2828 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2829
2830 /* Update the software queue position index in hardware */
2831 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2832 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2833 port_mmio + EDMA_RSP_Q_OUT_PTR);
2834 }
2835 }
2836
2837 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2838 {
2839 struct mv_port_priv *pp;
2840 int edma_was_enabled;
2841
2842 /*
2843 * Grab a snapshot of the EDMA_EN flag setting,
2844 * so that we have a consistent view for this port,
2845 * even if something we call of our routines changes it.
2846 */
2847 pp = ap->private_data;
2848 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2849 /*
2850 * Process completed CRPB response(s) before other events.
2851 */
2852 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2853 mv_process_crpb_entries(ap, pp);
2854 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2855 mv_handle_fbs_ncq_dev_err(ap);
2856 }
2857 /*
2858 * Handle chip-reported errors, or continue on to handle PIO.
2859 */
2860 if (unlikely(port_cause & ERR_IRQ)) {
2861 mv_err_intr(ap);
2862 } else if (!edma_was_enabled) {
2863 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2864 if (qc)
2865 ata_bmdma_port_intr(ap, qc);
2866 else
2867 mv_unexpected_intr(ap, edma_was_enabled);
2868 }
2869 }
2870
2871 /**
2872 * mv_host_intr - Handle all interrupts on the given host controller
2873 * @host: host specific structure
2874 * @main_irq_cause: Main interrupt cause register for the chip.
2875 *
2876 * LOCKING:
2877 * Inherited from caller.
2878 */
2879 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2880 {
2881 struct mv_host_priv *hpriv = host->private_data;
2882 void __iomem *mmio = hpriv->base, *hc_mmio;
2883 unsigned int handled = 0, port;
2884
2885 /* If asserted, clear the "all ports" IRQ coalescing bit */
2886 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2887 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2888
2889 for (port = 0; port < hpriv->n_ports; port++) {
2890 struct ata_port *ap = host->ports[port];
2891 unsigned int p, shift, hardport, port_cause;
2892
2893 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2894 /*
2895 * Each hc within the host has its own hc_irq_cause register,
2896 * where the interrupting ports bits get ack'd.
2897 */
2898 if (hardport == 0) { /* first port on this hc ? */
2899 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2900 u32 port_mask, ack_irqs;
2901 /*
2902 * Skip this entire hc if nothing pending for any ports
2903 */
2904 if (!hc_cause) {
2905 port += MV_PORTS_PER_HC - 1;
2906 continue;
2907 }
2908 /*
2909 * We don't need/want to read the hc_irq_cause register,
2910 * because doing so hurts performance, and
2911 * main_irq_cause already gives us everything we need.
2912 *
2913 * But we do have to *write* to the hc_irq_cause to ack
2914 * the ports that we are handling this time through.
2915 *
2916 * This requires that we create a bitmap for those
2917 * ports which interrupted us, and use that bitmap
2918 * to ack (only) those ports via hc_irq_cause.
2919 */
2920 ack_irqs = 0;
2921 if (hc_cause & PORTS_0_3_COAL_DONE)
2922 ack_irqs = HC_COAL_IRQ;
2923 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2924 if ((port + p) >= hpriv->n_ports)
2925 break;
2926 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2927 if (hc_cause & port_mask)
2928 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2929 }
2930 hc_mmio = mv_hc_base_from_port(mmio, port);
2931 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2932 handled = 1;
2933 }
2934 /*
2935 * Handle interrupts signalled for this port:
2936 */
2937 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2938 if (port_cause)
2939 mv_port_intr(ap, port_cause);
2940 }
2941 return handled;
2942 }
2943
2944 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2945 {
2946 struct mv_host_priv *hpriv = host->private_data;
2947 struct ata_port *ap;
2948 struct ata_queued_cmd *qc;
2949 struct ata_eh_info *ehi;
2950 unsigned int i, err_mask, printed = 0;
2951 u32 err_cause;
2952
2953 err_cause = readl(mmio + hpriv->irq_cause_offset);
2954
2955 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
2956
2957 DPRINTK("All regs @ PCI error\n");
2958 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2959
2960 writelfl(0, mmio + hpriv->irq_cause_offset);
2961
2962 for (i = 0; i < host->n_ports; i++) {
2963 ap = host->ports[i];
2964 if (!ata_link_offline(&ap->link)) {
2965 ehi = &ap->link.eh_info;
2966 ata_ehi_clear_desc(ehi);
2967 if (!printed++)
2968 ata_ehi_push_desc(ehi,
2969 "PCI err cause 0x%08x", err_cause);
2970 err_mask = AC_ERR_HOST_BUS;
2971 ehi->action = ATA_EH_RESET;
2972 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2973 if (qc)
2974 qc->err_mask |= err_mask;
2975 else
2976 ehi->err_mask |= err_mask;
2977
2978 ata_port_freeze(ap);
2979 }
2980 }
2981 return 1; /* handled */
2982 }
2983
2984 /**
2985 * mv_interrupt - Main interrupt event handler
2986 * @irq: unused
2987 * @dev_instance: private data; in this case the host structure
2988 *
2989 * Read the read only register to determine if any host
2990 * controllers have pending interrupts. If so, call lower level
2991 * routine to handle. Also check for PCI errors which are only
2992 * reported here.
2993 *
2994 * LOCKING:
2995 * This routine holds the host lock while processing pending
2996 * interrupts.
2997 */
2998 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2999 {
3000 struct ata_host *host = dev_instance;
3001 struct mv_host_priv *hpriv = host->private_data;
3002 unsigned int handled = 0;
3003 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
3004 u32 main_irq_cause, pending_irqs;
3005
3006 spin_lock(&host->lock);
3007
3008 /* for MSI: block new interrupts while in here */
3009 if (using_msi)
3010 mv_write_main_irq_mask(0, hpriv);
3011
3012 main_irq_cause = readl(hpriv->main_irq_cause_addr);
3013 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
3014 /*
3015 * Deal with cases where we either have nothing pending, or have read
3016 * a bogus register value which can indicate HW removal or PCI fault.
3017 */
3018 if (pending_irqs && main_irq_cause != 0xffffffffU) {
3019 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
3020 handled = mv_pci_error(host, hpriv->base);
3021 else
3022 handled = mv_host_intr(host, pending_irqs);
3023 }
3024
3025 /* for MSI: unmask; interrupt cause bits will retrigger now */
3026 if (using_msi)
3027 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
3028
3029 spin_unlock(&host->lock);
3030
3031 return IRQ_RETVAL(handled);
3032 }
3033
3034 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3035 {
3036 unsigned int ofs;
3037
3038 switch (sc_reg_in) {
3039 case SCR_STATUS:
3040 case SCR_ERROR:
3041 case SCR_CONTROL:
3042 ofs = sc_reg_in * sizeof(u32);
3043 break;
3044 default:
3045 ofs = 0xffffffffU;
3046 break;
3047 }
3048 return ofs;
3049 }
3050
3051 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3052 {
3053 struct mv_host_priv *hpriv = link->ap->host->private_data;
3054 void __iomem *mmio = hpriv->base;
3055 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3056 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3057
3058 if (ofs != 0xffffffffU) {
3059 *val = readl(addr + ofs);
3060 return 0;
3061 } else
3062 return -EINVAL;
3063 }
3064
3065 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3066 {
3067 struct mv_host_priv *hpriv = link->ap->host->private_data;
3068 void __iomem *mmio = hpriv->base;
3069 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3070 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3071
3072 if (ofs != 0xffffffffU) {
3073 writelfl(val, addr + ofs);
3074 return 0;
3075 } else
3076 return -EINVAL;
3077 }
3078
3079 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3080 {
3081 struct pci_dev *pdev = to_pci_dev(host->dev);
3082 int early_5080;
3083
3084 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3085
3086 if (!early_5080) {
3087 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3088 tmp |= (1 << 0);
3089 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3090 }
3091
3092 mv_reset_pci_bus(host, mmio);
3093 }
3094
3095 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3096 {
3097 writel(0x0fcfffff, mmio + FLASH_CTL);
3098 }
3099
3100 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3101 void __iomem *mmio)
3102 {
3103 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3104 u32 tmp;
3105
3106 tmp = readl(phy_mmio + MV5_PHY_MODE);
3107
3108 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3109 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3110 }
3111
3112 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3113 {
3114 u32 tmp;
3115
3116 writel(0, mmio + GPIO_PORT_CTL);
3117
3118 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3119
3120 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3121 tmp |= ~(1 << 0);
3122 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3123 }
3124
3125 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3126 unsigned int port)
3127 {
3128 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3129 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3130 u32 tmp;
3131 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3132
3133 if (fix_apm_sq) {
3134 tmp = readl(phy_mmio + MV5_LTMODE);
3135 tmp |= (1 << 19);
3136 writel(tmp, phy_mmio + MV5_LTMODE);
3137
3138 tmp = readl(phy_mmio + MV5_PHY_CTL);
3139 tmp &= ~0x3;
3140 tmp |= 0x1;
3141 writel(tmp, phy_mmio + MV5_PHY_CTL);
3142 }
3143
3144 tmp = readl(phy_mmio + MV5_PHY_MODE);
3145 tmp &= ~mask;
3146 tmp |= hpriv->signal[port].pre;
3147 tmp |= hpriv->signal[port].amps;
3148 writel(tmp, phy_mmio + MV5_PHY_MODE);
3149 }
3150
3151
3152 #undef ZERO
3153 #define ZERO(reg) writel(0, port_mmio + (reg))
3154 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3155 unsigned int port)
3156 {
3157 void __iomem *port_mmio = mv_port_base(mmio, port);
3158
3159 mv_reset_channel(hpriv, mmio, port);
3160
3161 ZERO(0x028); /* command */
3162 writel(0x11f, port_mmio + EDMA_CFG);
3163 ZERO(0x004); /* timer */
3164 ZERO(0x008); /* irq err cause */
3165 ZERO(0x00c); /* irq err mask */
3166 ZERO(0x010); /* rq bah */
3167 ZERO(0x014); /* rq inp */
3168 ZERO(0x018); /* rq outp */
3169 ZERO(0x01c); /* respq bah */
3170 ZERO(0x024); /* respq outp */
3171 ZERO(0x020); /* respq inp */
3172 ZERO(0x02c); /* test control */
3173 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3174 }
3175 #undef ZERO
3176
3177 #define ZERO(reg) writel(0, hc_mmio + (reg))
3178 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3179 unsigned int hc)
3180 {
3181 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3182 u32 tmp;
3183
3184 ZERO(0x00c);
3185 ZERO(0x010);
3186 ZERO(0x014);
3187 ZERO(0x018);
3188
3189 tmp = readl(hc_mmio + 0x20);
3190 tmp &= 0x1c1c1c1c;
3191 tmp |= 0x03030303;
3192 writel(tmp, hc_mmio + 0x20);
3193 }
3194 #undef ZERO
3195
3196 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3197 unsigned int n_hc)
3198 {
3199 unsigned int hc, port;
3200
3201 for (hc = 0; hc < n_hc; hc++) {
3202 for (port = 0; port < MV_PORTS_PER_HC; port++)
3203 mv5_reset_hc_port(hpriv, mmio,
3204 (hc * MV_PORTS_PER_HC) + port);
3205
3206 mv5_reset_one_hc(hpriv, mmio, hc);
3207 }
3208
3209 return 0;
3210 }
3211
3212 #undef ZERO
3213 #define ZERO(reg) writel(0, mmio + (reg))
3214 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3215 {
3216 struct mv_host_priv *hpriv = host->private_data;
3217 u32 tmp;
3218
3219 tmp = readl(mmio + MV_PCI_MODE);
3220 tmp &= 0xff00ffff;
3221 writel(tmp, mmio + MV_PCI_MODE);
3222
3223 ZERO(MV_PCI_DISC_TIMER);
3224 ZERO(MV_PCI_MSI_TRIGGER);
3225 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3226 ZERO(MV_PCI_SERR_MASK);
3227 ZERO(hpriv->irq_cause_offset);
3228 ZERO(hpriv->irq_mask_offset);
3229 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3230 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3231 ZERO(MV_PCI_ERR_ATTRIBUTE);
3232 ZERO(MV_PCI_ERR_COMMAND);
3233 }
3234 #undef ZERO
3235
3236 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3237 {
3238 u32 tmp;
3239
3240 mv5_reset_flash(hpriv, mmio);
3241
3242 tmp = readl(mmio + GPIO_PORT_CTL);
3243 tmp &= 0x3;
3244 tmp |= (1 << 5) | (1 << 6);
3245 writel(tmp, mmio + GPIO_PORT_CTL);
3246 }
3247
3248 /**
3249 * mv6_reset_hc - Perform the 6xxx global soft reset
3250 * @mmio: base address of the HBA
3251 *
3252 * This routine only applies to 6xxx parts.
3253 *
3254 * LOCKING:
3255 * Inherited from caller.
3256 */
3257 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3258 unsigned int n_hc)
3259 {
3260 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3261 int i, rc = 0;
3262 u32 t;
3263
3264 /* Following procedure defined in PCI "main command and status
3265 * register" table.
3266 */
3267 t = readl(reg);
3268 writel(t | STOP_PCI_MASTER, reg);
3269
3270 for (i = 0; i < 1000; i++) {
3271 udelay(1);
3272 t = readl(reg);
3273 if (PCI_MASTER_EMPTY & t)
3274 break;
3275 }
3276 if (!(PCI_MASTER_EMPTY & t)) {
3277 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3278 rc = 1;
3279 goto done;
3280 }
3281
3282 /* set reset */
3283 i = 5;
3284 do {
3285 writel(t | GLOB_SFT_RST, reg);
3286 t = readl(reg);
3287 udelay(1);
3288 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3289
3290 if (!(GLOB_SFT_RST & t)) {
3291 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3292 rc = 1;
3293 goto done;
3294 }
3295
3296 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3297 i = 5;
3298 do {
3299 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3300 t = readl(reg);
3301 udelay(1);
3302 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3303
3304 if (GLOB_SFT_RST & t) {
3305 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3306 rc = 1;
3307 }
3308 done:
3309 return rc;
3310 }
3311
3312 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3313 void __iomem *mmio)
3314 {
3315 void __iomem *port_mmio;
3316 u32 tmp;
3317
3318 tmp = readl(mmio + RESET_CFG);
3319 if ((tmp & (1 << 0)) == 0) {
3320 hpriv->signal[idx].amps = 0x7 << 8;
3321 hpriv->signal[idx].pre = 0x1 << 5;
3322 return;
3323 }
3324
3325 port_mmio = mv_port_base(mmio, idx);
3326 tmp = readl(port_mmio + PHY_MODE2);
3327
3328 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3329 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3330 }
3331
3332 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3333 {
3334 writel(0x00000060, mmio + GPIO_PORT_CTL);
3335 }
3336
3337 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3338 unsigned int port)
3339 {
3340 void __iomem *port_mmio = mv_port_base(mmio, port);
3341
3342 u32 hp_flags = hpriv->hp_flags;
3343 int fix_phy_mode2 =
3344 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3345 int fix_phy_mode4 =
3346 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3347 u32 m2, m3;
3348
3349 if (fix_phy_mode2) {
3350 m2 = readl(port_mmio + PHY_MODE2);
3351 m2 &= ~(1 << 16);
3352 m2 |= (1 << 31);
3353 writel(m2, port_mmio + PHY_MODE2);
3354
3355 udelay(200);
3356
3357 m2 = readl(port_mmio + PHY_MODE2);
3358 m2 &= ~((1 << 16) | (1 << 31));
3359 writel(m2, port_mmio + PHY_MODE2);
3360
3361 udelay(200);
3362 }
3363
3364 /*
3365 * Gen-II/IIe PHY_MODE3 errata RM#2:
3366 * Achieves better receiver noise performance than the h/w default:
3367 */
3368 m3 = readl(port_mmio + PHY_MODE3);
3369 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3370
3371 /* Guideline 88F5182 (GL# SATA-S11) */
3372 if (IS_SOC(hpriv))
3373 m3 &= ~0x1c;
3374
3375 if (fix_phy_mode4) {
3376 u32 m4 = readl(port_mmio + PHY_MODE4);
3377 /*
3378 * Enforce reserved-bit restrictions on GenIIe devices only.
3379 * For earlier chipsets, force only the internal config field
3380 * (workaround for errata FEr SATA#10 part 1).
3381 */
3382 if (IS_GEN_IIE(hpriv))
3383 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3384 else
3385 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3386 writel(m4, port_mmio + PHY_MODE4);
3387 }
3388 /*
3389 * Workaround for 60x1-B2 errata SATA#13:
3390 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3391 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3392 * Or ensure we use writelfl() when writing PHY_MODE4.
3393 */
3394 writel(m3, port_mmio + PHY_MODE3);
3395
3396 /* Revert values of pre-emphasis and signal amps to the saved ones */
3397 m2 = readl(port_mmio + PHY_MODE2);
3398
3399 m2 &= ~MV_M2_PREAMP_MASK;
3400 m2 |= hpriv->signal[port].amps;
3401 m2 |= hpriv->signal[port].pre;
3402 m2 &= ~(1 << 16);
3403
3404 /* according to mvSata 3.6.1, some IIE values are fixed */
3405 if (IS_GEN_IIE(hpriv)) {
3406 m2 &= ~0xC30FF01F;
3407 m2 |= 0x0000900F;
3408 }
3409
3410 writel(m2, port_mmio + PHY_MODE2);
3411 }
3412
3413 /* TODO: use the generic LED interface to configure the SATA Presence */
3414 /* & Acitivy LEDs on the board */
3415 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3416 void __iomem *mmio)
3417 {
3418 return;
3419 }
3420
3421 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3422 void __iomem *mmio)
3423 {
3424 void __iomem *port_mmio;
3425 u32 tmp;
3426
3427 port_mmio = mv_port_base(mmio, idx);
3428 tmp = readl(port_mmio + PHY_MODE2);
3429
3430 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3431 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3432 }
3433
3434 #undef ZERO
3435 #define ZERO(reg) writel(0, port_mmio + (reg))
3436 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3437 void __iomem *mmio, unsigned int port)
3438 {
3439 void __iomem *port_mmio = mv_port_base(mmio, port);
3440
3441 mv_reset_channel(hpriv, mmio, port);
3442
3443 ZERO(0x028); /* command */
3444 writel(0x101f, port_mmio + EDMA_CFG);
3445 ZERO(0x004); /* timer */
3446 ZERO(0x008); /* irq err cause */
3447 ZERO(0x00c); /* irq err mask */
3448 ZERO(0x010); /* rq bah */
3449 ZERO(0x014); /* rq inp */
3450 ZERO(0x018); /* rq outp */
3451 ZERO(0x01c); /* respq bah */
3452 ZERO(0x024); /* respq outp */
3453 ZERO(0x020); /* respq inp */
3454 ZERO(0x02c); /* test control */
3455 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3456 }
3457
3458 #undef ZERO
3459
3460 #define ZERO(reg) writel(0, hc_mmio + (reg))
3461 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3462 void __iomem *mmio)
3463 {
3464 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3465
3466 ZERO(0x00c);
3467 ZERO(0x010);
3468 ZERO(0x014);
3469
3470 }
3471
3472 #undef ZERO
3473
3474 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3475 void __iomem *mmio, unsigned int n_hc)
3476 {
3477 unsigned int port;
3478
3479 for (port = 0; port < hpriv->n_ports; port++)
3480 mv_soc_reset_hc_port(hpriv, mmio, port);
3481
3482 mv_soc_reset_one_hc(hpriv, mmio);
3483
3484 return 0;
3485 }
3486
3487 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3488 void __iomem *mmio)
3489 {
3490 return;
3491 }
3492
3493 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3494 {
3495 return;
3496 }
3497
3498 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3499 void __iomem *mmio, unsigned int port)
3500 {
3501 void __iomem *port_mmio = mv_port_base(mmio, port);
3502 u32 reg;
3503
3504 reg = readl(port_mmio + PHY_MODE3);
3505 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3506 reg |= (0x1 << 27);
3507 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3508 reg |= (0x1 << 29);
3509 writel(reg, port_mmio + PHY_MODE3);
3510
3511 reg = readl(port_mmio + PHY_MODE4);
3512 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3513 reg |= (0x1 << 16);
3514 writel(reg, port_mmio + PHY_MODE4);
3515
3516 reg = readl(port_mmio + PHY_MODE9_GEN2);
3517 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3518 reg |= 0x8;
3519 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3520 writel(reg, port_mmio + PHY_MODE9_GEN2);
3521
3522 reg = readl(port_mmio + PHY_MODE9_GEN1);
3523 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3524 reg |= 0x8;
3525 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3526 writel(reg, port_mmio + PHY_MODE9_GEN1);
3527 }
3528
3529 /**
3530 * soc_is_65 - check if the soc is 65 nano device
3531 *
3532 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3533 * register, this register should contain non-zero value and it exists only
3534 * in the 65 nano devices, when reading it from older devices we get 0.
3535 */
3536 static bool soc_is_65n(struct mv_host_priv *hpriv)
3537 {
3538 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3539
3540 if (readl(port0_mmio + PHYCFG_OFS))
3541 return true;
3542 return false;
3543 }
3544
3545 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3546 {
3547 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3548
3549 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3550 if (want_gen2i)
3551 ifcfg |= (1 << 7); /* enable gen2i speed */
3552 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3553 }
3554
3555 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3556 unsigned int port_no)
3557 {
3558 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3559
3560 /*
3561 * The datasheet warns against setting EDMA_RESET when EDMA is active
3562 * (but doesn't say what the problem might be). So we first try
3563 * to disable the EDMA engine before doing the EDMA_RESET operation.
3564 */
3565 mv_stop_edma_engine(port_mmio);
3566 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3567
3568 if (!IS_GEN_I(hpriv)) {
3569 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3570 mv_setup_ifcfg(port_mmio, 1);
3571 }
3572 /*
3573 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3574 * link, and physical layers. It resets all SATA interface registers
3575 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3576 */
3577 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3578 udelay(25); /* allow reset propagation */
3579 writelfl(0, port_mmio + EDMA_CMD);
3580
3581 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3582
3583 if (IS_GEN_I(hpriv))
3584 mdelay(1);
3585 }
3586
3587 static void mv_pmp_select(struct ata_port *ap, int pmp)
3588 {
3589 if (sata_pmp_supported(ap)) {
3590 void __iomem *port_mmio = mv_ap_base(ap);
3591 u32 reg = readl(port_mmio + SATA_IFCTL);
3592 int old = reg & 0xf;
3593
3594 if (old != pmp) {
3595 reg = (reg & ~0xf) | pmp;
3596 writelfl(reg, port_mmio + SATA_IFCTL);
3597 }
3598 }
3599 }
3600
3601 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3602 unsigned long deadline)
3603 {
3604 mv_pmp_select(link->ap, sata_srst_pmp(link));
3605 return sata_std_hardreset(link, class, deadline);
3606 }
3607
3608 static int mv_softreset(struct ata_link *link, unsigned int *class,
3609 unsigned long deadline)
3610 {
3611 mv_pmp_select(link->ap, sata_srst_pmp(link));
3612 return ata_sff_softreset(link, class, deadline);
3613 }
3614
3615 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3616 unsigned long deadline)
3617 {
3618 struct ata_port *ap = link->ap;
3619 struct mv_host_priv *hpriv = ap->host->private_data;
3620 struct mv_port_priv *pp = ap->private_data;
3621 void __iomem *mmio = hpriv->base;
3622 int rc, attempts = 0, extra = 0;
3623 u32 sstatus;
3624 bool online;
3625
3626 mv_reset_channel(hpriv, mmio, ap->port_no);
3627 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3628 pp->pp_flags &=
3629 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3630
3631 /* Workaround for errata FEr SATA#10 (part 2) */
3632 do {
3633 const unsigned long *timing =
3634 sata_ehc_deb_timing(&link->eh_context);
3635
3636 rc = sata_link_hardreset(link, timing, deadline + extra,
3637 &online, NULL);
3638 rc = online ? -EAGAIN : rc;
3639 if (rc)
3640 return rc;
3641 sata_scr_read(link, SCR_STATUS, &sstatus);
3642 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3643 /* Force 1.5gb/s link speed and try again */
3644 mv_setup_ifcfg(mv_ap_base(ap), 0);
3645 if (time_after(jiffies + HZ, deadline))
3646 extra = HZ; /* only extend it once, max */
3647 }
3648 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3649 mv_save_cached_regs(ap);
3650 mv_edma_cfg(ap, 0, 0);
3651
3652 return rc;
3653 }
3654
3655 static void mv_eh_freeze(struct ata_port *ap)
3656 {
3657 mv_stop_edma(ap);
3658 mv_enable_port_irqs(ap, 0);
3659 }
3660
3661 static void mv_eh_thaw(struct ata_port *ap)
3662 {
3663 struct mv_host_priv *hpriv = ap->host->private_data;
3664 unsigned int port = ap->port_no;
3665 unsigned int hardport = mv_hardport_from_port(port);
3666 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3667 void __iomem *port_mmio = mv_ap_base(ap);
3668 u32 hc_irq_cause;
3669
3670 /* clear EDMA errors on this port */
3671 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3672
3673 /* clear pending irq events */
3674 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3675 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3676
3677 mv_enable_port_irqs(ap, ERR_IRQ);
3678 }
3679
3680 /**
3681 * mv_port_init - Perform some early initialization on a single port.
3682 * @port: libata data structure storing shadow register addresses
3683 * @port_mmio: base address of the port
3684 *
3685 * Initialize shadow register mmio addresses, clear outstanding
3686 * interrupts on the port, and unmask interrupts for the future
3687 * start of the port.
3688 *
3689 * LOCKING:
3690 * Inherited from caller.
3691 */
3692 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3693 {
3694 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3695
3696 /* PIO related setup
3697 */
3698 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3699 port->error_addr =
3700 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3701 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3702 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3703 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3704 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3705 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3706 port->status_addr =
3707 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3708 /* special case: control/altstatus doesn't have ATA_REG_ address */
3709 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3710
3711 /* Clear any currently outstanding port interrupt conditions */
3712 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3713 writelfl(readl(serr), serr);
3714 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3715
3716 /* unmask all non-transient EDMA error interrupts */
3717 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3718
3719 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3720 readl(port_mmio + EDMA_CFG),
3721 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3722 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3723 }
3724
3725 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3726 {
3727 struct mv_host_priv *hpriv = host->private_data;
3728 void __iomem *mmio = hpriv->base;
3729 u32 reg;
3730
3731 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3732 return 0; /* not PCI-X capable */
3733 reg = readl(mmio + MV_PCI_MODE);
3734 if ((reg & MV_PCI_MODE_MASK) == 0)
3735 return 0; /* conventional PCI mode */
3736 return 1; /* chip is in PCI-X mode */
3737 }
3738
3739 static int mv_pci_cut_through_okay(struct ata_host *host)
3740 {
3741 struct mv_host_priv *hpriv = host->private_data;
3742 void __iomem *mmio = hpriv->base;
3743 u32 reg;
3744
3745 if (!mv_in_pcix_mode(host)) {
3746 reg = readl(mmio + MV_PCI_COMMAND);
3747 if (reg & MV_PCI_COMMAND_MRDTRIG)
3748 return 0; /* not okay */
3749 }
3750 return 1; /* okay */
3751 }
3752
3753 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3754 {
3755 struct mv_host_priv *hpriv = host->private_data;
3756 void __iomem *mmio = hpriv->base;
3757
3758 /* workaround for 60x1-B2 errata PCI#7 */
3759 if (mv_in_pcix_mode(host)) {
3760 u32 reg = readl(mmio + MV_PCI_COMMAND);
3761 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3762 }
3763 }
3764
3765 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3766 {
3767 struct pci_dev *pdev = to_pci_dev(host->dev);
3768 struct mv_host_priv *hpriv = host->private_data;
3769 u32 hp_flags = hpriv->hp_flags;
3770
3771 switch (board_idx) {
3772 case chip_5080:
3773 hpriv->ops = &mv5xxx_ops;
3774 hp_flags |= MV_HP_GEN_I;
3775
3776 switch (pdev->revision) {
3777 case 0x1:
3778 hp_flags |= MV_HP_ERRATA_50XXB0;
3779 break;
3780 case 0x3:
3781 hp_flags |= MV_HP_ERRATA_50XXB2;
3782 break;
3783 default:
3784 dev_warn(&pdev->dev,
3785 "Applying 50XXB2 workarounds to unknown rev\n");
3786 hp_flags |= MV_HP_ERRATA_50XXB2;
3787 break;
3788 }
3789 break;
3790
3791 case chip_504x:
3792 case chip_508x:
3793 hpriv->ops = &mv5xxx_ops;
3794 hp_flags |= MV_HP_GEN_I;
3795
3796 switch (pdev->revision) {
3797 case 0x0:
3798 hp_flags |= MV_HP_ERRATA_50XXB0;
3799 break;
3800 case 0x3:
3801 hp_flags |= MV_HP_ERRATA_50XXB2;
3802 break;
3803 default:
3804 dev_warn(&pdev->dev,
3805 "Applying B2 workarounds to unknown rev\n");
3806 hp_flags |= MV_HP_ERRATA_50XXB2;
3807 break;
3808 }
3809 break;
3810
3811 case chip_604x:
3812 case chip_608x:
3813 hpriv->ops = &mv6xxx_ops;
3814 hp_flags |= MV_HP_GEN_II;
3815
3816 switch (pdev->revision) {
3817 case 0x7:
3818 mv_60x1b2_errata_pci7(host);
3819 hp_flags |= MV_HP_ERRATA_60X1B2;
3820 break;
3821 case 0x9:
3822 hp_flags |= MV_HP_ERRATA_60X1C0;
3823 break;
3824 default:
3825 dev_warn(&pdev->dev,
3826 "Applying B2 workarounds to unknown rev\n");
3827 hp_flags |= MV_HP_ERRATA_60X1B2;
3828 break;
3829 }
3830 break;
3831
3832 case chip_7042:
3833 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3834 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3835 (pdev->device == 0x2300 || pdev->device == 0x2310))
3836 {
3837 /*
3838 * Highpoint RocketRAID PCIe 23xx series cards:
3839 *
3840 * Unconfigured drives are treated as "Legacy"
3841 * by the BIOS, and it overwrites sector 8 with
3842 * a "Lgcy" metadata block prior to Linux boot.
3843 *
3844 * Configured drives (RAID or JBOD) leave sector 8
3845 * alone, but instead overwrite a high numbered
3846 * sector for the RAID metadata. This sector can
3847 * be determined exactly, by truncating the physical
3848 * drive capacity to a nice even GB value.
3849 *
3850 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3851 *
3852 * Warn the user, lest they think we're just buggy.
3853 */
3854 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3855 " BIOS CORRUPTS DATA on all attached drives,"
3856 " regardless of if/how they are configured."
3857 " BEWARE!\n");
3858 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3859 " use sectors 8-9 on \"Legacy\" drives,"
3860 " and avoid the final two gigabytes on"
3861 " all RocketRAID BIOS initialized drives.\n");
3862 }
3863 /* drop through */
3864 case chip_6042:
3865 hpriv->ops = &mv6xxx_ops;
3866 hp_flags |= MV_HP_GEN_IIE;
3867 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3868 hp_flags |= MV_HP_CUT_THROUGH;
3869
3870 switch (pdev->revision) {
3871 case 0x2: /* Rev.B0: the first/only public release */
3872 hp_flags |= MV_HP_ERRATA_60X1C0;
3873 break;
3874 default:
3875 dev_warn(&pdev->dev,
3876 "Applying 60X1C0 workarounds to unknown rev\n");
3877 hp_flags |= MV_HP_ERRATA_60X1C0;
3878 break;
3879 }
3880 break;
3881 case chip_soc:
3882 if (soc_is_65n(hpriv))
3883 hpriv->ops = &mv_soc_65n_ops;
3884 else
3885 hpriv->ops = &mv_soc_ops;
3886 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3887 MV_HP_ERRATA_60X1C0;
3888 break;
3889
3890 default:
3891 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
3892 return 1;
3893 }
3894
3895 hpriv->hp_flags = hp_flags;
3896 if (hp_flags & MV_HP_PCIE) {
3897 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3898 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3899 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3900 } else {
3901 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3902 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3903 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3904 }
3905
3906 return 0;
3907 }
3908
3909 /**
3910 * mv_init_host - Perform some early initialization of the host.
3911 * @host: ATA host to initialize
3912 *
3913 * If possible, do an early global reset of the host. Then do
3914 * our port init and clear/unmask all/relevant host interrupts.
3915 *
3916 * LOCKING:
3917 * Inherited from caller.
3918 */
3919 static int mv_init_host(struct ata_host *host)
3920 {
3921 int rc = 0, n_hc, port, hc;
3922 struct mv_host_priv *hpriv = host->private_data;
3923 void __iomem *mmio = hpriv->base;
3924
3925 rc = mv_chip_id(host, hpriv->board_idx);
3926 if (rc)
3927 goto done;
3928
3929 if (IS_SOC(hpriv)) {
3930 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3931 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3932 } else {
3933 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3934 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3935 }
3936
3937 /* initialize shadow irq mask with register's value */
3938 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3939
3940 /* global interrupt mask: 0 == mask everything */
3941 mv_set_main_irq_mask(host, ~0, 0);
3942
3943 n_hc = mv_get_hc_count(host->ports[0]->flags);
3944
3945 for (port = 0; port < host->n_ports; port++)
3946 if (hpriv->ops->read_preamp)
3947 hpriv->ops->read_preamp(hpriv, port, mmio);
3948
3949 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3950 if (rc)
3951 goto done;
3952
3953 hpriv->ops->reset_flash(hpriv, mmio);
3954 hpriv->ops->reset_bus(host, mmio);
3955 hpriv->ops->enable_leds(hpriv, mmio);
3956
3957 for (port = 0; port < host->n_ports; port++) {
3958 struct ata_port *ap = host->ports[port];
3959 void __iomem *port_mmio = mv_port_base(mmio, port);
3960
3961 mv_port_init(&ap->ioaddr, port_mmio);
3962 }
3963
3964 for (hc = 0; hc < n_hc; hc++) {
3965 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3966
3967 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3968 "(before clear)=0x%08x\n", hc,
3969 readl(hc_mmio + HC_CFG),
3970 readl(hc_mmio + HC_IRQ_CAUSE));
3971
3972 /* Clear any currently outstanding hc interrupt conditions */
3973 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3974 }
3975
3976 if (!IS_SOC(hpriv)) {
3977 /* Clear any currently outstanding host interrupt conditions */
3978 writelfl(0, mmio + hpriv->irq_cause_offset);
3979
3980 /* and unmask interrupt generation for host regs */
3981 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3982 }
3983
3984 /*
3985 * enable only global host interrupts for now.
3986 * The per-port interrupts get done later as ports are set up.
3987 */
3988 mv_set_main_irq_mask(host, 0, PCI_ERR);
3989 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3990 irq_coalescing_usecs);
3991 done:
3992 return rc;
3993 }
3994
3995 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3996 {
3997 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3998 MV_CRQB_Q_SZ, 0);
3999 if (!hpriv->crqb_pool)
4000 return -ENOMEM;
4001
4002 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
4003 MV_CRPB_Q_SZ, 0);
4004 if (!hpriv->crpb_pool)
4005 return -ENOMEM;
4006
4007 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
4008 MV_SG_TBL_SZ, 0);
4009 if (!hpriv->sg_tbl_pool)
4010 return -ENOMEM;
4011
4012 return 0;
4013 }
4014
4015 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
4016 const struct mbus_dram_target_info *dram)
4017 {
4018 int i;
4019
4020 for (i = 0; i < 4; i++) {
4021 writel(0, hpriv->base + WINDOW_CTRL(i));
4022 writel(0, hpriv->base + WINDOW_BASE(i));
4023 }
4024
4025 for (i = 0; i < dram->num_cs; i++) {
4026 const struct mbus_dram_window *cs = dram->cs + i;
4027
4028 writel(((cs->size - 1) & 0xffff0000) |
4029 (cs->mbus_attr << 8) |
4030 (dram->mbus_dram_target_id << 4) | 1,
4031 hpriv->base + WINDOW_CTRL(i));
4032 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4033 }
4034 }
4035
4036 /**
4037 * mv_platform_probe - handle a positive probe of an soc Marvell
4038 * host
4039 * @pdev: platform device found
4040 *
4041 * LOCKING:
4042 * Inherited from caller.
4043 */
4044 static int mv_platform_probe(struct platform_device *pdev)
4045 {
4046 const struct mv_sata_platform_data *mv_platform_data;
4047 const struct mbus_dram_target_info *dram;
4048 const struct ata_port_info *ppi[] =
4049 { &mv_port_info[chip_soc], NULL };
4050 struct ata_host *host;
4051 struct mv_host_priv *hpriv;
4052 struct resource *res;
4053 int n_ports = 0, irq = 0;
4054 int rc;
4055 int port;
4056
4057 ata_print_version_once(&pdev->dev, DRV_VERSION);
4058
4059 /*
4060 * Simple resource validation ..
4061 */
4062 if (unlikely(pdev->num_resources != 2)) {
4063 dev_err(&pdev->dev, "invalid number of resources\n");
4064 return -EINVAL;
4065 }
4066
4067 /*
4068 * Get the register base first
4069 */
4070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4071 if (res == NULL)
4072 return -EINVAL;
4073
4074 /* allocate host */
4075 if (pdev->dev.of_node) {
4076 of_property_read_u32(pdev->dev.of_node, "nr-ports", &n_ports);
4077 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
4078 } else {
4079 mv_platform_data = dev_get_platdata(&pdev->dev);
4080 n_ports = mv_platform_data->n_ports;
4081 irq = platform_get_irq(pdev, 0);
4082 }
4083
4084 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4085 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4086
4087 if (!host || !hpriv)
4088 return -ENOMEM;
4089 hpriv->port_clks = devm_kzalloc(&pdev->dev,
4090 sizeof(struct clk *) * n_ports,
4091 GFP_KERNEL);
4092 if (!hpriv->port_clks)
4093 return -ENOMEM;
4094 host->private_data = hpriv;
4095 hpriv->n_ports = n_ports;
4096 hpriv->board_idx = chip_soc;
4097
4098 host->iomap = NULL;
4099 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4100 resource_size(res));
4101 hpriv->base -= SATAHC0_REG_BASE;
4102
4103 hpriv->clk = clk_get(&pdev->dev, NULL);
4104 if (IS_ERR(hpriv->clk))
4105 dev_notice(&pdev->dev, "cannot get optional clkdev\n");
4106 else
4107 clk_prepare_enable(hpriv->clk);
4108
4109 for (port = 0; port < n_ports; port++) {
4110 char port_number[16];
4111 sprintf(port_number, "%d", port);
4112 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4113 if (!IS_ERR(hpriv->port_clks[port]))
4114 clk_prepare_enable(hpriv->port_clks[port]);
4115 }
4116
4117 /*
4118 * (Re-)program MBUS remapping windows if we are asked to.
4119 */
4120 dram = mv_mbus_dram_info();
4121 if (dram)
4122 mv_conf_mbus_windows(hpriv, dram);
4123
4124 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4125 if (rc)
4126 goto err;
4127
4128 /*
4129 * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
4130 * updated in the LP_PHY_CTL register.
4131 */
4132 if (pdev->dev.of_node &&
4133 of_device_is_compatible(pdev->dev.of_node,
4134 "marvell,armada-370-sata"))
4135 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
4136
4137 /* initialize adapter */
4138 rc = mv_init_host(host);
4139 if (rc)
4140 goto err;
4141
4142 dev_info(&pdev->dev, "slots %u ports %d\n",
4143 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
4144
4145 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
4146 if (!rc)
4147 return 0;
4148
4149 err:
4150 if (!IS_ERR(hpriv->clk)) {
4151 clk_disable_unprepare(hpriv->clk);
4152 clk_put(hpriv->clk);
4153 }
4154 for (port = 0; port < n_ports; port++) {
4155 if (!IS_ERR(hpriv->port_clks[port])) {
4156 clk_disable_unprepare(hpriv->port_clks[port]);
4157 clk_put(hpriv->port_clks[port]);
4158 }
4159 }
4160
4161 return rc;
4162 }
4163
4164 /*
4165 *
4166 * mv_platform_remove - unplug a platform interface
4167 * @pdev: platform device
4168 *
4169 * A platform bus SATA device has been unplugged. Perform the needed
4170 * cleanup. Also called on module unload for any active devices.
4171 */
4172 static int mv_platform_remove(struct platform_device *pdev)
4173 {
4174 struct ata_host *host = platform_get_drvdata(pdev);
4175 struct mv_host_priv *hpriv = host->private_data;
4176 int port;
4177 ata_host_detach(host);
4178
4179 if (!IS_ERR(hpriv->clk)) {
4180 clk_disable_unprepare(hpriv->clk);
4181 clk_put(hpriv->clk);
4182 }
4183 for (port = 0; port < host->n_ports; port++) {
4184 if (!IS_ERR(hpriv->port_clks[port])) {
4185 clk_disable_unprepare(hpriv->port_clks[port]);
4186 clk_put(hpriv->port_clks[port]);
4187 }
4188 }
4189 return 0;
4190 }
4191
4192 #ifdef CONFIG_PM
4193 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4194 {
4195 struct ata_host *host = platform_get_drvdata(pdev);
4196 if (host)
4197 return ata_host_suspend(host, state);
4198 else
4199 return 0;
4200 }
4201
4202 static int mv_platform_resume(struct platform_device *pdev)
4203 {
4204 struct ata_host *host = platform_get_drvdata(pdev);
4205 const struct mbus_dram_target_info *dram;
4206 int ret;
4207
4208 if (host) {
4209 struct mv_host_priv *hpriv = host->private_data;
4210
4211 /*
4212 * (Re-)program MBUS remapping windows if we are asked to.
4213 */
4214 dram = mv_mbus_dram_info();
4215 if (dram)
4216 mv_conf_mbus_windows(hpriv, dram);
4217
4218 /* initialize adapter */
4219 ret = mv_init_host(host);
4220 if (ret) {
4221 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4222 return ret;
4223 }
4224 ata_host_resume(host);
4225 }
4226
4227 return 0;
4228 }
4229 #else
4230 #define mv_platform_suspend NULL
4231 #define mv_platform_resume NULL
4232 #endif
4233
4234 #ifdef CONFIG_OF
4235 static struct of_device_id mv_sata_dt_ids[] = {
4236 { .compatible = "marvell,armada-370-sata", },
4237 { .compatible = "marvell,orion-sata", },
4238 {},
4239 };
4240 MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
4241 #endif
4242
4243 static struct platform_driver mv_platform_driver = {
4244 .probe = mv_platform_probe,
4245 .remove = mv_platform_remove,
4246 .suspend = mv_platform_suspend,
4247 .resume = mv_platform_resume,
4248 .driver = {
4249 .name = DRV_NAME,
4250 .owner = THIS_MODULE,
4251 .of_match_table = of_match_ptr(mv_sata_dt_ids),
4252 },
4253 };
4254
4255
4256 #ifdef CONFIG_PCI
4257 static int mv_pci_init_one(struct pci_dev *pdev,
4258 const struct pci_device_id *ent);
4259 #ifdef CONFIG_PM
4260 static int mv_pci_device_resume(struct pci_dev *pdev);
4261 #endif
4262
4263
4264 static struct pci_driver mv_pci_driver = {
4265 .name = DRV_NAME,
4266 .id_table = mv_pci_tbl,
4267 .probe = mv_pci_init_one,
4268 .remove = ata_pci_remove_one,
4269 #ifdef CONFIG_PM
4270 .suspend = ata_pci_device_suspend,
4271 .resume = mv_pci_device_resume,
4272 #endif
4273
4274 };
4275
4276 /* move to PCI layer or libata core? */
4277 static int pci_go_64(struct pci_dev *pdev)
4278 {
4279 int rc;
4280
4281 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4282 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4283 if (rc) {
4284 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4285 if (rc) {
4286 dev_err(&pdev->dev,
4287 "64-bit DMA enable failed\n");
4288 return rc;
4289 }
4290 }
4291 } else {
4292 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4293 if (rc) {
4294 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
4295 return rc;
4296 }
4297 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4298 if (rc) {
4299 dev_err(&pdev->dev,
4300 "32-bit consistent DMA enable failed\n");
4301 return rc;
4302 }
4303 }
4304
4305 return rc;
4306 }
4307
4308 /**
4309 * mv_print_info - Dump key info to kernel log for perusal.
4310 * @host: ATA host to print info about
4311 *
4312 * FIXME: complete this.
4313 *
4314 * LOCKING:
4315 * Inherited from caller.
4316 */
4317 static void mv_print_info(struct ata_host *host)
4318 {
4319 struct pci_dev *pdev = to_pci_dev(host->dev);
4320 struct mv_host_priv *hpriv = host->private_data;
4321 u8 scc;
4322 const char *scc_s, *gen;
4323
4324 /* Use this to determine the HW stepping of the chip so we know
4325 * what errata to workaround
4326 */
4327 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4328 if (scc == 0)
4329 scc_s = "SCSI";
4330 else if (scc == 0x01)
4331 scc_s = "RAID";
4332 else
4333 scc_s = "?";
4334
4335 if (IS_GEN_I(hpriv))
4336 gen = "I";
4337 else if (IS_GEN_II(hpriv))
4338 gen = "II";
4339 else if (IS_GEN_IIE(hpriv))
4340 gen = "IIE";
4341 else
4342 gen = "?";
4343
4344 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4345 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4346 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4347 }
4348
4349 /**
4350 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4351 * @pdev: PCI device found
4352 * @ent: PCI device ID entry for the matched host
4353 *
4354 * LOCKING:
4355 * Inherited from caller.
4356 */
4357 static int mv_pci_init_one(struct pci_dev *pdev,
4358 const struct pci_device_id *ent)
4359 {
4360 unsigned int board_idx = (unsigned int)ent->driver_data;
4361 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4362 struct ata_host *host;
4363 struct mv_host_priv *hpriv;
4364 int n_ports, port, rc;
4365
4366 ata_print_version_once(&pdev->dev, DRV_VERSION);
4367
4368 /* allocate host */
4369 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4370
4371 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4372 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4373 if (!host || !hpriv)
4374 return -ENOMEM;
4375 host->private_data = hpriv;
4376 hpriv->n_ports = n_ports;
4377 hpriv->board_idx = board_idx;
4378
4379 /* acquire resources */
4380 rc = pcim_enable_device(pdev);
4381 if (rc)
4382 return rc;
4383
4384 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4385 if (rc == -EBUSY)
4386 pcim_pin_device(pdev);
4387 if (rc)
4388 return rc;
4389 host->iomap = pcim_iomap_table(pdev);
4390 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4391
4392 rc = pci_go_64(pdev);
4393 if (rc)
4394 return rc;
4395
4396 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4397 if (rc)
4398 return rc;
4399
4400 for (port = 0; port < host->n_ports; port++) {
4401 struct ata_port *ap = host->ports[port];
4402 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4403 unsigned int offset = port_mmio - hpriv->base;
4404
4405 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4406 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4407 }
4408
4409 /* initialize adapter */
4410 rc = mv_init_host(host);
4411 if (rc)
4412 return rc;
4413
4414 /* Enable message-switched interrupts, if requested */
4415 if (msi && pci_enable_msi(pdev) == 0)
4416 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4417
4418 mv_dump_pci_cfg(pdev, 0x68);
4419 mv_print_info(host);
4420
4421 pci_set_master(pdev);
4422 pci_try_set_mwi(pdev);
4423 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4424 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4425 }
4426
4427 #ifdef CONFIG_PM
4428 static int mv_pci_device_resume(struct pci_dev *pdev)
4429 {
4430 struct ata_host *host = pci_get_drvdata(pdev);
4431 int rc;
4432
4433 rc = ata_pci_device_do_resume(pdev);
4434 if (rc)
4435 return rc;
4436
4437 /* initialize adapter */
4438 rc = mv_init_host(host);
4439 if (rc)
4440 return rc;
4441
4442 ata_host_resume(host);
4443
4444 return 0;
4445 }
4446 #endif
4447 #endif
4448
4449 static int __init mv_init(void)
4450 {
4451 int rc = -ENODEV;
4452 #ifdef CONFIG_PCI
4453 rc = pci_register_driver(&mv_pci_driver);
4454 if (rc < 0)
4455 return rc;
4456 #endif
4457 rc = platform_driver_register(&mv_platform_driver);
4458
4459 #ifdef CONFIG_PCI
4460 if (rc < 0)
4461 pci_unregister_driver(&mv_pci_driver);
4462 #endif
4463 return rc;
4464 }
4465
4466 static void __exit mv_exit(void)
4467 {
4468 #ifdef CONFIG_PCI
4469 pci_unregister_driver(&mv_pci_driver);
4470 #endif
4471 platform_driver_unregister(&mv_platform_driver);
4472 }
4473
4474 MODULE_AUTHOR("Brett Russ");
4475 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4476 MODULE_LICENSE("GPL");
4477 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4478 MODULE_VERSION(DRV_VERSION);
4479 MODULE_ALIAS("platform:" DRV_NAME);
4480
4481 module_init(mv_init);
4482 module_exit(mv_exit);
Linux with added FPC-III support