?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / char / agp / amd64-agp.c
blobd79d692d05b8f3c4a2d87e3422569ef084f365f8
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
17 #include <asm/e820.h>
18 #include <asm/amd_nb.h>
19 #include <asm/gart.h>
20 #include "agp.h"
21
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
29
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
34
35 static struct resource *aperture_resource;
36 static bool __initdata agp_try_unsupported = 1;
37 static int agp_bridges_found;
38
39 static void amd64_tlbflush(struct agp_memory *temp)
40 {
41 amd_flush_garts();
42 }
43
44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
45 {
46 int i, j, num_entries;
47 long long tmp;
48 int mask_type;
49 struct agp_bridge_data *bridge = mem->bridge;
50 u32 pte;
51
52 num_entries = agp_num_entries();
53
54 if (type != mem->type)
55 return -EINVAL;
56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
57 if (mask_type != 0)
58 return -EINVAL;
59
60
61 /* Make sure we can fit the range in the gatt table. */
62 /* FIXME: could wrap */
63 if (((unsigned long)pg_start + mem->page_count) > num_entries)
64 return -EINVAL;
65
66 j = pg_start;
67
68 /* gatt table should be empty. */
69 while (j < (pg_start + mem->page_count)) {
70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
71 return -EBUSY;
72 j++;
73 }
74
75 if (!mem->is_flushed) {
76 global_cache_flush();
77 mem->is_flushed = true;
78 }
79
80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
81 tmp = agp_bridge->driver->mask_memory(agp_bridge,
82 page_to_phys(mem->pages[i]),
83 mask_type);
84
85 BUG_ON(tmp & 0xffffff0000000ffcULL);
86 pte = (tmp & 0x000000ff00000000ULL) >> 28;
87 pte |=(tmp & 0x00000000fffff000ULL);
88 pte |= GPTE_VALID | GPTE_COHERENT;
89
90 writel(pte, agp_bridge->gatt_table+j);
91 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
92 }
93 amd64_tlbflush(mem);
94 return 0;
95 }
96
97 /*
98 * This hack alters the order element according
99 * to the size of a long. It sucks. I totally disown this, even
100 * though it does appear to work for the most part.
101 */
102 static struct aper_size_info_32 amd64_aperture_sizes[7] =
103 {
104 {32, 8192, 3+(sizeof(long)/8), 0 },
105 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
106 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
107 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
108 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
109 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
110 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
111 };
112
113
114 /*
115 * Get the current Aperture size from the x86-64.
116 * Note, that there may be multiple x86-64's, but we just return
117 * the value from the first one we find. The set_size functions
118 * keep the rest coherent anyway. Or at least should do.
119 */
120 static int amd64_fetch_size(void)
121 {
122 struct pci_dev *dev;
123 int i;
124 u32 temp;
125 struct aper_size_info_32 *values;
126
127 dev = node_to_amd_nb(0)->misc;
128 if (dev==NULL)
129 return 0;
130
131 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
132 temp = (temp & 0xe);
133 values = A_SIZE_32(amd64_aperture_sizes);
134
135 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
136 if (temp == values[i].size_value) {
137 agp_bridge->previous_size =
138 agp_bridge->current_size = (void *) (values + i);
139
140 agp_bridge->aperture_size_idx = i;
141 return values[i].size;
142 }
143 }
144 return 0;
145 }
146
147 /*
148 * In a multiprocessor x86-64 system, this function gets
149 * called once for each CPU.
150 */
151 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
152 {
153 u64 aperturebase;
154 u32 tmp;
155 u64 aper_base;
156
157 /* Address to map to */
158 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
159 aperturebase = tmp << 25;
160 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
161
162 enable_gart_translation(hammer, gatt_table);
163
164 return aper_base;
165 }
166
167
168 static const struct aper_size_info_32 amd_8151_sizes[7] =
169 {
170 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
171 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
172 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
173 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
174 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
175 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
176 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
177 };
178
179 static int amd_8151_configure(void)
180 {
181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
182 int i;
183
184 if (!amd_nb_has_feature(AMD_NB_GART))
185 return 0;
186
187 /* Configure AGP regs in each x86-64 host bridge. */
188 for (i = 0; i < amd_nb_num(); i++) {
189 agp_bridge->gart_bus_addr =
190 amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
191 }
192 amd_flush_garts();
193 return 0;
194 }
195
196
197 static void amd64_cleanup(void)
198 {
199 u32 tmp;
200 int i;
201
202 if (!amd_nb_has_feature(AMD_NB_GART))
203 return;
204
205 for (i = 0; i < amd_nb_num(); i++) {
206 struct pci_dev *dev = node_to_amd_nb(i)->misc;
207 /* disable gart translation */
208 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
209 tmp &= ~GARTEN;
210 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
211 }
212 }
213
214
215 static const struct agp_bridge_driver amd_8151_driver = {
216 .owner = THIS_MODULE,
217 .aperture_sizes = amd_8151_sizes,
218 .size_type = U32_APER_SIZE,
219 .num_aperture_sizes = 7,
220 .needs_scratch_page = true,
221 .configure = amd_8151_configure,
222 .fetch_size = amd64_fetch_size,
223 .cleanup = amd64_cleanup,
224 .tlb_flush = amd64_tlbflush,
225 .mask_memory = agp_generic_mask_memory,
226 .masks = NULL,
227 .agp_enable = agp_generic_enable,
228 .cache_flush = global_cache_flush,
229 .create_gatt_table = agp_generic_create_gatt_table,
230 .free_gatt_table = agp_generic_free_gatt_table,
231 .insert_memory = amd64_insert_memory,
232 .remove_memory = agp_generic_remove_memory,
233 .alloc_by_type = agp_generic_alloc_by_type,
234 .free_by_type = agp_generic_free_by_type,
235 .agp_alloc_page = agp_generic_alloc_page,
236 .agp_alloc_pages = agp_generic_alloc_pages,
237 .agp_destroy_page = agp_generic_destroy_page,
238 .agp_destroy_pages = agp_generic_destroy_pages,
239 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
240 };
241
242 /* Some basic sanity checks for the aperture. */
243 static int agp_aperture_valid(u64 aper, u32 size)
244 {
245 if (!aperture_valid(aper, size, 32*1024*1024))
246 return 0;
247
248 /* Request the Aperture. This catches cases when someone else
249 already put a mapping in there - happens with some very broken BIOS
250
251 Maybe better to use pci_assign_resource/pci_enable_device instead
252 trusting the bridges? */
253 if (!aperture_resource &&
254 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
255 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
256 return 0;
257 }
258 return 1;
259 }
260
261 /*
262 * W*s centric BIOS sometimes only set up the aperture in the AGP
263 * bridge, not the northbridge. On AMD64 this is handled early
264 * in aperture.c, but when IOMMU is not enabled or we run
265 * on a 32bit kernel this needs to be redone.
266 * Unfortunately it is impossible to fix the aperture here because it's too late
267 * to allocate that much memory. But at least error out cleanly instead of
268 * crashing.
269 */
270 static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
271 {
272 u32 aper_low, aper_hi;
273 u64 aper, nb_aper;
274 int order = 0;
275 u32 nb_order, nb_base;
276 u16 apsize;
277
278 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
279 nb_order = (nb_order >> 1) & 7;
280 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
281 nb_aper = nb_base << 25;
282
283 /* Northbridge seems to contain crap. Try the AGP bridge. */
284
285 pci_read_config_word(agp, cap+0x14, &apsize);
286 if (apsize == 0xffff) {
287 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
288 return 0;
289 return -1;
290 }
291
292 apsize &= 0xfff;
293 /* Some BIOS use weird encodings not in the AGPv3 table. */
294 if (apsize & 0xff)
295 apsize |= 0xf00;
296 order = 7 - hweight16(apsize);
297
298 pci_read_config_dword(agp, 0x10, &aper_low);
299 pci_read_config_dword(agp, 0x14, &aper_hi);
300 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
301
302 /*
303 * On some sick chips APSIZE is 0. This means it wants 4G
304 * so let double check that order, and lets trust the AMD NB settings
305 */
306 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
307 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
308 32 << order);
309 order = nb_order;
310 }
311
312 if (nb_order >= order) {
313 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
314 return 0;
315 }
316
317 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
318 aper, 32 << order);
319 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
320 return -1;
321
322 gart_set_size_and_enable(nb, order);
323 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
324
325 return 0;
326 }
327
328 static int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
329 {
330 int i;
331
332 if (amd_cache_northbridges() < 0)
333 return -ENODEV;
334
335 if (!amd_nb_has_feature(AMD_NB_GART))
336 return -ENODEV;
337
338 i = 0;
339 for (i = 0; i < amd_nb_num(); i++) {
340 struct pci_dev *dev = node_to_amd_nb(i)->misc;
341 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
342 dev_err(&dev->dev, "no usable aperture found\n");
343 #ifdef __x86_64__
344 /* should port this to i386 */
345 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
346 #endif
347 return -1;
348 }
349 }
350 return 0;
351 }
352
353 /* Handle AMD 8151 quirks */
354 static void amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
355 {
356 char *revstring;
357
358 switch (pdev->revision) {
359 case 0x01: revstring="A0"; break;
360 case 0x02: revstring="A1"; break;
361 case 0x11: revstring="B0"; break;
362 case 0x12: revstring="B1"; break;
363 case 0x13: revstring="B2"; break;
364 case 0x14: revstring="B3"; break;
365 default: revstring="??"; break;
366 }
367
368 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
369
370 /*
371 * Work around errata.
372 * Chips before B2 stepping incorrectly reporting v3.5
373 */
374 if (pdev->revision < 0x13) {
375 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
376 bridge->major_version = 3;
377 bridge->minor_version = 0;
378 }
379 }
380
381
382 static const struct aper_size_info_32 uli_sizes[7] =
383 {
384 {256, 65536, 6, 10},
385 {128, 32768, 5, 9},
386 {64, 16384, 4, 8},
387 {32, 8192, 3, 7},
388 {16, 4096, 2, 6},
389 {8, 2048, 1, 4},
390 {4, 1024, 0, 3}
391 };
392 static int uli_agp_init(struct pci_dev *pdev)
393 {
394 u32 httfea,baseaddr,enuscr;
395 struct pci_dev *dev1;
396 int i, ret;
397 unsigned size = amd64_fetch_size();
398
399 dev_info(&pdev->dev, "setting up ULi AGP\n");
400 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
401 if (dev1 == NULL) {
402 dev_info(&pdev->dev, "can't find ULi secondary device\n");
403 return -ENODEV;
404 }
405
406 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
407 if (uli_sizes[i].size == size)
408 break;
409
410 if (i == ARRAY_SIZE(uli_sizes)) {
411 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
412 ret = -ENODEV;
413 goto put;
414 }
415
416 /* shadow x86-64 registers into ULi registers */
417 pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
418 &httfea);
419
420 /* if x86-64 aperture base is beyond 4G, exit here */
421 if ((httfea & 0x7fff) >> (32 - 25)) {
422 ret = -ENODEV;
423 goto put;
424 }
425
426 httfea = (httfea& 0x7fff) << 25;
427
428 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
429 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
430 baseaddr|= httfea;
431 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
432
433 enuscr= httfea+ (size * 1024 * 1024) - 1;
434 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
435 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
436 ret = 0;
437 put:
438 pci_dev_put(dev1);
439 return ret;
440 }
441
442
443 static const struct aper_size_info_32 nforce3_sizes[5] =
444 {
445 {512, 131072, 7, 0x00000000 },
446 {256, 65536, 6, 0x00000008 },
447 {128, 32768, 5, 0x0000000C },
448 {64, 16384, 4, 0x0000000E },
449 {32, 8192, 3, 0x0000000F }
450 };
451
452 /* Handle shadow device of the Nvidia NForce3 */
453 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
454 static int nforce3_agp_init(struct pci_dev *pdev)
455 {
456 u32 tmp, apbase, apbar, aplimit;
457 struct pci_dev *dev1;
458 int i, ret;
459 unsigned size = amd64_fetch_size();
460
461 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
462
463 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
464 if (dev1 == NULL) {
465 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
466 return -ENODEV;
467 }
468
469 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
470 if (nforce3_sizes[i].size == size)
471 break;
472
473 if (i == ARRAY_SIZE(nforce3_sizes)) {
474 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
475 ret = -ENODEV;
476 goto put;
477 }
478
479 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
480 tmp &= ~(0xf);
481 tmp |= nforce3_sizes[i].size_value;
482 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
483
484 /* shadow x86-64 registers into NVIDIA registers */
485 pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
486 &apbase);
487
488 /* if x86-64 aperture base is beyond 4G, exit here */
489 if ( (apbase & 0x7fff) >> (32 - 25) ) {
490 dev_info(&pdev->dev, "aperture base > 4G\n");
491 ret = -ENODEV;
492 goto put;
493 }
494
495 apbase = (apbase & 0x7fff) << 25;
496
497 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
498 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
499 apbar |= apbase;
500 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
501
502 aplimit = apbase + (size * 1024 * 1024) - 1;
503 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
504 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
505 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
506 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
507
508 ret = 0;
509 put:
510 pci_dev_put(dev1);
511
512 return ret;
513 }
514
515 static int agp_amd64_probe(struct pci_dev *pdev,
516 const struct pci_device_id *ent)
517 {
518 struct agp_bridge_data *bridge;
519 u8 cap_ptr;
520 int err;
521
522 /* The Highlander principle */
523 if (agp_bridges_found)
524 return -ENODEV;
525
526 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
527 if (!cap_ptr)
528 return -ENODEV;
529
530 /* Could check for AGPv3 here */
531
532 bridge = agp_alloc_bridge();
533 if (!bridge)
534 return -ENOMEM;
535
536 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
537 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
538 amd8151_init(pdev, bridge);
539 } else {
540 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
541 pdev->vendor, pdev->device);
542 }
543
544 bridge->driver = &amd_8151_driver;
545 bridge->dev = pdev;
546 bridge->capndx = cap_ptr;
547
548 /* Fill in the mode register */
549 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
550
551 if (cache_nbs(pdev, cap_ptr) == -1) {
552 agp_put_bridge(bridge);
553 return -ENODEV;
554 }
555
556 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
557 int ret = nforce3_agp_init(pdev);
558 if (ret) {
559 agp_put_bridge(bridge);
560 return ret;
561 }
562 }
563
564 if (pdev->vendor == PCI_VENDOR_ID_AL) {
565 int ret = uli_agp_init(pdev);
566 if (ret) {
567 agp_put_bridge(bridge);
568 return ret;
569 }
570 }
571
572 pci_set_drvdata(pdev, bridge);
573 err = agp_add_bridge(bridge);
574 if (err < 0)
575 return err;
576
577 agp_bridges_found++;
578 return 0;
579 }
580
581 static void agp_amd64_remove(struct pci_dev *pdev)
582 {
583 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
584
585 release_mem_region(virt_to_phys(bridge->gatt_table_real),
586 amd64_aperture_sizes[bridge->aperture_size_idx].size);
587 agp_remove_bridge(bridge);
588 agp_put_bridge(bridge);
589
590 agp_bridges_found--;
591 }
592
593 #ifdef CONFIG_PM
594
595 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
596 {
597 pci_save_state(pdev);
598 pci_set_power_state(pdev, pci_choose_state(pdev, state));
599
600 return 0;
601 }
602
603 static int agp_amd64_resume(struct pci_dev *pdev)
604 {
605 pci_set_power_state(pdev, PCI_D0);
606 pci_restore_state(pdev);
607
608 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
609 nforce3_agp_init(pdev);
610
611 return amd_8151_configure();
612 }
613
614 #endif /* CONFIG_PM */
615
616 static struct pci_device_id agp_amd64_pci_table[] = {
617 {
618 .class = (PCI_CLASS_BRIDGE_HOST << 8),
619 .class_mask = ~0,
620 .vendor = PCI_VENDOR_ID_AMD,
621 .device = PCI_DEVICE_ID_AMD_8151_0,
622 .subvendor = PCI_ANY_ID,
623 .subdevice = PCI_ANY_ID,
624 },
625 /* ULi M1689 */
626 {
627 .class = (PCI_CLASS_BRIDGE_HOST << 8),
628 .class_mask = ~0,
629 .vendor = PCI_VENDOR_ID_AL,
630 .device = PCI_DEVICE_ID_AL_M1689,
631 .subvendor = PCI_ANY_ID,
632 .subdevice = PCI_ANY_ID,
633 },
634 /* VIA K8T800Pro */
635 {
636 .class = (PCI_CLASS_BRIDGE_HOST << 8),
637 .class_mask = ~0,
638 .vendor = PCI_VENDOR_ID_VIA,
639 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
640 .subvendor = PCI_ANY_ID,
641 .subdevice = PCI_ANY_ID,
642 },
643 /* VIA K8T800 */
644 {
645 .class = (PCI_CLASS_BRIDGE_HOST << 8),
646 .class_mask = ~0,
647 .vendor = PCI_VENDOR_ID_VIA,
648 .device = PCI_DEVICE_ID_VIA_8385_0,
649 .subvendor = PCI_ANY_ID,
650 .subdevice = PCI_ANY_ID,
651 },
652 /* VIA K8M800 / K8N800 */
653 {
654 .class = (PCI_CLASS_BRIDGE_HOST << 8),
655 .class_mask = ~0,
656 .vendor = PCI_VENDOR_ID_VIA,
657 .device = PCI_DEVICE_ID_VIA_8380_0,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 },
661 /* VIA K8M890 / K8N890 */
662 {
663 .class = (PCI_CLASS_BRIDGE_HOST << 8),
664 .class_mask = ~0,
665 .vendor = PCI_VENDOR_ID_VIA,
666 .device = PCI_DEVICE_ID_VIA_VT3336,
667 .subvendor = PCI_ANY_ID,
668 .subdevice = PCI_ANY_ID,
669 },
670 /* VIA K8T890 */
671 {
672 .class = (PCI_CLASS_BRIDGE_HOST << 8),
673 .class_mask = ~0,
674 .vendor = PCI_VENDOR_ID_VIA,
675 .device = PCI_DEVICE_ID_VIA_3238_0,
676 .subvendor = PCI_ANY_ID,
677 .subdevice = PCI_ANY_ID,
678 },
679 /* VIA K8T800/K8M800/K8N800 */
680 {
681 .class = (PCI_CLASS_BRIDGE_HOST << 8),
682 .class_mask = ~0,
683 .vendor = PCI_VENDOR_ID_VIA,
684 .device = PCI_DEVICE_ID_VIA_838X_1,
685 .subvendor = PCI_ANY_ID,
686 .subdevice = PCI_ANY_ID,
687 },
688 /* NForce3 */
689 {
690 .class = (PCI_CLASS_BRIDGE_HOST << 8),
691 .class_mask = ~0,
692 .vendor = PCI_VENDOR_ID_NVIDIA,
693 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
694 .subvendor = PCI_ANY_ID,
695 .subdevice = PCI_ANY_ID,
696 },
697 {
698 .class = (PCI_CLASS_BRIDGE_HOST << 8),
699 .class_mask = ~0,
700 .vendor = PCI_VENDOR_ID_NVIDIA,
701 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
702 .subvendor = PCI_ANY_ID,
703 .subdevice = PCI_ANY_ID,
704 },
705 /* SIS 755 */
706 {
707 .class = (PCI_CLASS_BRIDGE_HOST << 8),
708 .class_mask = ~0,
709 .vendor = PCI_VENDOR_ID_SI,
710 .device = PCI_DEVICE_ID_SI_755,
711 .subvendor = PCI_ANY_ID,
712 .subdevice = PCI_ANY_ID,
713 },
714 /* SIS 760 */
715 {
716 .class = (PCI_CLASS_BRIDGE_HOST << 8),
717 .class_mask = ~0,
718 .vendor = PCI_VENDOR_ID_SI,
719 .device = PCI_DEVICE_ID_SI_760,
720 .subvendor = PCI_ANY_ID,
721 .subdevice = PCI_ANY_ID,
722 },
723 /* ALI/ULI M1695 */
724 {
725 .class = (PCI_CLASS_BRIDGE_HOST << 8),
726 .class_mask = ~0,
727 .vendor = PCI_VENDOR_ID_AL,
728 .device = 0x1695,
729 .subvendor = PCI_ANY_ID,
730 .subdevice = PCI_ANY_ID,
731 },
732
733 { }
734 };
735
736 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
737
738 static DEFINE_PCI_DEVICE_TABLE(agp_amd64_pci_promisc_table) = {
739 { PCI_DEVICE_CLASS(0, 0) },
740 { }
741 };
742
743 static struct pci_driver agp_amd64_pci_driver = {
744 .name = "agpgart-amd64",
745 .id_table = agp_amd64_pci_table,
746 .probe = agp_amd64_probe,
747 .remove = agp_amd64_remove,
748 #ifdef CONFIG_PM
749 .suspend = agp_amd64_suspend,
750 .resume = agp_amd64_resume,
751 #endif
752 };
753
754
755 /* Not static due to IOMMU code calling it early. */
756 int __init agp_amd64_init(void)
757 {
758 int err = 0;
759
760 if (agp_off)
761 return -EINVAL;
762
763 err = pci_register_driver(&agp_amd64_pci_driver);
764 if (err < 0)
765 return err;
766
767 if (agp_bridges_found == 0) {
768 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
769 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
770 #ifdef MODULE
771 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
772 #else
773 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
774 #endif
775 pci_unregister_driver(&agp_amd64_pci_driver);
776 return -ENODEV;
777 }
778
779 /* First check that we have at least one AMD64 NB */
780 if (!pci_dev_present(amd_nb_misc_ids)) {
781 pci_unregister_driver(&agp_amd64_pci_driver);
782 return -ENODEV;
783 }
784
785 /* Look for any AGP bridge */
786 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
787 err = driver_attach(&agp_amd64_pci_driver.driver);
788 if (err == 0 && agp_bridges_found == 0) {
789 pci_unregister_driver(&agp_amd64_pci_driver);
790 err = -ENODEV;
791 }
792 }
793 return err;
794 }
795
796 static int __init agp_amd64_mod_init(void)
797 {
798 #ifndef MODULE
799 if (gart_iommu_aperture)
800 return agp_bridges_found ? 0 : -ENODEV;
801 #endif
802 return agp_amd64_init();
803 }
804
805 static void __exit agp_amd64_cleanup(void)
806 {
807 #ifndef MODULE
808 if (gart_iommu_aperture)
809 return;
810 #endif
811 if (aperture_resource)
812 release_resource(aperture_resource);
813 pci_unregister_driver(&agp_amd64_pci_driver);
814 }
815
816 module_init(agp_amd64_mod_init);
817 module_exit(agp_amd64_cleanup);
818
819 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
820 module_param(agp_try_unsupported, bool, 0);
821 MODULE_LICENSE("GPL");
Linux with added FPC-III support