2 * Copyright 2011-2012 Calxeda, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/err.h>
20 #include <linux/clk-provider.h>
24 extern void __iomem
*sregs_base
;
26 #define HB_PLL_LOCK_500 0x20000000
27 #define HB_PLL_LOCK 0x10000000
28 #define HB_PLL_DIVF_SHIFT 20
29 #define HB_PLL_DIVF_MASK 0x0ff00000
30 #define HB_PLL_DIVQ_SHIFT 16
31 #define HB_PLL_DIVQ_MASK 0x00070000
32 #define HB_PLL_DIVR_SHIFT 8
33 #define HB_PLL_DIVR_MASK 0x00001f00
34 #define HB_PLL_RANGE_SHIFT 4
35 #define HB_PLL_RANGE_MASK 0x00000070
36 #define HB_PLL_BYPASS 0x00000008
37 #define HB_PLL_RESET 0x00000004
38 #define HB_PLL_EXT_BYPASS 0x00000002
39 #define HB_PLL_EXT_ENA 0x00000001
41 #define HB_PLL_VCO_MIN_FREQ 2133000000
42 #define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
43 #define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
45 #define HB_A9_BCLK_DIV_MASK 0x00000006
46 #define HB_A9_BCLK_DIV_SHIFT 1
47 #define HB_A9_PCLK_DIV 0x00000001
54 #define to_hb_clk(p) container_of(p, struct hb_clk, hw)
56 static int clk_pll_prepare(struct clk_hw
*hwclk
)
58 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
61 reg
= readl(hbclk
->reg
);
63 writel(reg
, hbclk
->reg
);
65 while ((readl(hbclk
->reg
) & HB_PLL_LOCK
) == 0)
67 while ((readl(hbclk
->reg
) & HB_PLL_LOCK_500
) == 0)
73 static void clk_pll_unprepare(struct clk_hw
*hwclk
)
75 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
78 reg
= readl(hbclk
->reg
);
80 writel(reg
, hbclk
->reg
);
83 static int clk_pll_enable(struct clk_hw
*hwclk
)
85 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
88 reg
= readl(hbclk
->reg
);
89 reg
|= HB_PLL_EXT_ENA
;
90 writel(reg
, hbclk
->reg
);
95 static void clk_pll_disable(struct clk_hw
*hwclk
)
97 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
100 reg
= readl(hbclk
->reg
);
101 reg
&= ~HB_PLL_EXT_ENA
;
102 writel(reg
, hbclk
->reg
);
105 static unsigned long clk_pll_recalc_rate(struct clk_hw
*hwclk
,
106 unsigned long parent_rate
)
108 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
109 unsigned long divf
, divq
, vco_freq
, reg
;
111 reg
= readl(hbclk
->reg
);
112 if (reg
& HB_PLL_EXT_BYPASS
)
115 divf
= (reg
& HB_PLL_DIVF_MASK
) >> HB_PLL_DIVF_SHIFT
;
116 divq
= (reg
& HB_PLL_DIVQ_MASK
) >> HB_PLL_DIVQ_SHIFT
;
117 vco_freq
= parent_rate
* (divf
+ 1);
119 return vco_freq
/ (1 << divq
);
122 static void clk_pll_calc(unsigned long rate
, unsigned long ref_freq
,
123 u32
*pdivq
, u32
*pdivf
)
126 unsigned long vco_freq
;
128 if (rate
< HB_PLL_MIN_FREQ
)
129 rate
= HB_PLL_MIN_FREQ
;
130 if (rate
> HB_PLL_MAX_FREQ
)
131 rate
= HB_PLL_MAX_FREQ
;
133 for (divq
= 1; divq
<= 6; divq
++) {
134 if ((rate
* (1 << divq
)) >= HB_PLL_VCO_MIN_FREQ
)
138 vco_freq
= rate
* (1 << divq
);
139 divf
= (vco_freq
+ (ref_freq
/ 2)) / ref_freq
;
146 static long clk_pll_round_rate(struct clk_hw
*hwclk
, unsigned long rate
,
147 unsigned long *parent_rate
)
150 unsigned long ref_freq
= *parent_rate
;
152 clk_pll_calc(rate
, ref_freq
, &divq
, &divf
);
154 return (ref_freq
* (divf
+ 1)) / (1 << divq
);
157 static int clk_pll_set_rate(struct clk_hw
*hwclk
, unsigned long rate
,
158 unsigned long parent_rate
)
160 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
164 clk_pll_calc(rate
, parent_rate
, &divq
, &divf
);
166 reg
= readl(hbclk
->reg
);
167 if (divf
!= ((reg
& HB_PLL_DIVF_MASK
) >> HB_PLL_DIVF_SHIFT
)) {
168 /* Need to re-lock PLL, so put it into bypass mode */
169 reg
|= HB_PLL_EXT_BYPASS
;
170 writel(reg
| HB_PLL_EXT_BYPASS
, hbclk
->reg
);
172 writel(reg
| HB_PLL_RESET
, hbclk
->reg
);
173 reg
&= ~(HB_PLL_DIVF_MASK
| HB_PLL_DIVQ_MASK
);
174 reg
|= (divf
<< HB_PLL_DIVF_SHIFT
) | (divq
<< HB_PLL_DIVQ_SHIFT
);
175 writel(reg
| HB_PLL_RESET
, hbclk
->reg
);
176 writel(reg
, hbclk
->reg
);
178 while ((readl(hbclk
->reg
) & HB_PLL_LOCK
) == 0)
180 while ((readl(hbclk
->reg
) & HB_PLL_LOCK_500
) == 0)
182 reg
|= HB_PLL_EXT_ENA
;
183 reg
&= ~HB_PLL_EXT_BYPASS
;
185 writel(reg
| HB_PLL_EXT_BYPASS
, hbclk
->reg
);
186 reg
&= ~HB_PLL_DIVQ_MASK
;
187 reg
|= divq
<< HB_PLL_DIVQ_SHIFT
;
188 writel(reg
| HB_PLL_EXT_BYPASS
, hbclk
->reg
);
190 writel(reg
, hbclk
->reg
);
195 static const struct clk_ops clk_pll_ops
= {
196 .prepare
= clk_pll_prepare
,
197 .unprepare
= clk_pll_unprepare
,
198 .enable
= clk_pll_enable
,
199 .disable
= clk_pll_disable
,
200 .recalc_rate
= clk_pll_recalc_rate
,
201 .round_rate
= clk_pll_round_rate
,
202 .set_rate
= clk_pll_set_rate
,
205 static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw
*hwclk
,
206 unsigned long parent_rate
)
208 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
209 u32 div
= (readl(hbclk
->reg
) & HB_A9_PCLK_DIV
) ? 8 : 4;
210 return parent_rate
/ div
;
213 static const struct clk_ops a9periphclk_ops
= {
214 .recalc_rate
= clk_cpu_periphclk_recalc_rate
,
217 static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw
*hwclk
,
218 unsigned long parent_rate
)
220 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
221 u32 div
= (readl(hbclk
->reg
) & HB_A9_BCLK_DIV_MASK
) >> HB_A9_BCLK_DIV_SHIFT
;
223 return parent_rate
/ (div
+ 2);
226 static const struct clk_ops a9bclk_ops
= {
227 .recalc_rate
= clk_cpu_a9bclk_recalc_rate
,
230 static unsigned long clk_periclk_recalc_rate(struct clk_hw
*hwclk
,
231 unsigned long parent_rate
)
233 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
236 div
= readl(hbclk
->reg
) & 0x1f;
240 return parent_rate
/ div
;
243 static long clk_periclk_round_rate(struct clk_hw
*hwclk
, unsigned long rate
,
244 unsigned long *parent_rate
)
248 div
= *parent_rate
/ rate
;
252 return *parent_rate
/ div
;
255 static int clk_periclk_set_rate(struct clk_hw
*hwclk
, unsigned long rate
,
256 unsigned long parent_rate
)
258 struct hb_clk
*hbclk
= to_hb_clk(hwclk
);
261 div
= parent_rate
/ rate
;
265 writel(div
>> 1, hbclk
->reg
);
269 static const struct clk_ops periclk_ops
= {
270 .recalc_rate
= clk_periclk_recalc_rate
,
271 .round_rate
= clk_periclk_round_rate
,
272 .set_rate
= clk_periclk_set_rate
,
275 static __init
struct clk
*hb_clk_init(struct device_node
*node
, const struct clk_ops
*ops
)
279 struct hb_clk
*hb_clk
;
280 const char *clk_name
= node
->name
;
281 const char *parent_name
;
282 struct clk_init_data init
;
285 rc
= of_property_read_u32(node
, "reg", ®
);
289 hb_clk
= kzalloc(sizeof(*hb_clk
), GFP_KERNEL
);
290 if (WARN_ON(!hb_clk
))
293 hb_clk
->reg
= sregs_base
+ reg
;
295 of_property_read_string(node
, "clock-output-names", &clk_name
);
297 init
.name
= clk_name
;
300 parent_name
= of_clk_get_parent_name(node
, 0);
301 init
.parent_names
= &parent_name
;
302 init
.num_parents
= 1;
304 hb_clk
->hw
.init
= &init
;
306 clk
= clk_register(NULL
, &hb_clk
->hw
);
307 if (WARN_ON(IS_ERR(clk
))) {
311 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
315 static void __init
hb_pll_init(struct device_node
*node
)
317 hb_clk_init(node
, &clk_pll_ops
);
319 CLK_OF_DECLARE(hb_pll
, "calxeda,hb-pll-clock", hb_pll_init
);
321 static void __init
hb_a9periph_init(struct device_node
*node
)
323 hb_clk_init(node
, &a9periphclk_ops
);
325 CLK_OF_DECLARE(hb_a9periph
, "calxeda,hb-a9periph-clock", hb_a9periph_init
);
327 static void __init
hb_a9bus_init(struct device_node
*node
)
329 struct clk
*clk
= hb_clk_init(node
, &a9bclk_ops
);
330 clk_prepare_enable(clk
);
332 CLK_OF_DECLARE(hb_a9bus
, "calxeda,hb-a9bus-clock", hb_a9bus_init
);
334 static void __init
hb_emmc_init(struct device_node
*node
)
336 hb_clk_init(node
, &periclk_ops
);
338 CLK_OF_DECLARE(hb_emmc
, "calxeda,hb-emmc-clock", hb_emmc_init
);