2 * Clock tree for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/syscore_ops.h>
18 #define SIRFSOC_CLKC_CLK_EN0 0x0000
19 #define SIRFSOC_CLKC_CLK_EN1 0x0004
20 #define SIRFSOC_CLKC_REF_CFG 0x0014
21 #define SIRFSOC_CLKC_CPU_CFG 0x0018
22 #define SIRFSOC_CLKC_MEM_CFG 0x001c
23 #define SIRFSOC_CLKC_SYS_CFG 0x0020
24 #define SIRFSOC_CLKC_IO_CFG 0x0024
25 #define SIRFSOC_CLKC_DSP_CFG 0x0028
26 #define SIRFSOC_CLKC_GFX_CFG 0x002c
27 #define SIRFSOC_CLKC_MM_CFG 0x0030
28 #define SIRFSOC_CLKC_LCD_CFG 0x0034
29 #define SIRFSOC_CLKC_MMC_CFG 0x0038
30 #define SIRFSOC_CLKC_PLL1_CFG0 0x0040
31 #define SIRFSOC_CLKC_PLL2_CFG0 0x0044
32 #define SIRFSOC_CLKC_PLL3_CFG0 0x0048
33 #define SIRFSOC_CLKC_PLL1_CFG1 0x004c
34 #define SIRFSOC_CLKC_PLL2_CFG1 0x0050
35 #define SIRFSOC_CLKC_PLL3_CFG1 0x0054
36 #define SIRFSOC_CLKC_PLL1_CFG2 0x0058
37 #define SIRFSOC_CLKC_PLL2_CFG2 0x005c
38 #define SIRFSOC_CLKC_PLL3_CFG2 0x0060
39 #define SIRFSOC_USBPHY_PLL_CTRL 0x0008
40 #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
41 #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
42 #define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
44 static void *sirfsoc_clk_vbase
, *sirfsoc_rsc_vbase
;
47 #define MHZ (KHZ * KHZ)
50 * SiRFprimaII clock controller
51 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
52 * - 3 standard configurable plls: pll1, pll2 & pll3
53 * - 2 exclusive plls: usb phy pll and sata phy pll
54 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
56 * Each clock domain can select its own clock source from five clock sources,
57 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
58 * clock of the group clock.
59 * - dsp domain: gps, mf
60 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
61 * - sys domain: security
66 unsigned short regofs
; /* register offset */
69 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
73 signed char enable_bit
; /* enable bit: 0 ~ 63 */
74 unsigned short regofs
; /* register offset */
77 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
81 signed char enable_bit
; /* enable bit: 0 ~ 63 */
84 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
86 static int std_clk_is_enabled(struct clk_hw
*hw
);
87 static int std_clk_enable(struct clk_hw
*hw
);
88 static void std_clk_disable(struct clk_hw
*hw
);
90 static inline unsigned long clkc_readl(unsigned reg
)
92 return readl(sirfsoc_clk_vbase
+ reg
);
95 static inline void clkc_writel(u32 val
, unsigned reg
)
97 writel(val
, sirfsoc_clk_vbase
+ reg
);
104 static unsigned long pll_clk_recalc_rate(struct clk_hw
*hw
,
105 unsigned long parent_rate
)
107 unsigned long fin
= parent_rate
;
108 struct clk_pll
*clk
= to_pllclk(hw
);
109 u32 regcfg2
= clk
->regofs
+ SIRFSOC_CLKC_PLL1_CFG2
-
110 SIRFSOC_CLKC_PLL1_CFG0
;
112 if (clkc_readl(regcfg2
) & BIT(2)) {
113 /* pll bypass mode */
116 /* fout = fin * nf / nr / od */
117 u32 cfg0
= clkc_readl(clk
->regofs
);
118 u32 nf
= (cfg0
& (BIT(13) - 1)) + 1;
119 u32 nr
= ((cfg0
>> 13) & (BIT(6) - 1)) + 1;
120 u32 od
= ((cfg0
>> 19) & (BIT(4) - 1)) + 1;
122 return fin
/ MHZ
* nf
/ nr
/ od
* MHZ
;
126 static long pll_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
127 unsigned long *parent_rate
)
129 unsigned long fin
, nf
, nr
, od
;
132 * fout = fin * nf / (nr * od);
133 * set od = 1, nr = fin/MHz, so fout = nf * MHz
135 rate
= rate
- rate
% MHZ
;
150 return fin
* nf
/ (nr
* od
);
153 static int pll_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
154 unsigned long parent_rate
)
156 struct clk_pll
*clk
= to_pllclk(hw
);
157 unsigned long fin
, nf
, nr
, od
, reg
;
160 * fout = fin * nf / (nr * od);
161 * set od = 1, nr = fin/MHz, so fout = nf * MHz
165 if (unlikely((rate
% MHZ
) || nf
> BIT(13) || nf
< 1))
172 BUG_ON((fin
% MHZ
) || nr
> BIT(6));
176 reg
= (nf
- 1) | ((nr
- 1) << 13) | ((od
- 1) << 19);
177 clkc_writel(reg
, clk
->regofs
);
179 reg
= clk
->regofs
+ SIRFSOC_CLKC_PLL1_CFG1
- SIRFSOC_CLKC_PLL1_CFG0
;
180 clkc_writel((nf
>> 1) - 1, reg
);
182 reg
= clk
->regofs
+ SIRFSOC_CLKC_PLL1_CFG2
- SIRFSOC_CLKC_PLL1_CFG0
;
183 while (!(clkc_readl(reg
) & BIT(6)))
189 static struct clk_ops std_pll_ops
= {
190 .recalc_rate
= pll_clk_recalc_rate
,
191 .round_rate
= pll_clk_round_rate
,
192 .set_rate
= pll_clk_set_rate
,
195 static const char *pll_clk_parents
[] = {
199 static struct clk_init_data clk_pll1_init
= {
202 .parent_names
= pll_clk_parents
,
203 .num_parents
= ARRAY_SIZE(pll_clk_parents
),
206 static struct clk_init_data clk_pll2_init
= {
209 .parent_names
= pll_clk_parents
,
210 .num_parents
= ARRAY_SIZE(pll_clk_parents
),
213 static struct clk_init_data clk_pll3_init
= {
216 .parent_names
= pll_clk_parents
,
217 .num_parents
= ARRAY_SIZE(pll_clk_parents
),
220 static struct clk_pll clk_pll1
= {
221 .regofs
= SIRFSOC_CLKC_PLL1_CFG0
,
223 .init
= &clk_pll1_init
,
227 static struct clk_pll clk_pll2
= {
228 .regofs
= SIRFSOC_CLKC_PLL2_CFG0
,
230 .init
= &clk_pll2_init
,
234 static struct clk_pll clk_pll3
= {
235 .regofs
= SIRFSOC_CLKC_PLL3_CFG0
,
237 .init
= &clk_pll3_init
,
242 * usb uses specified pll
245 static int usb_pll_clk_enable(struct clk_hw
*hw
)
247 u32 reg
= readl(sirfsoc_rsc_vbase
+ SIRFSOC_USBPHY_PLL_CTRL
);
248 reg
&= ~(SIRFSOC_USBPHY_PLL_POWERDOWN
| SIRFSOC_USBPHY_PLL_BYPASS
);
249 writel(reg
, sirfsoc_rsc_vbase
+ SIRFSOC_USBPHY_PLL_CTRL
);
250 while (!(readl(sirfsoc_rsc_vbase
+ SIRFSOC_USBPHY_PLL_CTRL
) &
251 SIRFSOC_USBPHY_PLL_LOCK
))
257 static void usb_pll_clk_disable(struct clk_hw
*clk
)
259 u32 reg
= readl(sirfsoc_rsc_vbase
+ SIRFSOC_USBPHY_PLL_CTRL
);
260 reg
|= (SIRFSOC_USBPHY_PLL_POWERDOWN
| SIRFSOC_USBPHY_PLL_BYPASS
);
261 writel(reg
, sirfsoc_rsc_vbase
+ SIRFSOC_USBPHY_PLL_CTRL
);
264 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
)
266 u32 reg
= readl(sirfsoc_rsc_vbase
+ SIRFSOC_USBPHY_PLL_CTRL
);
267 return (reg
& SIRFSOC_USBPHY_PLL_BYPASS
) ? parent_rate
: 48*MHZ
;
270 static struct clk_ops usb_pll_ops
= {
271 .enable
= usb_pll_clk_enable
,
272 .disable
= usb_pll_clk_disable
,
273 .recalc_rate
= usb_pll_clk_recalc_rate
,
276 static struct clk_init_data clk_usb_pll_init
= {
279 .parent_names
= pll_clk_parents
,
280 .num_parents
= ARRAY_SIZE(pll_clk_parents
),
283 static struct clk_hw usb_pll_clk_hw
= {
284 .init
= &clk_usb_pll_init
,
288 * clock domains - cpu, mem, sys/io, dsp, gfx
291 static const char *dmn_clk_parents
[] = {
299 static u8
dmn_clk_get_parent(struct clk_hw
*hw
)
301 struct clk_dmn
*clk
= to_dmnclk(hw
);
302 u32 cfg
= clkc_readl(clk
->regofs
);
304 /* parent of io domain can only be pll3 */
305 if (strcmp(hw
->init
->name
, "io") == 0)
308 WARN_ON((cfg
& (BIT(3) - 1)) > 4);
310 return cfg
& (BIT(3) - 1);
313 static int dmn_clk_set_parent(struct clk_hw
*hw
, u8 parent
)
315 struct clk_dmn
*clk
= to_dmnclk(hw
);
316 u32 cfg
= clkc_readl(clk
->regofs
);
318 /* parent of io domain can only be pll3 */
319 if (strcmp(hw
->init
->name
, "io") == 0)
322 cfg
&= ~(BIT(3) - 1);
323 clkc_writel(cfg
| parent
, clk
->regofs
);
324 /* BIT(3) - switching status: 1 - busy, 0 - done */
325 while (clkc_readl(clk
->regofs
) & BIT(3))
331 static unsigned long dmn_clk_recalc_rate(struct clk_hw
*hw
,
332 unsigned long parent_rate
)
335 unsigned long fin
= parent_rate
;
336 struct clk_dmn
*clk
= to_dmnclk(hw
);
338 u32 cfg
= clkc_readl(clk
->regofs
);
341 /* fcd bypass mode */
345 * wait count: bit[19:16], hold count: bit[23:20]
347 u32 wait
= (cfg
>> 16) & (BIT(4) - 1);
348 u32 hold
= (cfg
>> 20) & (BIT(4) - 1);
350 return fin
/ (wait
+ hold
+ 2);
354 static long dmn_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
355 unsigned long *parent_rate
)
358 unsigned ratio
, wait
, hold
;
359 unsigned bits
= (strcmp(hw
->init
->name
, "mem") == 0) ? 3 : 4;
366 if (ratio
> BIT(bits
+ 1))
367 ratio
= BIT(bits
+ 1);
369 wait
= (ratio
>> 1) - 1;
370 hold
= ratio
- wait
- 2;
372 return fin
/ (wait
+ hold
+ 2);
375 static int dmn_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
376 unsigned long parent_rate
)
378 struct clk_dmn
*clk
= to_dmnclk(hw
);
380 unsigned ratio
, wait
, hold
, reg
;
381 unsigned bits
= (strcmp(hw
->init
->name
, "mem") == 0) ? 3 : 4;
386 if (unlikely(ratio
< 2 || ratio
> BIT(bits
+ 1)))
391 wait
= (ratio
>> 1) - 1;
392 hold
= ratio
- wait
- 2;
394 reg
= clkc_readl(clk
->regofs
);
395 reg
&= ~(((BIT(bits
) - 1) << 16) | ((BIT(bits
) - 1) << 20));
396 reg
|= (wait
<< 16) | (hold
<< 20) | BIT(25);
397 clkc_writel(reg
, clk
->regofs
);
399 /* waiting FCD been effective */
400 while (clkc_readl(clk
->regofs
) & BIT(25))
406 static struct clk_ops msi_ops
= {
407 .set_rate
= dmn_clk_set_rate
,
408 .round_rate
= dmn_clk_round_rate
,
409 .recalc_rate
= dmn_clk_recalc_rate
,
410 .set_parent
= dmn_clk_set_parent
,
411 .get_parent
= dmn_clk_get_parent
,
414 static struct clk_init_data clk_mem_init
= {
417 .parent_names
= dmn_clk_parents
,
418 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
421 static struct clk_dmn clk_mem
= {
422 .regofs
= SIRFSOC_CLKC_MEM_CFG
,
424 .init
= &clk_mem_init
,
428 static struct clk_init_data clk_sys_init
= {
431 .parent_names
= dmn_clk_parents
,
432 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
433 .flags
= CLK_SET_RATE_GATE
,
436 static struct clk_dmn clk_sys
= {
437 .regofs
= SIRFSOC_CLKC_SYS_CFG
,
439 .init
= &clk_sys_init
,
443 static struct clk_init_data clk_io_init
= {
446 .parent_names
= dmn_clk_parents
,
447 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
450 static struct clk_dmn clk_io
= {
451 .regofs
= SIRFSOC_CLKC_IO_CFG
,
453 .init
= &clk_io_init
,
457 static struct clk_ops cpu_ops
= {
458 .set_parent
= dmn_clk_set_parent
,
459 .get_parent
= dmn_clk_get_parent
,
462 static struct clk_init_data clk_cpu_init
= {
465 .parent_names
= dmn_clk_parents
,
466 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
467 .flags
= CLK_SET_RATE_PARENT
,
470 static struct clk_dmn clk_cpu
= {
471 .regofs
= SIRFSOC_CLKC_CPU_CFG
,
473 .init
= &clk_cpu_init
,
477 static struct clk_ops dmn_ops
= {
478 .is_enabled
= std_clk_is_enabled
,
479 .enable
= std_clk_enable
,
480 .disable
= std_clk_disable
,
481 .set_rate
= dmn_clk_set_rate
,
482 .round_rate
= dmn_clk_round_rate
,
483 .recalc_rate
= dmn_clk_recalc_rate
,
484 .set_parent
= dmn_clk_set_parent
,
485 .get_parent
= dmn_clk_get_parent
,
488 /* dsp, gfx, mm, lcd and vpp domain */
490 static struct clk_init_data clk_dsp_init
= {
493 .parent_names
= dmn_clk_parents
,
494 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
497 static struct clk_dmn clk_dsp
= {
498 .regofs
= SIRFSOC_CLKC_DSP_CFG
,
501 .init
= &clk_dsp_init
,
505 static struct clk_init_data clk_gfx_init
= {
508 .parent_names
= dmn_clk_parents
,
509 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
512 static struct clk_dmn clk_gfx
= {
513 .regofs
= SIRFSOC_CLKC_GFX_CFG
,
516 .init
= &clk_gfx_init
,
520 static struct clk_init_data clk_mm_init
= {
523 .parent_names
= dmn_clk_parents
,
524 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
527 static struct clk_dmn clk_mm
= {
528 .regofs
= SIRFSOC_CLKC_MM_CFG
,
531 .init
= &clk_mm_init
,
535 static struct clk_init_data clk_lcd_init
= {
538 .parent_names
= dmn_clk_parents
,
539 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
542 static struct clk_dmn clk_lcd
= {
543 .regofs
= SIRFSOC_CLKC_LCD_CFG
,
546 .init
= &clk_lcd_init
,
550 static struct clk_init_data clk_vpp_init
= {
553 .parent_names
= dmn_clk_parents
,
554 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
557 static struct clk_dmn clk_vpp
= {
558 .regofs
= SIRFSOC_CLKC_LCD_CFG
,
561 .init
= &clk_vpp_init
,
565 static struct clk_init_data clk_mmc01_init
= {
568 .parent_names
= dmn_clk_parents
,
569 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
572 static struct clk_dmn clk_mmc01
= {
573 .regofs
= SIRFSOC_CLKC_MMC_CFG
,
576 .init
= &clk_mmc01_init
,
580 static struct clk_init_data clk_mmc23_init
= {
583 .parent_names
= dmn_clk_parents
,
584 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
587 static struct clk_dmn clk_mmc23
= {
588 .regofs
= SIRFSOC_CLKC_MMC_CFG
,
591 .init
= &clk_mmc23_init
,
595 static struct clk_init_data clk_mmc45_init
= {
598 .parent_names
= dmn_clk_parents
,
599 .num_parents
= ARRAY_SIZE(dmn_clk_parents
),
602 static struct clk_dmn clk_mmc45
= {
603 .regofs
= SIRFSOC_CLKC_MMC_CFG
,
606 .init
= &clk_mmc45_init
,
611 * peripheral controllers in io domain
614 static int std_clk_is_enabled(struct clk_hw
*hw
)
618 struct clk_std
*clk
= to_stdclk(hw
);
620 bit
= clk
->enable_bit
% 32;
621 reg
= clk
->enable_bit
/ 32;
622 reg
= SIRFSOC_CLKC_CLK_EN0
+ reg
* sizeof(reg
);
624 return !!(clkc_readl(reg
) & BIT(bit
));
627 static int std_clk_enable(struct clk_hw
*hw
)
631 struct clk_std
*clk
= to_stdclk(hw
);
633 BUG_ON(clk
->enable_bit
< 0 || clk
->enable_bit
> 63);
635 bit
= clk
->enable_bit
% 32;
636 reg
= clk
->enable_bit
/ 32;
637 reg
= SIRFSOC_CLKC_CLK_EN0
+ reg
* sizeof(reg
);
639 val
= clkc_readl(reg
) | BIT(bit
);
640 clkc_writel(val
, reg
);
644 static void std_clk_disable(struct clk_hw
*hw
)
648 struct clk_std
*clk
= to_stdclk(hw
);
650 BUG_ON(clk
->enable_bit
< 0 || clk
->enable_bit
> 63);
652 bit
= clk
->enable_bit
% 32;
653 reg
= clk
->enable_bit
/ 32;
654 reg
= SIRFSOC_CLKC_CLK_EN0
+ reg
* sizeof(reg
);
656 val
= clkc_readl(reg
) & ~BIT(bit
);
657 clkc_writel(val
, reg
);
660 static const char *std_clk_io_parents
[] = {
664 static struct clk_ops ios_ops
= {
665 .is_enabled
= std_clk_is_enabled
,
666 .enable
= std_clk_enable
,
667 .disable
= std_clk_disable
,
670 static struct clk_init_data clk_dmac0_init
= {
673 .parent_names
= std_clk_io_parents
,
674 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
677 static struct clk_std clk_dmac0
= {
680 .init
= &clk_dmac0_init
,
684 static struct clk_init_data clk_dmac1_init
= {
687 .parent_names
= std_clk_io_parents
,
688 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
691 static struct clk_std clk_dmac1
= {
694 .init
= &clk_dmac1_init
,
698 static struct clk_init_data clk_nand_init
= {
701 .parent_names
= std_clk_io_parents
,
702 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
705 static struct clk_std clk_nand
= {
708 .init
= &clk_nand_init
,
712 static struct clk_init_data clk_audio_init
= {
715 .parent_names
= std_clk_io_parents
,
716 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
719 static struct clk_std clk_audio
= {
722 .init
= &clk_audio_init
,
726 static struct clk_init_data clk_uart0_init
= {
729 .parent_names
= std_clk_io_parents
,
730 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
733 static struct clk_std clk_uart0
= {
736 .init
= &clk_uart0_init
,
740 static struct clk_init_data clk_uart1_init
= {
743 .parent_names
= std_clk_io_parents
,
744 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
747 static struct clk_std clk_uart1
= {
750 .init
= &clk_uart1_init
,
754 static struct clk_init_data clk_uart2_init
= {
757 .parent_names
= std_clk_io_parents
,
758 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
761 static struct clk_std clk_uart2
= {
764 .init
= &clk_uart2_init
,
768 static struct clk_init_data clk_usp0_init
= {
771 .parent_names
= std_clk_io_parents
,
772 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
775 static struct clk_std clk_usp0
= {
778 .init
= &clk_usp0_init
,
782 static struct clk_init_data clk_usp1_init
= {
785 .parent_names
= std_clk_io_parents
,
786 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
789 static struct clk_std clk_usp1
= {
792 .init
= &clk_usp1_init
,
796 static struct clk_init_data clk_usp2_init
= {
799 .parent_names
= std_clk_io_parents
,
800 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
803 static struct clk_std clk_usp2
= {
806 .init
= &clk_usp2_init
,
810 static struct clk_init_data clk_vip_init
= {
813 .parent_names
= std_clk_io_parents
,
814 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
817 static struct clk_std clk_vip
= {
820 .init
= &clk_vip_init
,
824 static struct clk_init_data clk_spi0_init
= {
827 .parent_names
= std_clk_io_parents
,
828 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
831 static struct clk_std clk_spi0
= {
834 .init
= &clk_spi0_init
,
838 static struct clk_init_data clk_spi1_init
= {
841 .parent_names
= std_clk_io_parents
,
842 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
845 static struct clk_std clk_spi1
= {
848 .init
= &clk_spi1_init
,
852 static struct clk_init_data clk_tsc_init
= {
855 .parent_names
= std_clk_io_parents
,
856 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
859 static struct clk_std clk_tsc
= {
862 .init
= &clk_tsc_init
,
866 static struct clk_init_data clk_i2c0_init
= {
869 .parent_names
= std_clk_io_parents
,
870 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
873 static struct clk_std clk_i2c0
= {
876 .init
= &clk_i2c0_init
,
880 static struct clk_init_data clk_i2c1_init
= {
883 .parent_names
= std_clk_io_parents
,
884 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
887 static struct clk_std clk_i2c1
= {
890 .init
= &clk_i2c1_init
,
894 static struct clk_init_data clk_pwmc_init
= {
897 .parent_names
= std_clk_io_parents
,
898 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
901 static struct clk_std clk_pwmc
= {
904 .init
= &clk_pwmc_init
,
908 static struct clk_init_data clk_efuse_init
= {
911 .parent_names
= std_clk_io_parents
,
912 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
915 static struct clk_std clk_efuse
= {
918 .init
= &clk_efuse_init
,
922 static struct clk_init_data clk_pulse_init
= {
925 .parent_names
= std_clk_io_parents
,
926 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
929 static struct clk_std clk_pulse
= {
932 .init
= &clk_pulse_init
,
936 static const char *std_clk_dsp_parents
[] = {
940 static struct clk_init_data clk_gps_init
= {
943 .parent_names
= std_clk_dsp_parents
,
944 .num_parents
= ARRAY_SIZE(std_clk_dsp_parents
),
947 static struct clk_std clk_gps
= {
950 .init
= &clk_gps_init
,
954 static struct clk_init_data clk_mf_init
= {
957 .parent_names
= std_clk_io_parents
,
958 .num_parents
= ARRAY_SIZE(std_clk_io_parents
),
961 static struct clk_std clk_mf
= {
964 .init
= &clk_mf_init
,
968 static const char *std_clk_sys_parents
[] = {
972 static struct clk_init_data clk_security_init
= {
975 .parent_names
= std_clk_sys_parents
,
976 .num_parents
= ARRAY_SIZE(std_clk_sys_parents
),
979 static struct clk_std clk_security
= {
982 .init
= &clk_security_init
,
986 static const char *std_clk_usb_parents
[] = {
990 static struct clk_init_data clk_usb0_init
= {
993 .parent_names
= std_clk_usb_parents
,
994 .num_parents
= ARRAY_SIZE(std_clk_usb_parents
),
997 static struct clk_std clk_usb0
= {
1000 .init
= &clk_usb0_init
,
1004 static struct clk_init_data clk_usb1_init
= {
1007 .parent_names
= std_clk_usb_parents
,
1008 .num_parents
= ARRAY_SIZE(std_clk_usb_parents
),
1011 static struct clk_std clk_usb1
= {
1014 .init
= &clk_usb1_init
,
1018 static struct of_device_id clkc_ids
[] = {
1019 { .compatible
= "sirf,prima2-clkc" },
1023 static struct of_device_id rsc_ids
[] = {
1024 { .compatible
= "sirf,prima2-rsc" },
1028 enum prima2_clk_index
{
1029 /* 0 1 2 3 4 5 6 7 8 9 */
1030 rtc
, osc
, pll1
, pll2
, pll3
, mem
, sys
, security
, dsp
, gps
,
1031 mf
, io
, cpu
, uart0
, uart1
, uart2
, tsc
, i2c0
, i2c1
, spi0
,
1032 spi1
, pwmc
, efuse
, pulse
, dmac0
, dmac1
, nand
, audio
, usp0
, usp1
,
1033 usp2
, vip
, gfx
, mm
, lcd
, vpp
, mmc01
, mmc23
, mmc45
, usbpll
,
1037 static struct clk_hw
*prima2_clk_hw_array
[maxclk
] __initdata
= {
1082 static struct clk
*prima2_clks
[maxclk
];
1083 static struct clk_onecell_data clk_data
;
1085 void __init
sirfsoc_of_clk_init(void)
1087 struct device_node
*np
;
1090 np
= of_find_matching_node(NULL
, rsc_ids
);
1092 panic("unable to find compatible rsc node in dtb\n");
1094 sirfsoc_rsc_vbase
= of_iomap(np
, 0);
1095 if (!sirfsoc_rsc_vbase
)
1096 panic("unable to map rsc registers\n");
1100 np
= of_find_matching_node(NULL
, clkc_ids
);
1104 sirfsoc_clk_vbase
= of_iomap(np
, 0);
1105 if (!sirfsoc_clk_vbase
)
1106 panic("unable to map clkc registers\n");
1108 /* These are always available (RTC and 26MHz OSC)*/
1109 prima2_clks
[rtc
] = clk_register_fixed_rate(NULL
, "rtc", NULL
,
1110 CLK_IS_ROOT
, 32768);
1111 prima2_clks
[osc
]= clk_register_fixed_rate(NULL
, "osc", NULL
,
1112 CLK_IS_ROOT
, 26000000);
1114 for (i
= pll1
; i
< maxclk
; i
++) {
1115 prima2_clks
[i
] = clk_register(NULL
, prima2_clk_hw_array
[i
]);
1116 BUG_ON(IS_ERR(prima2_clks
[i
]));
1118 clk_register_clkdev(prima2_clks
[cpu
], NULL
, "cpu");
1119 clk_register_clkdev(prima2_clks
[io
], NULL
, "io");
1120 clk_register_clkdev(prima2_clks
[mem
], NULL
, "mem");
1122 clk_data
.clks
= prima2_clks
;
1123 clk_data
.clk_num
= maxclk
;
1125 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);