4 * Copyright 2011-2 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/mfd/wm831x/core.h>
24 struct wm831x
*wm831x
;
25 struct clk_hw xtal_hw
;
27 struct clk_hw clkout_hw
;
34 static int wm831x_xtal_is_prepared(struct clk_hw
*hw
)
36 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
39 return clkdata
->xtal_ena
;
42 static unsigned long wm831x_xtal_recalc_rate(struct clk_hw
*hw
,
43 unsigned long parent_rate
)
45 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
48 if (clkdata
->xtal_ena
)
54 static const struct clk_ops wm831x_xtal_ops
= {
55 .is_prepared
= wm831x_xtal_is_prepared
,
56 .recalc_rate
= wm831x_xtal_recalc_rate
,
59 static struct clk_init_data wm831x_xtal_init
= {
61 .ops
= &wm831x_xtal_ops
,
65 static const unsigned long wm831x_fll_auto_rates
[] = {
76 static int wm831x_fll_is_prepared(struct clk_hw
*hw
)
78 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
80 struct wm831x
*wm831x
= clkdata
->wm831x
;
83 ret
= wm831x_reg_read(wm831x
, WM831X_FLL_CONTROL_1
);
85 dev_err(wm831x
->dev
, "Unable to read FLL_CONTROL_1: %d\n",
90 return (ret
& WM831X_FLL_ENA
) != 0;
93 static int wm831x_fll_prepare(struct clk_hw
*hw
)
95 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
97 struct wm831x
*wm831x
= clkdata
->wm831x
;
100 ret
= wm831x_set_bits(wm831x
, WM831X_FLL_CONTROL_1
,
101 WM831X_FLL_ENA
, WM831X_FLL_ENA
);
103 dev_crit(wm831x
->dev
, "Failed to enable FLL: %d\n", ret
);
105 usleep_range(2000, 2000);
110 static void wm831x_fll_unprepare(struct clk_hw
*hw
)
112 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
114 struct wm831x
*wm831x
= clkdata
->wm831x
;
117 ret
= wm831x_set_bits(wm831x
, WM831X_FLL_CONTROL_1
, WM831X_FLL_ENA
, 0);
119 dev_crit(wm831x
->dev
, "Failed to disable FLL: %d\n", ret
);
122 static unsigned long wm831x_fll_recalc_rate(struct clk_hw
*hw
,
123 unsigned long parent_rate
)
125 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
127 struct wm831x
*wm831x
= clkdata
->wm831x
;
130 ret
= wm831x_reg_read(wm831x
, WM831X_CLOCK_CONTROL_2
);
132 dev_err(wm831x
->dev
, "Unable to read CLOCK_CONTROL_2: %d\n",
137 if (ret
& WM831X_FLL_AUTO
)
138 return wm831x_fll_auto_rates
[ret
& WM831X_FLL_AUTO_FREQ_MASK
];
140 dev_err(wm831x
->dev
, "FLL only supported in AUTO mode\n");
145 static long wm831x_fll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
146 unsigned long *unused
)
151 for (i
= 0; i
< ARRAY_SIZE(wm831x_fll_auto_rates
); i
++)
152 if (abs(wm831x_fll_auto_rates
[i
] - rate
) <
153 abs(wm831x_fll_auto_rates
[best
] - rate
))
156 return wm831x_fll_auto_rates
[best
];
159 static int wm831x_fll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
160 unsigned long parent_rate
)
162 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
164 struct wm831x
*wm831x
= clkdata
->wm831x
;
167 for (i
= 0; i
< ARRAY_SIZE(wm831x_fll_auto_rates
); i
++)
168 if (wm831x_fll_auto_rates
[i
] == rate
)
170 if (i
== ARRAY_SIZE(wm831x_fll_auto_rates
))
173 if (wm831x_fll_is_prepared(hw
))
176 return wm831x_set_bits(wm831x
, WM831X_CLOCK_CONTROL_2
,
177 WM831X_FLL_AUTO_FREQ_MASK
, i
);
180 static const char *wm831x_fll_parents
[] = {
185 static u8
wm831x_fll_get_parent(struct clk_hw
*hw
)
187 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
189 struct wm831x
*wm831x
= clkdata
->wm831x
;
192 /* AUTO mode is always clocked from the crystal */
193 ret
= wm831x_reg_read(wm831x
, WM831X_CLOCK_CONTROL_2
);
195 dev_err(wm831x
->dev
, "Unable to read CLOCK_CONTROL_2: %d\n",
200 if (ret
& WM831X_FLL_AUTO
)
203 ret
= wm831x_reg_read(wm831x
, WM831X_FLL_CONTROL_5
);
205 dev_err(wm831x
->dev
, "Unable to read FLL_CONTROL_5: %d\n",
210 switch (ret
& WM831X_FLL_CLK_SRC_MASK
) {
216 dev_err(wm831x
->dev
, "Unsupported FLL clock source %d\n",
217 ret
& WM831X_FLL_CLK_SRC_MASK
);
222 static const struct clk_ops wm831x_fll_ops
= {
223 .is_prepared
= wm831x_fll_is_prepared
,
224 .prepare
= wm831x_fll_prepare
,
225 .unprepare
= wm831x_fll_unprepare
,
226 .round_rate
= wm831x_fll_round_rate
,
227 .recalc_rate
= wm831x_fll_recalc_rate
,
228 .set_rate
= wm831x_fll_set_rate
,
229 .get_parent
= wm831x_fll_get_parent
,
232 static struct clk_init_data wm831x_fll_init
= {
234 .ops
= &wm831x_fll_ops
,
235 .parent_names
= wm831x_fll_parents
,
236 .num_parents
= ARRAY_SIZE(wm831x_fll_parents
),
237 .flags
= CLK_SET_RATE_GATE
,
240 static int wm831x_clkout_is_prepared(struct clk_hw
*hw
)
242 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
244 struct wm831x
*wm831x
= clkdata
->wm831x
;
247 ret
= wm831x_reg_read(wm831x
, WM831X_CLOCK_CONTROL_1
);
249 dev_err(wm831x
->dev
, "Unable to read CLOCK_CONTROL_1: %d\n",
254 return (ret
& WM831X_CLKOUT_ENA
) != 0;
257 static int wm831x_clkout_prepare(struct clk_hw
*hw
)
259 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
261 struct wm831x
*wm831x
= clkdata
->wm831x
;
264 ret
= wm831x_reg_unlock(wm831x
);
266 dev_crit(wm831x
->dev
, "Failed to lock registers: %d\n", ret
);
270 ret
= wm831x_set_bits(wm831x
, WM831X_CLOCK_CONTROL_1
,
271 WM831X_CLKOUT_ENA
, WM831X_CLKOUT_ENA
);
273 dev_crit(wm831x
->dev
, "Failed to enable CLKOUT: %d\n", ret
);
275 wm831x_reg_lock(wm831x
);
280 static void wm831x_clkout_unprepare(struct clk_hw
*hw
)
282 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
284 struct wm831x
*wm831x
= clkdata
->wm831x
;
287 ret
= wm831x_reg_unlock(wm831x
);
289 dev_crit(wm831x
->dev
, "Failed to lock registers: %d\n", ret
);
293 ret
= wm831x_set_bits(wm831x
, WM831X_CLOCK_CONTROL_1
,
294 WM831X_CLKOUT_ENA
, 0);
296 dev_crit(wm831x
->dev
, "Failed to disable CLKOUT: %d\n", ret
);
298 wm831x_reg_lock(wm831x
);
301 static const char *wm831x_clkout_parents
[] = {
306 static u8
wm831x_clkout_get_parent(struct clk_hw
*hw
)
308 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
310 struct wm831x
*wm831x
= clkdata
->wm831x
;
313 ret
= wm831x_reg_read(wm831x
, WM831X_CLOCK_CONTROL_1
);
315 dev_err(wm831x
->dev
, "Unable to read CLOCK_CONTROL_1: %d\n",
320 if (ret
& WM831X_CLKOUT_SRC
)
326 static int wm831x_clkout_set_parent(struct clk_hw
*hw
, u8 parent
)
328 struct wm831x_clk
*clkdata
= container_of(hw
, struct wm831x_clk
,
330 struct wm831x
*wm831x
= clkdata
->wm831x
;
332 return wm831x_set_bits(wm831x
, WM831X_CLOCK_CONTROL_1
,
334 parent
<< WM831X_CLKOUT_SRC_SHIFT
);
337 static const struct clk_ops wm831x_clkout_ops
= {
338 .is_prepared
= wm831x_clkout_is_prepared
,
339 .prepare
= wm831x_clkout_prepare
,
340 .unprepare
= wm831x_clkout_unprepare
,
341 .get_parent
= wm831x_clkout_get_parent
,
342 .set_parent
= wm831x_clkout_set_parent
,
345 static struct clk_init_data wm831x_clkout_init
= {
347 .ops
= &wm831x_clkout_ops
,
348 .parent_names
= wm831x_clkout_parents
,
349 .num_parents
= ARRAY_SIZE(wm831x_clkout_parents
),
350 .flags
= CLK_SET_RATE_PARENT
,
353 static int wm831x_clk_probe(struct platform_device
*pdev
)
355 struct wm831x
*wm831x
= dev_get_drvdata(pdev
->dev
.parent
);
356 struct wm831x_clk
*clkdata
;
359 clkdata
= devm_kzalloc(&pdev
->dev
, sizeof(*clkdata
), GFP_KERNEL
);
363 clkdata
->wm831x
= wm831x
;
365 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
366 ret
= wm831x_reg_read(wm831x
, WM831X_CLOCK_CONTROL_2
);
368 dev_err(wm831x
->dev
, "Unable to read CLOCK_CONTROL_2: %d\n",
372 clkdata
->xtal_ena
= ret
& WM831X_XTAL_ENA
;
374 clkdata
->xtal_hw
.init
= &wm831x_xtal_init
;
375 clkdata
->xtal
= devm_clk_register(&pdev
->dev
, &clkdata
->xtal_hw
);
376 if (IS_ERR(clkdata
->xtal
))
377 return PTR_ERR(clkdata
->xtal
);
379 clkdata
->fll_hw
.init
= &wm831x_fll_init
;
380 clkdata
->fll
= devm_clk_register(&pdev
->dev
, &clkdata
->fll_hw
);
381 if (IS_ERR(clkdata
->fll
))
382 return PTR_ERR(clkdata
->fll
);
384 clkdata
->clkout_hw
.init
= &wm831x_clkout_init
;
385 clkdata
->clkout
= devm_clk_register(&pdev
->dev
, &clkdata
->clkout_hw
);
386 if (IS_ERR(clkdata
->clkout
))
387 return PTR_ERR(clkdata
->clkout
);
389 platform_set_drvdata(pdev
, clkdata
);
394 static int wm831x_clk_remove(struct platform_device
*pdev
)
399 static struct platform_driver wm831x_clk_driver
= {
400 .probe
= wm831x_clk_probe
,
401 .remove
= wm831x_clk_remove
,
403 .name
= "wm831x-clk",
404 .owner
= THIS_MODULE
,
408 module_platform_driver(wm831x_clk_driver
);
410 /* Module information */
411 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
412 MODULE_DESCRIPTION("WM831x clock driver");
413 MODULE_LICENSE("GPL");
414 MODULE_ALIAS("platform:wm831x-clk");