drivers/clk/mxs/clk-imx28.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk/mxs.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include "clk.h"
  21
  22 static void __iomem *clkctrl;
  23 #define CLKCTRL clkctrl
  24
  25 #define PLL0CTRL0               (CLKCTRL + 0x0000)
  26 #define PLL1CTRL0               (CLKCTRL + 0x0020)
  27 #define PLL2CTRL0               (CLKCTRL + 0x0040)
  28 #define CPU                     (CLKCTRL + 0x0050)
  29 #define HBUS                    (CLKCTRL + 0x0060)
  30 #define XBUS                    (CLKCTRL + 0x0070)
  31 #define XTAL                    (CLKCTRL + 0x0080)
  32 #define SSP0                    (CLKCTRL + 0x0090)
  33 #define SSP1                    (CLKCTRL + 0x00a0)
  34 #define SSP2                    (CLKCTRL + 0x00b0)
  35 #define SSP3                    (CLKCTRL + 0x00c0)
  36 #define GPMI                    (CLKCTRL + 0x00d0)
  37 #define SPDIF                   (CLKCTRL + 0x00e0)
  38 #define EMI                     (CLKCTRL + 0x00f0)
  39 #define SAIF0                   (CLKCTRL + 0x0100)
  40 #define SAIF1                   (CLKCTRL + 0x0110)
  41 #define LCDIF                   (CLKCTRL + 0x0120)
  42 #define ETM                     (CLKCTRL + 0x0130)
  43 #define ENET                    (CLKCTRL + 0x0140)
  44 #define FLEXCAN                 (CLKCTRL + 0x0160)
  45 #define FRAC0                   (CLKCTRL + 0x01b0)
  46 #define FRAC1                   (CLKCTRL + 0x01c0)
  47 #define CLKSEQ                  (CLKCTRL + 0x01d0)
  48
  49 #define BP_CPU_INTERRUPT_WAIT   12
  50 #define BP_SAIF_DIV_FRAC_EN     16
  51 #define BP_ENET_DIV_TIME        21
  52 #define BP_ENET_SLEEP           31
  53 #define BP_CLKSEQ_BYPASS_SAIF0  0
  54 #define BP_CLKSEQ_BYPASS_SSP0   3
  55 #define BP_FRAC0_IO1FRAC        16
  56 #define BP_FRAC0_IO0FRAC        24
  57
  58 static void __iomem *digctrl;
  59 #define DIGCTRL digctrl
  60 #define BP_SAIF_CLKMUX          10
  61
  62 /*
  63  * HW_SAIF_CLKMUX_SEL:
  64  *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
  65  *              clock pins selected for SAIF1 input clocks.
  66  *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
  67  *              SAIF0 clock inputs selected for SAIF1 input clocks.
  68  *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
  69  *              clocks.
  70  *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
  71  *              clocks.
  72  */
  73 int mxs_saif_clkmux_select(unsigned int clkmux)
  74 {
  75         if (clkmux > 0x3)
  76                 return -EINVAL;
  77
  78         writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
  79         writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
  80
  81         return 0;
  82 }
  83
  84 static void __init clk_misc_init(void)
  85 {
  86         u32 val;
  87
  88         /* Gate off cpu clock in WFI for power saving */
  89         writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
  90
  91         /* 0 is a bad default value for a divider */
  92         writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
  93
  94         /* Clear BYPASS for SAIF */
  95         writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
  96
  97         /* SAIF has to use frac div for functional operation */
  98         val = readl_relaxed(SAIF0);
  99         val |= 1 << BP_SAIF_DIV_FRAC_EN;
 100         writel_relaxed(val, SAIF0);
 101
 102         val = readl_relaxed(SAIF1);
 103         val |= 1 << BP_SAIF_DIV_FRAC_EN;
 104         writel_relaxed(val, SAIF1);
 105
 106         /* Extra fec clock setting */
 107         val = readl_relaxed(ENET);
 108         val &= ~(1 << BP_ENET_SLEEP);
 109         writel_relaxed(val, ENET);
 110
 111         /*
 112          * Source ssp clock from ref_io than ref_xtal,
 113          * as ref_xtal only provides 24 MHz as maximum.
 114          */
 115         writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
 116
 117         /*
 118          * 480 MHz seems too high to be ssp clock source directly,
 119          * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 120          */
 121         val = readl_relaxed(FRAC0);
 122         val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
 123         val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 124         writel_relaxed(val, FRAC0);
 125 }
 126
 127 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 128 static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 129 static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
 130 static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
 131 static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
 132 static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", };
 133 static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
 134 static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
 135 static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", };
 136
 137 enum imx28_clk {
 138         ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
 139         ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
 140         ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
 141         lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
 142         ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
 143         emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
 144         clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
 145         ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
 146         fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
 147         clk_max
 148 };
 149
 150 static struct clk *clks[clk_max];
 151 static struct clk_onecell_data clk_data;
 152
 153 static enum imx28_clk clks_init_on[] __initdata = {
 154         cpu, hbus, xbus, emi, uart,
 155 };
 156
 157 int __init mx28_clocks_init(void)
 158 {
 159         struct device_node *np;
 160         u32 i;
 161
 162         np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
 163         digctrl = of_iomap(np, 0);
 164         WARN_ON(!digctrl);
 165
 166         np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
 167         clkctrl = of_iomap(np, 0);
 168         WARN_ON(!clkctrl);
 169
 170         clk_misc_init();
 171
 172         clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
 173         clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
 174         clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
 175         clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
 176         clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
 177         clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
 178         clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
 179         clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
 180         clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
 181         clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
 182         clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
 183         clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
 184         clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
 185         clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
 186         clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
 187         clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
 188         clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
 189         clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
 190         clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
 191         clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
 192         clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
 193         clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
 194         clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
 195         clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
 196         clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
 197         clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
 198         clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
 199         clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
 200         clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
 201         clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
 202         clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
 203         clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
 204         clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
 205         clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
 206         clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
 207         clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
 208         clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
 209         clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
 210         clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
 211         clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
 212         clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
 213         clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
 214         clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
 215         clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
 216         clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
 217         clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
 218         clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
 219         clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
 220         clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
 221         clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
 222         clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
 223         clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
 224         clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
 225         clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
 226         clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
 227         clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
 228         clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
 229         clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
 230         clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
 231         clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
 232         clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
 233         clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
 234         clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
 235         clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
 236         clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
 237
 238         for (i = 0; i < ARRAY_SIZE(clks); i++)
 239                 if (IS_ERR(clks[i])) {
 240                         pr_err("i.MX28 clk %d: register failed with %ld\n",
 241                                 i, PTR_ERR(clks[i]));
 242                         return PTR_ERR(clks[i]);
 243                 }
 244
 245         clk_data.clks = clks;
 246         clk_data.clk_num = ARRAY_SIZE(clks);
 247         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 248
 249         clk_register_clkdev(clks[enet_out], NULL, "enet_out");
 250
 251         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 252                 clk_prepare_enable(clks[clks_init_on[i]]);
 253
 254         return 0;
 255 }