2 * Copyright (C) 2008 STMicroelectronics
3 * Copyright (C) 2010 Alessandro Rubini
4 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
14 #include <linux/clockchips.h>
15 #include <linux/clocksource.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/clk.h>
20 #include <linux/jiffies.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/platform_data/clocksource-nomadik-mtu.h>
24 #include <linux/sched_clock.h>
25 #include <asm/mach/time.h>
28 * The MTU device hosts four different counters, with 4 set of
29 * registers. These are register names.
32 #define MTU_IMSC 0x00 /* Interrupt mask set/clear */
33 #define MTU_RIS 0x04 /* Raw interrupt status */
34 #define MTU_MIS 0x08 /* Masked interrupt status */
35 #define MTU_ICR 0x0C /* Interrupt clear register */
37 /* per-timer registers take 0..3 as argument */
38 #define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
39 #define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
40 #define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
41 #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
43 /* bits for the control register */
44 #define MTU_CRn_ENA 0x80
45 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
46 #define MTU_CRn_PRESCALE_MASK 0x0c
47 #define MTU_CRn_PRESCALE_1 0x00
48 #define MTU_CRn_PRESCALE_16 0x04
49 #define MTU_CRn_PRESCALE_256 0x08
50 #define MTU_CRn_32BITS 0x02
51 #define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
53 /* Other registers are usual amba/primecell registers, currently not used */
54 #define MTU_ITCR 0xff0
55 #define MTU_ITOP 0xff4
57 #define MTU_PERIPH_ID0 0xfe0
58 #define MTU_PERIPH_ID1 0xfe4
59 #define MTU_PERIPH_ID2 0xfe8
60 #define MTU_PERIPH_ID3 0xfeC
62 #define MTU_PCELL0 0xff0
63 #define MTU_PCELL1 0xff4
64 #define MTU_PCELL2 0xff8
65 #define MTU_PCELL3 0xffC
67 static void __iomem
*mtu_base
;
68 static bool clkevt_periodic
;
69 static u32 clk_prescale
;
70 static u32 nmdk_cycle
; /* write-once */
71 static struct delay_timer mtu_delay_timer
;
73 #ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
75 * Override the global weak sched_clock symbol with this
76 * local implementation which uses the clocksource to get some
77 * better resolution when scheduling the kernel.
79 static u32 notrace
nomadik_read_sched_clock(void)
81 if (unlikely(!mtu_base
))
84 return -readl(mtu_base
+ MTU_VAL(0));
88 static unsigned long nmdk_timer_read_current_timer(void)
90 return ~readl_relaxed(mtu_base
+ MTU_VAL(0));
93 /* Clockevent device: use one-shot mode */
94 static int nmdk_clkevt_next(unsigned long evt
, struct clock_event_device
*ev
)
96 writel(1 << 1, mtu_base
+ MTU_IMSC
);
97 writel(evt
, mtu_base
+ MTU_LR(1));
98 /* Load highest value, enable device, enable interrupts */
99 writel(MTU_CRn_ONESHOT
| clk_prescale
|
100 MTU_CRn_32BITS
| MTU_CRn_ENA
,
101 mtu_base
+ MTU_CR(1));
106 void nmdk_clkevt_reset(void)
108 if (clkevt_periodic
) {
109 /* Timer: configure load and background-load, and fire it up */
110 writel(nmdk_cycle
, mtu_base
+ MTU_LR(1));
111 writel(nmdk_cycle
, mtu_base
+ MTU_BGLR(1));
113 writel(MTU_CRn_PERIODIC
| clk_prescale
|
114 MTU_CRn_32BITS
| MTU_CRn_ENA
,
115 mtu_base
+ MTU_CR(1));
116 writel(1 << 1, mtu_base
+ MTU_IMSC
);
118 /* Generate an interrupt to start the clockevent again */
119 (void) nmdk_clkevt_next(nmdk_cycle
, NULL
);
123 static void nmdk_clkevt_mode(enum clock_event_mode mode
,
124 struct clock_event_device
*dev
)
127 case CLOCK_EVT_MODE_PERIODIC
:
128 clkevt_periodic
= true;
131 case CLOCK_EVT_MODE_ONESHOT
:
132 clkevt_periodic
= false;
134 case CLOCK_EVT_MODE_SHUTDOWN
:
135 case CLOCK_EVT_MODE_UNUSED
:
136 writel(0, mtu_base
+ MTU_IMSC
);
138 writel(0, mtu_base
+ MTU_CR(1));
139 /* load some high default value */
140 writel(0xffffffff, mtu_base
+ MTU_LR(1));
142 case CLOCK_EVT_MODE_RESUME
:
147 void nmdk_clksrc_reset(void)
150 writel(0, mtu_base
+ MTU_CR(0));
152 /* ClockSource: configure load and background-load, and fire it up */
153 writel(nmdk_cycle
, mtu_base
+ MTU_LR(0));
154 writel(nmdk_cycle
, mtu_base
+ MTU_BGLR(0));
156 writel(clk_prescale
| MTU_CRn_32BITS
| MTU_CRn_ENA
,
157 mtu_base
+ MTU_CR(0));
160 static void nmdk_clkevt_resume(struct clock_event_device
*cedev
)
166 static struct clock_event_device nmdk_clkevt
= {
168 .features
= CLOCK_EVT_FEAT_ONESHOT
| CLOCK_EVT_FEAT_PERIODIC
|
169 CLOCK_EVT_FEAT_DYNIRQ
,
171 .set_mode
= nmdk_clkevt_mode
,
172 .set_next_event
= nmdk_clkevt_next
,
173 .resume
= nmdk_clkevt_resume
,
177 * IRQ Handler for timer 1 of the MTU block.
179 static irqreturn_t
nmdk_timer_interrupt(int irq
, void *dev_id
)
181 struct clock_event_device
*evdev
= dev_id
;
183 writel(1 << 1, mtu_base
+ MTU_ICR
); /* Interrupt clear reg */
184 evdev
->event_handler(evdev
);
188 static struct irqaction nmdk_timer_irq
= {
189 .name
= "Nomadik Timer Tick",
190 .flags
= IRQF_DISABLED
| IRQF_TIMER
,
191 .handler
= nmdk_timer_interrupt
,
192 .dev_id
= &nmdk_clkevt
,
195 static void __init
__nmdk_timer_init(void __iomem
*base
, int irq
,
196 struct clk
*pclk
, struct clk
*clk
)
202 BUG_ON(clk_prepare_enable(pclk
));
203 BUG_ON(clk_prepare_enable(clk
));
206 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
208 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
209 * At 32 MHz, the timer (with 32 bit counter) can be programmed
210 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
211 * with 16 gives too low timer resolution.
213 rate
= clk_get_rate(clk
);
214 if (rate
> 32000000) {
216 clk_prescale
= MTU_CRn_PRESCALE_16
;
218 clk_prescale
= MTU_CRn_PRESCALE_1
;
221 /* Cycles for periodic mode */
222 nmdk_cycle
= DIV_ROUND_CLOSEST(rate
, HZ
);
225 /* Timer 0 is the free running clocksource */
228 if (clocksource_mmio_init(mtu_base
+ MTU_VAL(0), "mtu_0",
229 rate
, 200, 32, clocksource_mmio_readl_down
))
230 pr_err("timer: failed to initialize clock source %s\n",
233 #ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
234 setup_sched_clock(nomadik_read_sched_clock
, 32, rate
);
237 /* Timer 1 is used for events, register irq and clockevents */
238 setup_irq(irq
, &nmdk_timer_irq
);
239 nmdk_clkevt
.cpumask
= cpumask_of(0);
240 nmdk_clkevt
.irq
= irq
;
241 clockevents_config_and_register(&nmdk_clkevt
, rate
, 2, 0xffffffffU
);
243 mtu_delay_timer
.read_current_timer
= &nmdk_timer_read_current_timer
;
244 mtu_delay_timer
.freq
= rate
;
245 register_current_timer_delay(&mtu_delay_timer
);
248 void __init
nmdk_timer_init(void __iomem
*base
, int irq
)
250 struct clk
*clk0
, *pclk0
;
252 pclk0
= clk_get_sys("mtu0", "apb_pclk");
253 BUG_ON(IS_ERR(pclk0
));
254 clk0
= clk_get_sys("mtu0", NULL
);
255 BUG_ON(IS_ERR(clk0
));
257 __nmdk_timer_init(base
, irq
, pclk0
, clk0
);
260 static void __init
nmdk_timer_of_init(struct device_node
*node
)
267 base
= of_iomap(node
, 0);
269 panic("Can't remap registers");
271 pclk
= of_clk_get_by_name(node
, "apb_pclk");
273 panic("could not get apb_pclk");
275 clk
= of_clk_get_by_name(node
, "timclk");
277 panic("could not get timclk");
279 irq
= irq_of_parse_and_map(node
, 0);
281 panic("Can't parse IRQ");
283 __nmdk_timer_init(base
, irq
, pclk
, clk
);
285 CLOCKSOURCE_OF_DECLARE(nomadik_mtu
, "st,nomadik-mtu",