drivers/edac/highbank_mc_edac.c

   1 /*
   2  * Copyright 2011-2012 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/ctype.h>
  19 #include <linux/edac.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/uaccess.h>
  24
  25 #include "edac_core.h"
  26 #include "edac_module.h"
  27
  28 /* DDR Ctrlr Error Registers */
  29 #define HB_DDR_ECC_OPT                  0x128
  30 #define HB_DDR_ECC_U_ERR_ADDR           0x130
  31 #define HB_DDR_ECC_U_ERR_STAT           0x134
  32 #define HB_DDR_ECC_U_ERR_DATAL          0x138
  33 #define HB_DDR_ECC_U_ERR_DATAH          0x13c
  34 #define HB_DDR_ECC_C_ERR_ADDR           0x140
  35 #define HB_DDR_ECC_C_ERR_STAT           0x144
  36 #define HB_DDR_ECC_C_ERR_DATAL          0x148
  37 #define HB_DDR_ECC_C_ERR_DATAH          0x14c
  38 #define HB_DDR_ECC_INT_STATUS           0x180
  39 #define HB_DDR_ECC_INT_ACK              0x184
  40 #define HB_DDR_ECC_U_ERR_ID             0x424
  41 #define HB_DDR_ECC_C_ERR_ID             0x428
  42
  43 #define HB_DDR_ECC_INT_STAT_CE          0x8
  44 #define HB_DDR_ECC_INT_STAT_DOUBLE_CE   0x10
  45 #define HB_DDR_ECC_INT_STAT_UE          0x20
  46 #define HB_DDR_ECC_INT_STAT_DOUBLE_UE   0x40
  47
  48 #define HB_DDR_ECC_OPT_MODE_MASK        0x3
  49 #define HB_DDR_ECC_OPT_FWC              0x100
  50 #define HB_DDR_ECC_OPT_XOR_SHIFT        16
  51
  52 struct hb_mc_drvdata {
  53         void __iomem *mc_vbase;
  54 };
  55
  56 static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
  57 {
  58         struct mem_ctl_info *mci = dev_id;
  59         struct hb_mc_drvdata *drvdata = mci->pvt_info;
  60         u32 status, err_addr;
  61
  62         /* Read the interrupt status register */
  63         status = readl(drvdata->mc_vbase + HB_DDR_ECC_INT_STATUS);
  64
  65         if (status & HB_DDR_ECC_INT_STAT_UE) {
  66                 err_addr = readl(drvdata->mc_vbase + HB_DDR_ECC_U_ERR_ADDR);
  67                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  68                                      err_addr >> PAGE_SHIFT,
  69                                      err_addr & ~PAGE_MASK, 0,
  70                                      0, 0, -1,
  71                                      mci->ctl_name, "");
  72         }
  73         if (status & HB_DDR_ECC_INT_STAT_CE) {
  74                 u32 syndrome = readl(drvdata->mc_vbase + HB_DDR_ECC_C_ERR_STAT);
  75                 syndrome = (syndrome >> 8) & 0xff;
  76                 err_addr = readl(drvdata->mc_vbase + HB_DDR_ECC_C_ERR_ADDR);
  77                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  78                                      err_addr >> PAGE_SHIFT,
  79                                      err_addr & ~PAGE_MASK, syndrome,
  80                                      0, 0, -1,
  81                                      mci->ctl_name, "");
  82         }
  83
  84         /* clear the error, clears the interrupt */
  85         writel(status, drvdata->mc_vbase + HB_DDR_ECC_INT_ACK);
  86         return IRQ_HANDLED;
  87 }
  88
  89 #ifdef CONFIG_EDAC_DEBUG
  90 static ssize_t highbank_mc_err_inject_write(struct file *file,
  91                                       const char __user *data,
  92                                       size_t count, loff_t *ppos)
  93 {
  94         struct mem_ctl_info *mci = file->private_data;
  95         struct hb_mc_drvdata *pdata = mci->pvt_info;
  96         char buf[32];
  97         size_t buf_size;
  98         u32 reg;
  99         u8 synd;
 100
 101         buf_size = min(count, (sizeof(buf)-1));
 102         if (copy_from_user(buf, data, buf_size))
 103                 return -EFAULT;
 104         buf[buf_size] = 0;
 105
 106         if (!kstrtou8(buf, 16, &synd)) {
 107                 reg = readl(pdata->mc_vbase + HB_DDR_ECC_OPT);
 108                 reg &= HB_DDR_ECC_OPT_MODE_MASK;
 109                 reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
 110                 writel(reg, pdata->mc_vbase + HB_DDR_ECC_OPT);
 111         }
 112
 113         return count;
 114 }
 115
 116 static const struct file_operations highbank_mc_debug_inject_fops = {
 117         .open = simple_open,
 118         .write = highbank_mc_err_inject_write,
 119         .llseek = generic_file_llseek,
 120 };
 121
 122 static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 123 {
 124         if (mci->debugfs)
 125                 debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
 126                                     &highbank_mc_debug_inject_fops);
 127 ;
 128 }
 129 #else
 130 static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 131 {}
 132 #endif
 133
 134 static int highbank_mc_probe(struct platform_device *pdev)
 135 {
 136         struct edac_mc_layer layers[2];
 137         struct mem_ctl_info *mci;
 138         struct hb_mc_drvdata *drvdata;
 139         struct dimm_info *dimm;
 140         struct resource *r;
 141         u32 control;
 142         int irq;
 143         int res = 0;
 144
 145         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 146         layers[0].size = 1;
 147         layers[0].is_virt_csrow = true;
 148         layers[1].type = EDAC_MC_LAYER_CHANNEL;
 149         layers[1].size = 1;
 150         layers[1].is_virt_csrow = false;
 151         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 152                             sizeof(struct hb_mc_drvdata));
 153         if (!mci)
 154                 return -ENOMEM;
 155
 156         mci->pdev = &pdev->dev;
 157         drvdata = mci->pvt_info;
 158         platform_set_drvdata(pdev, mci);
 159
 160         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
 161                 return -ENOMEM;
 162
 163         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 164         if (!r) {
 165                 dev_err(&pdev->dev, "Unable to get mem resource\n");
 166                 res = -ENODEV;
 167                 goto err;
 168         }
 169
 170         if (!devm_request_mem_region(&pdev->dev, r->start,
 171                                      resource_size(r), dev_name(&pdev->dev))) {
 172                 dev_err(&pdev->dev, "Error while requesting mem region\n");
 173                 res = -EBUSY;
 174                 goto err;
 175         }
 176
 177         drvdata->mc_vbase = devm_ioremap(&pdev->dev,
 178                                           r->start, resource_size(r));
 179         if (!drvdata->mc_vbase) {
 180                 dev_err(&pdev->dev, "Unable to map regs\n");
 181                 res = -ENOMEM;
 182                 goto err;
 183         }
 184
 185         control = readl(drvdata->mc_vbase + HB_DDR_ECC_OPT) & 0x3;
 186         if (!control || (control == 0x2)) {
 187                 dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
 188                 res = -ENODEV;
 189                 goto err;
 190         }
 191
 192         mci->mtype_cap = MEM_FLAG_DDR3;
 193         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 194         mci->edac_cap = EDAC_FLAG_SECDED;
 195         mci->mod_name = dev_name(&pdev->dev);
 196         mci->mod_ver = "1";
 197         mci->ctl_name = dev_name(&pdev->dev);
 198         mci->scrub_mode = SCRUB_SW_SRC;
 199
 200         /* Only a single 4GB DIMM is supported */
 201         dimm = *mci->dimms;
 202         dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
 203         dimm->grain = 8;
 204         dimm->dtype = DEV_X8;
 205         dimm->mtype = MEM_DDR3;
 206         dimm->edac_mode = EDAC_SECDED;
 207
 208         res = edac_mc_add_mc(mci);
 209         if (res < 0)
 210                 goto err;
 211
 212         irq = platform_get_irq(pdev, 0);
 213         res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
 214                                0, dev_name(&pdev->dev), mci);
 215         if (res < 0) {
 216                 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
 217                 goto err2;
 218         }
 219
 220         highbank_mc_create_debugfs_nodes(mci);
 221
 222         devres_close_group(&pdev->dev, NULL);
 223         return 0;
 224 err2:
 225         edac_mc_del_mc(&pdev->dev);
 226 err:
 227         devres_release_group(&pdev->dev, NULL);
 228         edac_mc_free(mci);
 229         return res;
 230 }
 231
 232 static int highbank_mc_remove(struct platform_device *pdev)
 233 {
 234         struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 235
 236         edac_mc_del_mc(&pdev->dev);
 237         edac_mc_free(mci);
 238         return 0;
 239 }
 240
 241 static const struct of_device_id hb_ddr_ctrl_of_match[] = {
 242         { .compatible = "calxeda,hb-ddr-ctrl", },
 243         {},
 244 };
 245 MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
 246
 247 static struct platform_driver highbank_mc_edac_driver = {
 248         .probe = highbank_mc_probe,
 249         .remove = highbank_mc_remove,
 250         .driver = {
 251                 .name = "hb_mc_edac",
 252                 .of_match_table = hb_ddr_ctrl_of_match,
 253         },
 254 };
 255
 256 module_platform_driver(highbank_mc_edac_driver);
 257
 258 MODULE_LICENSE("GPL v2");
 259 MODULE_AUTHOR("Calxeda, Inc.");
 260 MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");