x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpio / gpio-sch.c
blob5af65719b95dafad605fb8f1f733ead623b78bf5
1 /*
2 * GPIO interface for Intel Poulsbo SCH
4 * Copyright (c) 2010 CompuLab Ltd
5 * Author: Denis Turischev <denis@compulab.co.il>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License 2 as published
9 * by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/io.h>
25 #include <linux/errno.h>
26 #include <linux/acpi.h>
27 #include <linux/platform_device.h>
28 #include <linux/pci_ids.h>
30 #include <linux/gpio.h>
32 static DEFINE_SPINLOCK(gpio_lock);
34 #define CGEN (0x00)
35 #define CGIO (0x04)
36 #define CGLV (0x08)
38 #define RGEN (0x20)
39 #define RGIO (0x24)
40 #define RGLV (0x28)
42 static unsigned short gpio_ba;
44 static int sch_gpio_core_direction_in(struct gpio_chip *gc, unsigned gpio_num)
46 u8 curr_dirs;
47 unsigned short offset, bit;
49 spin_lock(&gpio_lock);
51 offset = CGIO + gpio_num / 8;
52 bit = gpio_num % 8;
54 curr_dirs = inb(gpio_ba + offset);
56 if (!(curr_dirs & (1 << bit)))
57 outb(curr_dirs | (1 << bit), gpio_ba + offset);
59 spin_unlock(&gpio_lock);
60 return 0;
63 static int sch_gpio_core_get(struct gpio_chip *gc, unsigned gpio_num)
65 int res;
66 unsigned short offset, bit;
68 offset = CGLV + gpio_num / 8;
69 bit = gpio_num % 8;
71 res = !!(inb(gpio_ba + offset) & (1 << bit));
72 return res;
75 static void sch_gpio_core_set(struct gpio_chip *gc, unsigned gpio_num, int val)
77 u8 curr_vals;
78 unsigned short offset, bit;
80 spin_lock(&gpio_lock);
82 offset = CGLV + gpio_num / 8;
83 bit = gpio_num % 8;
85 curr_vals = inb(gpio_ba + offset);
87 if (val)
88 outb(curr_vals | (1 << bit), gpio_ba + offset);
89 else
90 outb((curr_vals & ~(1 << bit)), gpio_ba + offset);
91 spin_unlock(&gpio_lock);
94 static int sch_gpio_core_direction_out(struct gpio_chip *gc,
95 unsigned gpio_num, int val)
97 u8 curr_dirs;
98 unsigned short offset, bit;
100 sch_gpio_core_set(gc, gpio_num, val);
102 spin_lock(&gpio_lock);
104 offset = CGIO + gpio_num / 8;
105 bit = gpio_num % 8;
107 curr_dirs = inb(gpio_ba + offset);
108 if (curr_dirs & (1 << bit))
109 outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
111 spin_unlock(&gpio_lock);
112 return 0;
115 static struct gpio_chip sch_gpio_core = {
116 .label = "sch_gpio_core",
117 .owner = THIS_MODULE,
118 .direction_input = sch_gpio_core_direction_in,
119 .get = sch_gpio_core_get,
120 .direction_output = sch_gpio_core_direction_out,
121 .set = sch_gpio_core_set,
124 static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
125 unsigned gpio_num)
127 u8 curr_dirs;
128 unsigned short offset, bit;
130 spin_lock(&gpio_lock);
132 offset = RGIO + gpio_num / 8;
133 bit = gpio_num % 8;
135 curr_dirs = inb(gpio_ba + offset);
137 if (!(curr_dirs & (1 << bit)))
138 outb(curr_dirs | (1 << bit), gpio_ba + offset);
140 spin_unlock(&gpio_lock);
141 return 0;
144 static int sch_gpio_resume_get(struct gpio_chip *gc, unsigned gpio_num)
146 unsigned short offset, bit;
148 offset = RGLV + gpio_num / 8;
149 bit = gpio_num % 8;
151 return !!(inb(gpio_ba + offset) & (1 << bit));
154 static void sch_gpio_resume_set(struct gpio_chip *gc,
155 unsigned gpio_num, int val)
157 u8 curr_vals;
158 unsigned short offset, bit;
160 spin_lock(&gpio_lock);
162 offset = RGLV + gpio_num / 8;
163 bit = gpio_num % 8;
165 curr_vals = inb(gpio_ba + offset);
167 if (val)
168 outb(curr_vals | (1 << bit), gpio_ba + offset);
169 else
170 outb((curr_vals & ~(1 << bit)), gpio_ba + offset);
172 spin_unlock(&gpio_lock);
175 static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
176 unsigned gpio_num, int val)
178 u8 curr_dirs;
179 unsigned short offset, bit;
181 sch_gpio_resume_set(gc, gpio_num, val);
183 offset = RGIO + gpio_num / 8;
184 bit = gpio_num % 8;
186 spin_lock(&gpio_lock);
188 curr_dirs = inb(gpio_ba + offset);
189 if (curr_dirs & (1 << bit))
190 outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
192 spin_unlock(&gpio_lock);
193 return 0;
196 static struct gpio_chip sch_gpio_resume = {
197 .label = "sch_gpio_resume",
198 .owner = THIS_MODULE,
199 .direction_input = sch_gpio_resume_direction_in,
200 .get = sch_gpio_resume_get,
201 .direction_output = sch_gpio_resume_direction_out,
202 .set = sch_gpio_resume_set,
205 static int sch_gpio_probe(struct platform_device *pdev)
207 struct resource *res;
208 int err, id;
210 id = pdev->id;
211 if (!id)
212 return -ENODEV;
214 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
215 if (!res)
216 return -EBUSY;
218 if (!request_region(res->start, resource_size(res), pdev->name))
219 return -EBUSY;
221 gpio_ba = res->start;
223 switch (id) {
224 case PCI_DEVICE_ID_INTEL_SCH_LPC:
225 sch_gpio_core.base = 0;
226 sch_gpio_core.ngpio = 10;
227 sch_gpio_resume.base = 10;
228 sch_gpio_resume.ngpio = 4;
230 * GPIO[6:0] enabled by default
231 * GPIO7 is configured by the CMC as SLPIOVR
232 * Enable GPIO[9:8] core powered gpios explicitly
234 outb(0x3, gpio_ba + CGEN + 1);
236 * SUS_GPIO[2:0] enabled by default
237 * Enable SUS_GPIO3 resume powered gpio explicitly
239 outb(0x8, gpio_ba + RGEN);
240 break;
242 case PCI_DEVICE_ID_INTEL_ITC_LPC:
243 sch_gpio_core.base = 0;
244 sch_gpio_core.ngpio = 5;
245 sch_gpio_resume.base = 5;
246 sch_gpio_resume.ngpio = 9;
247 break;
249 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
250 sch_gpio_core.base = 0;
251 sch_gpio_core.ngpio = 21;
252 sch_gpio_resume.base = 21;
253 sch_gpio_resume.ngpio = 9;
254 break;
256 default:
257 err = -ENODEV;
258 goto err_sch_gpio_core;
261 sch_gpio_core.dev = &pdev->dev;
262 sch_gpio_resume.dev = &pdev->dev;
264 err = gpiochip_add(&sch_gpio_core);
265 if (err < 0)
266 goto err_sch_gpio_core;
268 err = gpiochip_add(&sch_gpio_resume);
269 if (err < 0)
270 goto err_sch_gpio_resume;
272 return 0;
274 err_sch_gpio_resume:
275 if (gpiochip_remove(&sch_gpio_core))
276 dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
278 err_sch_gpio_core:
279 release_region(res->start, resource_size(res));
280 gpio_ba = 0;
282 return err;
285 static int sch_gpio_remove(struct platform_device *pdev)
287 struct resource *res;
288 if (gpio_ba) {
289 int err;
291 err = gpiochip_remove(&sch_gpio_core);
292 if (err)
293 dev_err(&pdev->dev, "%s failed, %d\n",
294 "gpiochip_remove()", err);
295 err = gpiochip_remove(&sch_gpio_resume);
296 if (err)
297 dev_err(&pdev->dev, "%s failed, %d\n",
298 "gpiochip_remove()", err);
300 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
302 release_region(res->start, resource_size(res));
303 gpio_ba = 0;
305 return err;
308 return 0;
311 static struct platform_driver sch_gpio_driver = {
312 .driver = {
313 .name = "sch_gpio",
314 .owner = THIS_MODULE,
316 .probe = sch_gpio_probe,
317 .remove = sch_gpio_remove,
320 module_platform_driver(sch_gpio_driver);
322 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
323 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
324 MODULE_LICENSE("GPL");
325 MODULE_ALIAS("platform:sch_gpio");