drivers/gpu/drm/gma500/intel_gmbus.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/module.h>
  30 #include <linux/i2c.h>
  31 #include <linux/i2c-algo-bit.h>
  32 #include <drm/drmP.h>
  33 #include "psb_intel_drv.h"
  34 #include <drm/gma_drm.h>
  35 #include "psb_drv.h"
  36 #include "psb_intel_reg.h"
  37
  38 #define _wait_for(COND, MS, W) ({ \
  39         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
  40         int ret__ = 0;                                                  \
  41         while (! (COND)) {                                              \
  42                 if (time_after(jiffies, timeout__)) {                   \
  43                         ret__ = -ETIMEDOUT;                             \
  44                         break;                                          \
  45                 }                                                       \
  46                 if (W && !(in_atomic() || in_dbg_master())) msleep(W);  \
  47         }                                                               \
  48         ret__;                                                          \
  49 })
  50
  51 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  52 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  53
  54 /* Intel GPIO access functions */
  55
  56 #define I2C_RISEFALL_TIME 20
  57
  58 static inline struct intel_gmbus *
  59 to_intel_gmbus(struct i2c_adapter *i2c)
  60 {
  61         return container_of(i2c, struct intel_gmbus, adapter);
  62 }
  63
  64 struct intel_gpio {
  65         struct i2c_adapter adapter;
  66         struct i2c_algo_bit_data algo;
  67         struct drm_psb_private *dev_priv;
  68         u32 reg;
  69 };
  70
  71 void
  72 gma_intel_i2c_reset(struct drm_device *dev)
  73 {
  74         REG_WRITE(GMBUS0, 0);
  75 }
  76
  77 static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
  78 {
  79         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  80         /* FIXME: We are never Pineview, right?
  81
  82         u32 val;
  83
  84         if (!IS_PINEVIEW(dev_priv->dev))
  85                 return;
  86
  87         val = REG_READ(DSPCLK_GATE_D);
  88         if (enable)
  89                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  90         else
  91                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  92         REG_WRITE(DSPCLK_GATE_D, val);
  93
  94         return;
  95         */
  96 }
  97
  98 static u32 get_reserved(struct intel_gpio *gpio)
  99 {
 100         struct drm_psb_private *dev_priv = gpio->dev_priv;
 101         struct drm_device *dev = dev_priv->dev;
 102         u32 reserved = 0;
 103
 104         /* On most chips, these bits must be preserved in software. */
 105         reserved = REG_READ(gpio->reg) &
 106                                      (GPIO_DATA_PULLUP_DISABLE |
 107                                       GPIO_CLOCK_PULLUP_DISABLE);
 108
 109         return reserved;
 110 }
 111
 112 static int get_clock(void *data)
 113 {
 114         struct intel_gpio *gpio = data;
 115         struct drm_psb_private *dev_priv = gpio->dev_priv;
 116         struct drm_device *dev = dev_priv->dev;
 117         u32 reserved = get_reserved(gpio);
 118         REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
 119         REG_WRITE(gpio->reg, reserved);
 120         return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
 121 }
 122
 123 static int get_data(void *data)
 124 {
 125         struct intel_gpio *gpio = data;
 126         struct drm_psb_private *dev_priv = gpio->dev_priv;
 127         struct drm_device *dev = dev_priv->dev;
 128         u32 reserved = get_reserved(gpio);
 129         REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
 130         REG_WRITE(gpio->reg, reserved);
 131         return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
 132 }
 133
 134 static void set_clock(void *data, int state_high)
 135 {
 136         struct intel_gpio *gpio = data;
 137         struct drm_psb_private *dev_priv = gpio->dev_priv;
 138         struct drm_device *dev = dev_priv->dev;
 139         u32 reserved = get_reserved(gpio);
 140         u32 clock_bits;
 141
 142         if (state_high)
 143                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 144         else
 145                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 146                         GPIO_CLOCK_VAL_MASK;
 147
 148         REG_WRITE(gpio->reg, reserved | clock_bits);
 149         REG_READ(gpio->reg); /* Posting */
 150 }
 151
 152 static void set_data(void *data, int state_high)
 153 {
 154         struct intel_gpio *gpio = data;
 155         struct drm_psb_private *dev_priv = gpio->dev_priv;
 156         struct drm_device *dev = dev_priv->dev;
 157         u32 reserved = get_reserved(gpio);
 158         u32 data_bits;
 159
 160         if (state_high)
 161                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 162         else
 163                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 164                         GPIO_DATA_VAL_MASK;
 165
 166         REG_WRITE(gpio->reg, reserved | data_bits);
 167         REG_READ(gpio->reg);
 168 }
 169
 170 static struct i2c_adapter *
 171 intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
 172 {
 173         static const int map_pin_to_reg[] = {
 174                 0,
 175                 GPIOB,
 176                 GPIOA,
 177                 GPIOC,
 178                 GPIOD,
 179                 GPIOE,
 180                 0,
 181                 GPIOF,
 182         };
 183         struct intel_gpio *gpio;
 184
 185         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
 186                 return NULL;
 187
 188         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 189         if (gpio == NULL)
 190                 return NULL;
 191
 192         gpio->reg = map_pin_to_reg[pin];
 193         gpio->dev_priv = dev_priv;
 194
 195         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
 196                  "gma500 GPIO%c", "?BACDE?F"[pin]);
 197         gpio->adapter.owner = THIS_MODULE;
 198         gpio->adapter.algo_data = &gpio->algo;
 199         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 200         gpio->algo.setsda = set_data;
 201         gpio->algo.setscl = set_clock;
 202         gpio->algo.getsda = get_data;
 203         gpio->algo.getscl = get_clock;
 204         gpio->algo.udelay = I2C_RISEFALL_TIME;
 205         gpio->algo.timeout = usecs_to_jiffies(2200);
 206         gpio->algo.data = gpio;
 207
 208         if (i2c_bit_add_bus(&gpio->adapter))
 209                 goto out_free;
 210
 211         return &gpio->adapter;
 212
 213 out_free:
 214         kfree(gpio);
 215         return NULL;
 216 }
 217
 218 static int
 219 intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
 220                      struct i2c_adapter *adapter,
 221                      struct i2c_msg *msgs,
 222                      int num)
 223 {
 224         struct intel_gpio *gpio = container_of(adapter,
 225                                                struct intel_gpio,
 226                                                adapter);
 227         int ret;
 228
 229         gma_intel_i2c_reset(dev_priv->dev);
 230
 231         intel_i2c_quirk_set(dev_priv, true);
 232         set_data(gpio, 1);
 233         set_clock(gpio, 1);
 234         udelay(I2C_RISEFALL_TIME);
 235
 236         ret = adapter->algo->master_xfer(adapter, msgs, num);
 237
 238         set_data(gpio, 1);
 239         set_clock(gpio, 1);
 240         intel_i2c_quirk_set(dev_priv, false);
 241
 242         return ret;
 243 }
 244
 245 static int
 246 gmbus_xfer(struct i2c_adapter *adapter,
 247            struct i2c_msg *msgs,
 248            int num)
 249 {
 250         struct intel_gmbus *bus = container_of(adapter,
 251                                                struct intel_gmbus,
 252                                                adapter);
 253         struct drm_psb_private *dev_priv = adapter->algo_data;
 254         struct drm_device *dev = dev_priv->dev;
 255         int i, reg_offset;
 256
 257         if (bus->force_bit)
 258                 return intel_i2c_quirk_xfer(dev_priv,
 259                                             bus->force_bit, msgs, num);
 260
 261         reg_offset = 0;
 262
 263         REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
 264
 265         for (i = 0; i < num; i++) {
 266                 u16 len = msgs[i].len;
 267                 u8 *buf = msgs[i].buf;
 268
 269                 if (msgs[i].flags & I2C_M_RD) {
 270                         REG_WRITE(GMBUS1 + reg_offset,
 271                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 272                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 273                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 274                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 275                         REG_READ(GMBUS2+reg_offset);
 276                         do {
 277                                 u32 val, loop = 0;
 278
 279                                 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 280                                         goto timeout;
 281                                 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 282                                         goto clear_err;
 283
 284                                 val = REG_READ(GMBUS3 + reg_offset);
 285                                 do {
 286                                         *buf++ = val & 0xff;
 287                                         val >>= 8;
 288                                 } while (--len && ++loop < 4);
 289                         } while (len);
 290                 } else {
 291                         u32 val, loop;
 292
 293                         val = loop = 0;
 294                         do {
 295                                 val |= *buf++ << (8 * loop);
 296                         } while (--len && ++loop < 4);
 297
 298                         REG_WRITE(GMBUS3 + reg_offset, val);
 299                         REG_WRITE(GMBUS1 + reg_offset,
 300                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
 301                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 302                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 303                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 304                         REG_READ(GMBUS2+reg_offset);
 305
 306                         while (len) {
 307                                 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 308                                         goto timeout;
 309                                 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 310                                         goto clear_err;
 311
 312                                 val = loop = 0;
 313                                 do {
 314                                         val |= *buf++ << (8 * loop);
 315                                 } while (--len && ++loop < 4);
 316
 317                                 REG_WRITE(GMBUS3 + reg_offset, val);
 318                                 REG_READ(GMBUS2+reg_offset);
 319                         }
 320                 }
 321
 322                 if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 323                         goto timeout;
 324                 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 325                         goto clear_err;
 326         }
 327
 328         goto done;
 329
 330 clear_err:
 331         /* Toggle the Software Clear Interrupt bit. This has the effect
 332          * of resetting the GMBUS controller and so clearing the
 333          * BUS_ERROR raised by the slave's NAK.
 334          */
 335         REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 336         REG_WRITE(GMBUS1 + reg_offset, 0);
 337
 338 done:
 339         /* Mark the GMBUS interface as disabled. We will re-enable it at the
 340          * start of the next xfer, till then let it sleep.
 341          */
 342         REG_WRITE(GMBUS0 + reg_offset, 0);
 343         return i;
 344
 345 timeout:
 346         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 347                  bus->reg0 & 0xff, bus->adapter.name);
 348         REG_WRITE(GMBUS0 + reg_offset, 0);
 349
 350         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 351         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
 352         if (!bus->force_bit)
 353                 return -ENOMEM;
 354
 355         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
 356 }
 357
 358 static u32 gmbus_func(struct i2c_adapter *adapter)
 359 {
 360         struct intel_gmbus *bus = container_of(adapter,
 361                                                struct intel_gmbus,
 362                                                adapter);
 363
 364         if (bus->force_bit)
 365                 bus->force_bit->algo->functionality(bus->force_bit);
 366
 367         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 368                 /* I2C_FUNC_10BIT_ADDR | */
 369                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 370                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 371 }
 372
 373 static const struct i2c_algorithm gmbus_algorithm = {
 374         .master_xfer    = gmbus_xfer,
 375         .functionality  = gmbus_func
 376 };
 377
 378 /**
 379  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 380  * @dev: DRM device
 381  */
 382 int gma_intel_setup_gmbus(struct drm_device *dev)
 383 {
 384         static const char *names[GMBUS_NUM_PORTS] = {
 385                 "disabled",
 386                 "ssc",
 387                 "vga",
 388                 "panel",
 389                 "dpc",
 390                 "dpb",
 391                 "reserved",
 392                 "dpd",
 393         };
 394         struct drm_psb_private *dev_priv = dev->dev_private;
 395         int ret, i;
 396
 397         dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
 398                                   GFP_KERNEL);
 399         if (dev_priv->gmbus == NULL)
 400                 return -ENOMEM;
 401
 402         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 403                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 404
 405                 bus->adapter.owner = THIS_MODULE;
 406                 bus->adapter.class = I2C_CLASS_DDC;
 407                 snprintf(bus->adapter.name,
 408                          sizeof(bus->adapter.name),
 409                          "gma500 gmbus %s",
 410                          names[i]);
 411
 412                 bus->adapter.dev.parent = &dev->pdev->dev;
 413                 bus->adapter.algo_data  = dev_priv;
 414
 415                 bus->adapter.algo = &gmbus_algorithm;
 416                 ret = i2c_add_adapter(&bus->adapter);
 417                 if (ret)
 418                         goto err;
 419
 420                 /* By default use a conservative clock rate */
 421                 bus->reg0 = i | GMBUS_RATE_100KHZ;
 422
 423                 /* XXX force bit banging until GMBUS is fully debugged */
 424                 bus->force_bit = intel_gpio_create(dev_priv, i);
 425         }
 426
 427         gma_intel_i2c_reset(dev_priv->dev);
 428
 429         return 0;
 430
 431 err:
 432         while (--i) {
 433                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 434                 i2c_del_adapter(&bus->adapter);
 435         }
 436         kfree(dev_priv->gmbus);
 437         dev_priv->gmbus = NULL;
 438         return ret;
 439 }
 440
 441 void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 442 {
 443         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 444
 445         /* speed:
 446          * 0x0 = 100 KHz
 447          * 0x1 = 50 KHz
 448          * 0x2 = 400 KHz
 449          * 0x3 = 1000 Khz
 450          */
 451         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
 452 }
 453
 454 void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 455 {
 456         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 457
 458         if (force_bit) {
 459                 if (bus->force_bit == NULL) {
 460                         struct drm_psb_private *dev_priv = adapter->algo_data;
 461                         bus->force_bit = intel_gpio_create(dev_priv,
 462                                                            bus->reg0 & 0xff);
 463                 }
 464         } else {
 465                 if (bus->force_bit) {
 466                         i2c_del_adapter(bus->force_bit);
 467                         kfree(bus->force_bit);
 468                         bus->force_bit = NULL;
 469                 }
 470         }
 471 }
 472
 473 void gma_intel_teardown_gmbus(struct drm_device *dev)
 474 {
 475         struct drm_psb_private *dev_priv = dev->dev_private;
 476         int i;
 477
 478         if (dev_priv->gmbus == NULL)
 479                 return;
 480
 481         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 482                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 483                 if (bus->force_bit) {
 484                         i2c_del_adapter(bus->force_bit);
 485                         kfree(bus->force_bit);
 486                 }
 487                 i2c_del_adapter(&bus->adapter);
 488         }
 489
 490         kfree(dev_priv->gmbus);
 491         dev_priv->gmbus = NULL;
 492 }