drivers/gpu/drm/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/kref.h>
  24
  25 #include <drm/drmP.h>
  26 #include <drm/drm_global.h>
  27 #include <drm/gma_drm.h>
  28 #include "psb_reg.h"
  29 #include "psb_intel_drv.h"
  30 #include "gma_display.h"
  31 #include "intel_bios.h"
  32 #include "gtt.h"
  33 #include "power.h"
  34 #include "opregion.h"
  35 #include "oaktrail.h"
  36
  37 /* Append new drm mode definition here, align with libdrm definition */
  38 #define DRM_MODE_SCALE_NO_SCALE         2
  39
  40 enum {
  41         CHIP_PSB_8108 = 0,              /* Poulsbo */
  42         CHIP_PSB_8109 = 1,              /* Poulsbo */
  43         CHIP_MRST_4100 = 2,             /* Moorestown/Oaktrail */
  44         CHIP_MFLD_0130 = 3,             /* Medfield */
  45 };
  46
  47 #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
  48 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  49 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
  50 #define IS_CDV(dev) (((dev)->pci_device & 0xfff0) == 0x0be0)
  51
  52 /*
  53  * Driver definitions
  54  */
  55
  56 #define DRIVER_NAME "gma500"
  57 #define DRIVER_DESC "DRM driver for the Intel GMA500"
  58
  59 #define PSB_DRM_DRIVER_DATE "2011-06-06"
  60 #define PSB_DRM_DRIVER_MAJOR 1
  61 #define PSB_DRM_DRIVER_MINOR 0
  62 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  63
  64 /*
  65  *      Hardware offsets
  66  */
  67 #define PSB_VDC_OFFSET           0x00000000
  68 #define PSB_VDC_SIZE             0x000080000
  69 #define MRST_MMIO_SIZE           0x0000C0000
  70 #define MDFLD_MMIO_SIZE          0x000100000
  71 #define PSB_SGX_SIZE             0x8000
  72 #define PSB_SGX_OFFSET           0x00040000
  73 #define MRST_SGX_OFFSET          0x00080000
  74 /*
  75  *      PCI resource identifiers
  76  */
  77 #define PSB_MMIO_RESOURCE        0
  78 #define PSB_GATT_RESOURCE        2
  79 #define PSB_GTT_RESOURCE         3
  80 /*
  81  *      PCI configuration
  82  */
  83 #define PSB_GMCH_CTRL            0x52
  84 #define PSB_BSM                  0x5C
  85 #define _PSB_GMCH_ENABLED        0x4
  86 #define PSB_PGETBL_CTL           0x2020
  87 #define _PSB_PGETBL_ENABLED      0x00000001
  88 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  89
  90 /* To get rid of */
  91 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  92 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  93
  94 /*
  95  *      SGX side MMU definitions (these can probably go)
  96  */
  97
  98 /*
  99  *      Flags for external memory type field.
 100  */
 101 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
 102 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
 103 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
 104 /*
 105  *      PTE's and PDE's
 106  */
 107 #define PSB_PDE_MASK              0x003FFFFF
 108 #define PSB_PDE_SHIFT             22
 109 #define PSB_PTE_SHIFT             12
 110 /*
 111  *      Cache control
 112  */
 113 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 114 #define PSB_PTE_WO                0x0002        /* Write only */
 115 #define PSB_PTE_RO                0x0004        /* Read only */
 116 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 117
 118 /*
 119  *      VDC registers and bits
 120  */
 121 #define PSB_MSVDX_CLOCKGATING     0x2064
 122 #define PSB_TOPAZ_CLOCKGATING     0x2068
 123 #define PSB_HWSTAM                0x2098
 124 #define PSB_INSTPM                0x20C0
 125 #define PSB_INT_IDENTITY_R        0x20A4
 126 #define _PSB_IRQ_ASLE             (1<<0)
 127 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 128 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 129 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 130 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 131 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 132 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 133 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 134 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 135 #define _MDFLD_MIPIA_FLAG         (1<<16)
 136 #define _MDFLD_MIPIC_FLAG         (1<<17)
 137 #define _PSB_IRQ_DISP_HOTSYNC     (1<<17)
 138 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 139 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 140 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 141
 142 #define _PSB_PIPE_EVENT_FLAG    (_PSB_VSYNC_PIPEA_FLAG | \
 143                                  _PSB_VSYNC_PIPEB_FLAG)
 144
 145 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 146 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
 147                                   _MDFLD_PIPEB_EVENT_FLAG | \
 148                                   _PSB_PIPEA_EVENT_FLAG | \
 149                                   _PSB_VSYNC_PIPEA_FLAG | \
 150                                   _MDFLD_MIPIA_FLAG | \
 151                                   _MDFLD_MIPIC_FLAG)
 152 #define PSB_INT_IDENTITY_R        0x20A4
 153 #define PSB_INT_MASK_R            0x20A8
 154 #define PSB_INT_ENABLE_R          0x20A0
 155
 156 #define _PSB_MMU_ER_MASK      0x0001FF00
 157 #define _PSB_MMU_ER_HOST      (1 << 16)
 158 #define GPIOA                   0x5010
 159 #define GPIOB                   0x5014
 160 #define GPIOC                   0x5018
 161 #define GPIOD                   0x501c
 162 #define GPIOE                   0x5020
 163 #define GPIOF                   0x5024
 164 #define GPIOG                   0x5028
 165 #define GPIOH                   0x502c
 166 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 167 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 168 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 169 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 170 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 171 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 172 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 173 #define GPIO_DATA_DIR_MASK              (1 << 8)
 174 #define GPIO_DATA_DIR_IN                (0 << 9)
 175 #define GPIO_DATA_DIR_OUT               (1 << 9)
 176 #define GPIO_DATA_VAL_MASK              (1 << 10)
 177 #define GPIO_DATA_VAL_OUT               (1 << 11)
 178 #define GPIO_DATA_VAL_IN                (1 << 12)
 179 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 180
 181 #define VCLK_DIVISOR_VGA0   0x6000
 182 #define VCLK_DIVISOR_VGA1   0x6004
 183 #define VCLK_POST_DIV       0x6010
 184
 185 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 186 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 187 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 188 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 189 #define PSB_COMM_USER_IRQ (1024 >> 2)
 190 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 191 #define PSB_COMM_FW (2048 >> 2)
 192
 193 #define PSB_UIRQ_VISTEST               1
 194 #define PSB_UIRQ_OOM_REPLY             2
 195 #define PSB_UIRQ_FIRE_TA_REPLY         3
 196 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 197
 198 #define PSB_2D_SIZE (256*1024*1024)
 199 #define PSB_MAX_RELOC_PAGES 1024
 200
 201 #define PSB_LOW_REG_OFFS 0x0204
 202 #define PSB_HIGH_REG_OFFS 0x0600
 203
 204 #define PSB_NUM_VBLANKS 2
 205
 206
 207 #define PSB_2D_SIZE (256*1024*1024)
 208 #define PSB_MAX_RELOC_PAGES 1024
 209
 210 #define PSB_LOW_REG_OFFS 0x0204
 211 #define PSB_HIGH_REG_OFFS 0x0600
 212
 213 #define PSB_NUM_VBLANKS 2
 214 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 215 #define PSB_LID_DELAY (DRM_HZ / 10)
 216
 217 #define MDFLD_PNW_B0 0x04
 218 #define MDFLD_PNW_C0 0x08
 219
 220 #define MDFLD_DSR_2D_3D_0       (1 << 0)
 221 #define MDFLD_DSR_2D_3D_2       (1 << 1)
 222 #define MDFLD_DSR_CURSOR_0      (1 << 2)
 223 #define MDFLD_DSR_CURSOR_2      (1 << 3)
 224 #define MDFLD_DSR_OVERLAY_0     (1 << 4)
 225 #define MDFLD_DSR_OVERLAY_2     (1 << 5)
 226 #define MDFLD_DSR_MIPI_CONTROL  (1 << 6)
 227 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
 228 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
 229 #define MDFLD_DSR_2D_3D         (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
 230
 231 #define MDFLD_DSR_RR            45
 232 #define MDFLD_DPU_ENABLE        (1 << 31)
 233 #define MDFLD_DSR_FULLSCREEN    (1 << 30)
 234 #define MDFLD_DSR_DELAY         (DRM_HZ / MDFLD_DSR_RR)
 235
 236 #define PSB_PWR_STATE_ON                1
 237 #define PSB_PWR_STATE_OFF               2
 238
 239 #define PSB_PMPOLICY_NOPM               0
 240 #define PSB_PMPOLICY_CLOCKGATING        1
 241 #define PSB_PMPOLICY_POWERDOWN          2
 242
 243 #define PSB_PMSTATE_POWERUP             0
 244 #define PSB_PMSTATE_CLOCKGATED          1
 245 #define PSB_PMSTATE_POWERDOWN           2
 246 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 247 #define PSB_PCIx_MSI_DATA_LOC           0x98
 248
 249 /* Medfield crystal settings */
 250 #define KSEL_CRYSTAL_19 1
 251 #define KSEL_BYPASS_19 5
 252 #define KSEL_BYPASS_25 6
 253 #define KSEL_BYPASS_83_100 7
 254
 255 struct opregion_header;
 256 struct opregion_acpi;
 257 struct opregion_swsci;
 258 struct opregion_asle;
 259
 260 struct psb_intel_opregion {
 261         struct opregion_header *header;
 262         struct opregion_acpi *acpi;
 263         struct opregion_swsci *swsci;
 264         struct opregion_asle *asle;
 265         void *vbt;
 266         u32 __iomem *lid_state;
 267 };
 268
 269 struct sdvo_device_mapping {
 270         u8 initialized;
 271         u8 dvo_port;
 272         u8 slave_addr;
 273         u8 dvo_wiring;
 274         u8 i2c_pin;
 275         u8 i2c_speed;
 276         u8 ddc_pin;
 277 };
 278
 279 struct intel_gmbus {
 280         struct i2c_adapter adapter;
 281         struct i2c_adapter *force_bit;
 282         u32 reg0;
 283 };
 284
 285 /*
 286  *      Register offset maps
 287  */
 288
 289 struct psb_offset {
 290         u32     fp0;
 291         u32     fp1;
 292         u32     cntr;
 293         u32     conf;
 294         u32     src;
 295         u32     dpll;
 296         u32     dpll_md;
 297         u32     htotal;
 298         u32     hblank;
 299         u32     hsync;
 300         u32     vtotal;
 301         u32     vblank;
 302         u32     vsync;
 303         u32     stride;
 304         u32     size;
 305         u32     pos;
 306         u32     surf;
 307         u32     addr;
 308         u32     base;
 309         u32     status;
 310         u32     linoff;
 311         u32     tileoff;
 312         u32     palette;
 313 };
 314
 315 /*
 316  *      Register save state. This is used to hold the context when the
 317  *      device is powered off. In the case of Oaktrail this can (but does not
 318  *      yet) include screen blank. Operations occuring during the save
 319  *      update the register cache instead.
 320  */
 321
 322 /*
 323  *      Common status for pipes.
 324  */
 325 struct psb_pipe {
 326         u32     fp0;
 327         u32     fp1;
 328         u32     cntr;
 329         u32     conf;
 330         u32     src;
 331         u32     dpll;
 332         u32     dpll_md;
 333         u32     htotal;
 334         u32     hblank;
 335         u32     hsync;
 336         u32     vtotal;
 337         u32     vblank;
 338         u32     vsync;
 339         u32     stride;
 340         u32     size;
 341         u32     pos;
 342         u32     base;
 343         u32     surf;
 344         u32     addr;
 345         u32     status;
 346         u32     linoff;
 347         u32     tileoff;
 348         u32     palette[256];
 349 };
 350
 351 struct psb_state {
 352         uint32_t saveVCLK_DIVISOR_VGA0;
 353         uint32_t saveVCLK_DIVISOR_VGA1;
 354         uint32_t saveVCLK_POST_DIV;
 355         uint32_t saveVGACNTRL;
 356         uint32_t saveADPA;
 357         uint32_t saveLVDS;
 358         uint32_t saveDVOA;
 359         uint32_t saveDVOB;
 360         uint32_t saveDVOC;
 361         uint32_t savePP_ON;
 362         uint32_t savePP_OFF;
 363         uint32_t savePP_CONTROL;
 364         uint32_t savePP_CYCLE;
 365         uint32_t savePFIT_CONTROL;
 366         uint32_t saveCLOCKGATING;
 367         uint32_t saveDSPARB;
 368         uint32_t savePFIT_AUTO_RATIOS;
 369         uint32_t savePFIT_PGM_RATIOS;
 370         uint32_t savePP_ON_DELAYS;
 371         uint32_t savePP_OFF_DELAYS;
 372         uint32_t savePP_DIVISOR;
 373         uint32_t saveBCLRPAT_A;
 374         uint32_t saveBCLRPAT_B;
 375         uint32_t savePERF_MODE;
 376         uint32_t saveDSPFW1;
 377         uint32_t saveDSPFW2;
 378         uint32_t saveDSPFW3;
 379         uint32_t saveDSPFW4;
 380         uint32_t saveDSPFW5;
 381         uint32_t saveDSPFW6;
 382         uint32_t saveCHICKENBIT;
 383         uint32_t saveDSPACURSOR_CTRL;
 384         uint32_t saveDSPBCURSOR_CTRL;
 385         uint32_t saveDSPACURSOR_BASE;
 386         uint32_t saveDSPBCURSOR_BASE;
 387         uint32_t saveDSPACURSOR_POS;
 388         uint32_t saveDSPBCURSOR_POS;
 389         uint32_t saveOV_OVADD;
 390         uint32_t saveOV_OGAMC0;
 391         uint32_t saveOV_OGAMC1;
 392         uint32_t saveOV_OGAMC2;
 393         uint32_t saveOV_OGAMC3;
 394         uint32_t saveOV_OGAMC4;
 395         uint32_t saveOV_OGAMC5;
 396         uint32_t saveOVC_OVADD;
 397         uint32_t saveOVC_OGAMC0;
 398         uint32_t saveOVC_OGAMC1;
 399         uint32_t saveOVC_OGAMC2;
 400         uint32_t saveOVC_OGAMC3;
 401         uint32_t saveOVC_OGAMC4;
 402         uint32_t saveOVC_OGAMC5;
 403
 404         /* DPST register save */
 405         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
 406         uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
 407         uint32_t savePWM_CONTROL_LOGIC;
 408 };
 409
 410 struct medfield_state {
 411         uint32_t saveMIPI;
 412         uint32_t saveMIPI_C;
 413
 414         uint32_t savePFIT_CONTROL;
 415         uint32_t savePFIT_PGM_RATIOS;
 416         uint32_t saveHDMIPHYMISCCTL;
 417         uint32_t saveHDMIB_CONTROL;
 418 };
 419
 420 struct cdv_state {
 421         uint32_t saveDSPCLK_GATE_D;
 422         uint32_t saveRAMCLK_GATE_D;
 423         uint32_t saveDSPARB;
 424         uint32_t saveDSPFW[6];
 425         uint32_t saveADPA;
 426         uint32_t savePP_CONTROL;
 427         uint32_t savePFIT_PGM_RATIOS;
 428         uint32_t saveLVDS;
 429         uint32_t savePFIT_CONTROL;
 430         uint32_t savePP_ON_DELAYS;
 431         uint32_t savePP_OFF_DELAYS;
 432         uint32_t savePP_CYCLE;
 433         uint32_t saveVGACNTRL;
 434         uint32_t saveIER;
 435         uint32_t saveIMR;
 436         u8       saveLBB;
 437 };
 438
 439 struct psb_save_area {
 440         struct psb_pipe pipe[3];
 441         uint32_t saveBSM;
 442         uint32_t saveVBT;
 443         union {
 444                 struct psb_state psb;
 445                 struct medfield_state mdfld;
 446                 struct cdv_state cdv;
 447         };
 448         uint32_t saveBLC_PWM_CTL2;
 449         uint32_t saveBLC_PWM_CTL;
 450 };
 451
 452 struct psb_ops;
 453
 454 #define PSB_NUM_PIPE            3
 455
 456 struct drm_psb_private {
 457         struct drm_device *dev;
 458         const struct psb_ops *ops;
 459         const struct psb_offset *regmap;
 460
 461         struct child_device_config *child_dev;
 462         int child_dev_num;
 463
 464         struct psb_gtt gtt;
 465
 466         /* GTT Memory manager */
 467         struct psb_gtt_mm *gtt_mm;
 468         struct page *scratch_page;
 469         u32 __iomem *gtt_map;
 470         uint32_t stolen_base;
 471         u8 __iomem *vram_addr;
 472         unsigned long vram_stolen_size;
 473         int gtt_initialized;
 474         u16 gmch_ctrl;          /* Saved GTT setup */
 475         u32 pge_ctl;
 476
 477         struct mutex gtt_mutex;
 478         struct resource *gtt_mem;       /* Our PCI resource */
 479
 480         struct psb_mmu_driver *mmu;
 481         struct psb_mmu_pd *pf_pd;
 482
 483         /*
 484          * Register base
 485          */
 486
 487         uint8_t __iomem *sgx_reg;
 488         uint8_t __iomem *vdc_reg;
 489         uint32_t gatt_free_offset;
 490
 491         /*
 492          * Fencing / irq.
 493          */
 494
 495         uint32_t vdc_irq_mask;
 496         uint32_t pipestat[PSB_NUM_PIPE];
 497
 498         spinlock_t irqmask_lock;
 499
 500         /*
 501          * Power
 502          */
 503
 504         bool suspended;
 505         bool display_power;
 506         int display_count;
 507
 508         /*
 509          * Modesetting
 510          */
 511         struct psb_intel_mode_device mode_dev;
 512         bool modeset;   /* true if we have done the mode_device setup */
 513
 514         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 515         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 516         uint32_t num_pipe;
 517
 518         /*
 519          * OSPM info (Power management base) (can go ?)
 520          */
 521         uint32_t ospm_base;
 522
 523         /*
 524          * Sizes info
 525          */
 526
 527         u32 fuse_reg_value;
 528         u32 video_device_fuse;
 529
 530         /* PCI revision ID for B0:D2:F0 */
 531         uint8_t platform_rev_id;
 532
 533         /* gmbus */
 534         struct intel_gmbus *gmbus;
 535
 536         /* Used by SDVO */
 537         int crt_ddc_pin;
 538         /* FIXME: The mappings should be parsed from bios but for now we can
 539                   pretend there are no mappings available */
 540         struct sdvo_device_mapping sdvo_mappings[2];
 541         u32 hotplug_supported_mask;
 542         struct drm_property *broadcast_rgb_property;
 543         struct drm_property *force_audio_property;
 544
 545         /*
 546          * LVDS info
 547          */
 548         int backlight_duty_cycle;       /* restore backlight to this value */
 549         bool panel_wants_dither;
 550         struct drm_display_mode *panel_fixed_mode;
 551         struct drm_display_mode *lfp_lvds_vbt_mode;
 552         struct drm_display_mode *sdvo_lvds_vbt_mode;
 553
 554         struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
 555         struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
 556
 557         /* Feature bits from the VBIOS */
 558         unsigned int int_tv_support:1;
 559         unsigned int lvds_dither:1;
 560         unsigned int lvds_vbt:1;
 561         unsigned int int_crt_support:1;
 562         unsigned int lvds_use_ssc:1;
 563         int lvds_ssc_freq;
 564         bool is_lvds_on;
 565         bool is_mipi_on;
 566         u32 mipi_ctrl_display;
 567
 568         unsigned int core_freq;
 569         uint32_t iLVDS_enable;
 570
 571         /* Runtime PM state */
 572         int rpm_enabled;
 573
 574         /* MID specific */
 575         bool has_gct;
 576         struct oaktrail_gct_data gct_data;
 577
 578         /* Oaktrail HDMI state */
 579         struct oaktrail_hdmi_dev *hdmi_priv;
 580
 581         /*
 582          * Register state
 583          */
 584
 585         struct psb_save_area regs;
 586
 587         /* MSI reg save */
 588         uint32_t msi_addr;
 589         uint32_t msi_data;
 590
 591         /*
 592          * Hotplug handling
 593          */
 594
 595         struct work_struct hotplug_work;
 596
 597         /*
 598          * LID-Switch
 599          */
 600         spinlock_t lid_lock;
 601         struct timer_list lid_timer;
 602         struct psb_intel_opregion opregion;
 603         u32 lid_last_state;
 604
 605         /*
 606          * Watchdog
 607          */
 608
 609         uint32_t apm_reg;
 610         uint16_t apm_base;
 611
 612         /*
 613          * Used for modifying backlight from
 614          * xrandr -- consider removing and using HAL instead
 615          */
 616         struct backlight_device *backlight_device;
 617         struct drm_property *backlight_property;
 618         bool backlight_enabled;
 619         int backlight_level;
 620         uint32_t blc_adj1;
 621         uint32_t blc_adj2;
 622
 623         void *fbdev;
 624
 625         /* 2D acceleration */
 626         spinlock_t lock_2d;
 627
 628         /*
 629          * Panel brightness
 630          */
 631         int brightness;
 632         int brightness_adjusted;
 633
 634         bool dsr_enable;
 635         u32 dsr_fb_update;
 636         bool dpi_panel_on[3];
 637         void *dsi_configs[2];
 638         u32 bpp;
 639         u32 bpp2;
 640
 641         u32 pipeconf[3];
 642         u32 dspcntr[3];
 643
 644         int mdfld_panel_id;
 645
 646         bool dplla_96mhz;       /* DPLL data from the VBT */
 647
 648         struct {
 649                 int rate;
 650                 int lanes;
 651                 int preemphasis;
 652                 int vswing;
 653
 654                 bool initialized;
 655                 bool support;
 656                 int bpp;
 657                 struct edp_power_seq pps;
 658         } edp;
 659         uint8_t panel_type;
 660 };
 661
 662
 663 /*
 664  *      Operations for each board type
 665  */
 666
 667 struct psb_ops {
 668         const char *name;
 669         unsigned int accel_2d:1;
 670         int pipes;              /* Number of output pipes */
 671         int crtcs;              /* Number of CRTCs */
 672         int sgx_offset;         /* Base offset of SGX device */
 673         int hdmi_mask;          /* Mask of HDMI CRTCs */
 674         int lvds_mask;          /* Mask of LVDS CRTCs */
 675         int cursor_needs_phys;  /* If cursor base reg need physical address */
 676
 677         /* Sub functions */
 678         struct drm_crtc_helper_funcs const *crtc_helper;
 679         struct drm_crtc_funcs const *crtc_funcs;
 680         const struct gma_clock_funcs *clock_funcs;
 681
 682         /* Setup hooks */
 683         int (*chip_setup)(struct drm_device *dev);
 684         void (*chip_teardown)(struct drm_device *dev);
 685         /* Optional helper caller after modeset */
 686         void (*errata)(struct drm_device *dev);
 687
 688         /* Display management hooks */
 689         int (*output_init)(struct drm_device *dev);
 690         int (*hotplug)(struct drm_device *dev);
 691         void (*hotplug_enable)(struct drm_device *dev, bool on);
 692         /* Power management hooks */
 693         void (*init_pm)(struct drm_device *dev);
 694         int (*save_regs)(struct drm_device *dev);
 695         int (*restore_regs)(struct drm_device *dev);
 696         int (*power_up)(struct drm_device *dev);
 697         int (*power_down)(struct drm_device *dev);
 698         void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
 699         void (*disable_sr)(struct drm_device *dev);
 700
 701         void (*lvds_bl_power)(struct drm_device *dev, bool on);
 702 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 703         /* Backlight */
 704         int (*backlight_init)(struct drm_device *dev);
 705 #endif
 706         int i2c_bus;            /* I2C bus identifier for Moorestown */
 707 };
 708
 709
 710
 711 struct psb_mmu_driver;
 712
 713 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 714 extern int drm_pick_crtcs(struct drm_device *dev);
 715
 716 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 717 {
 718         return (struct drm_psb_private *) dev->dev_private;
 719 }
 720
 721 /*
 722  * MMU stuff.
 723  */
 724
 725 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 726                                         int trap_pagefaults,
 727                                         int invalid_type,
 728                                         struct drm_psb_private *dev_priv);
 729 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 730 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 731                                                  *driver);
 732 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 733                                uint32_t gtt_start, uint32_t gtt_pages);
 734 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 735                                            int trap_pagefaults,
 736                                            int invalid_type);
 737 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 738 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 739 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 740                                         unsigned long address,
 741                                         uint32_t num_pages);
 742 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 743                                        uint32_t start_pfn,
 744                                        unsigned long address,
 745                                        uint32_t num_pages, int type);
 746 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 747                                   unsigned long *pfn);
 748
 749 /*
 750  * Enable / disable MMU for different requestors.
 751  */
 752
 753
 754 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 755 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 756                                 unsigned long address, uint32_t num_pages,
 757                                 uint32_t desired_tile_stride,
 758                                 uint32_t hw_tile_stride, int type);
 759 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 760                                  unsigned long address, uint32_t num_pages,
 761                                  uint32_t desired_tile_stride,
 762                                  uint32_t hw_tile_stride);
 763 /*
 764  *psb_irq.c
 765  */
 766
 767 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 768 extern int psb_irq_enable_dpst(struct drm_device *dev);
 769 extern int psb_irq_disable_dpst(struct drm_device *dev);
 770 extern void psb_irq_preinstall(struct drm_device *dev);
 771 extern int psb_irq_postinstall(struct drm_device *dev);
 772 extern void psb_irq_uninstall(struct drm_device *dev);
 773 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 774 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 775
 776 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 777 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 778 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 779 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 780 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 781 void
 782 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 783
 784 void
 785 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 786
 787 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 788
 789 /*
 790  * framebuffer.c
 791  */
 792 extern int psbfb_probed(struct drm_device *dev);
 793 extern int psbfb_remove(struct drm_device *dev,
 794                         struct drm_framebuffer *fb);
 795 /*
 796  * accel_2d.c
 797  */
 798 extern void psbfb_copyarea(struct fb_info *info,
 799                                         const struct fb_copyarea *region);
 800 extern int psbfb_sync(struct fb_info *info);
 801 extern void psb_spank(struct drm_psb_private *dev_priv);
 802
 803 /*
 804  * psb_reset.c
 805  */
 806
 807 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 808 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 809 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 810
 811 /* modesetting */
 812 extern void psb_modeset_init(struct drm_device *dev);
 813 extern void psb_modeset_cleanup(struct drm_device *dev);
 814 extern int psb_fbdev_init(struct drm_device *dev);
 815
 816 /* backlight.c */
 817 int gma_backlight_init(struct drm_device *dev);
 818 void gma_backlight_exit(struct drm_device *dev);
 819 void gma_backlight_disable(struct drm_device *dev);
 820 void gma_backlight_enable(struct drm_device *dev);
 821 void gma_backlight_set(struct drm_device *dev, int v);
 822
 823 /* oaktrail_crtc.c */
 824 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
 825
 826 /* oaktrail_lvds.c */
 827 extern void oaktrail_lvds_init(struct drm_device *dev,
 828                     struct psb_intel_mode_device *mode_dev);
 829
 830 /* psb_intel_display.c */
 831 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
 832 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
 833
 834 /* psb_intel_lvds.c */
 835 extern const struct drm_connector_helper_funcs
 836                                         psb_intel_lvds_connector_helper_funcs;
 837 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 838
 839 /* gem.c */
 840 extern int psb_gem_init_object(struct drm_gem_object *obj);
 841 extern void psb_gem_free_object(struct drm_gem_object *obj);
 842 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
 843                         struct drm_file *file);
 844 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 845                         struct drm_mode_create_dumb *args);
 846 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
 847                         uint32_t handle, uint64_t *offset);
 848 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 849 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
 850                         struct drm_file *file);
 851 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
 852                                         struct drm_file *file);
 853
 854 /* psb_device.c */
 855 extern const struct psb_ops psb_chip_ops;
 856
 857 /* oaktrail_device.c */
 858 extern const struct psb_ops oaktrail_chip_ops;
 859
 860 /* mdlfd_device.c */
 861 extern const struct psb_ops mdfld_chip_ops;
 862
 863 /* cdv_device.c */
 864 extern const struct psb_ops cdv_chip_ops;
 865
 866 /*
 867  * Debug print bits setting
 868  */
 869 #define PSB_D_GENERAL (1 << 0)
 870 #define PSB_D_INIT    (1 << 1)
 871 #define PSB_D_IRQ     (1 << 2)
 872 #define PSB_D_ENTRY   (1 << 3)
 873 /* debug the get H/V BP/FP count */
 874 #define PSB_D_HV      (1 << 4)
 875 #define PSB_D_DBI_BF  (1 << 5)
 876 #define PSB_D_PM      (1 << 6)
 877 #define PSB_D_RENDER  (1 << 7)
 878 #define PSB_D_REG     (1 << 8)
 879 #define PSB_D_MSVDX   (1 << 9)
 880 #define PSB_D_TOPAZ   (1 << 10)
 881
 882 extern int drm_idle_check_interval;
 883
 884 /*
 885  *      Utilities
 886  */
 887
 888 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 889 {
 890         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 891         uint32_t ret_val = 0;
 892         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 893         pci_write_config_dword(pci_root, 0xD0, mcr);
 894         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 895         pci_dev_put(pci_root);
 896         return ret_val;
 897 }
 898 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 899 {
 900         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 901         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 902         pci_write_config_dword(pci_root, 0xD4, value);
 903         pci_write_config_dword(pci_root, 0xD0, mcr);
 904         pci_dev_put(pci_root);
 905 }
 906 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 907 {
 908         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 909         uint32_t ret_val = 0;
 910         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 911         pci_write_config_dword(pci_root, 0xD0, mcr);
 912         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 913         pci_dev_put(pci_root);
 914         return ret_val;
 915 }
 916 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 917 {
 918         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 919         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 920         pci_write_config_dword(pci_root, 0xD4, value);
 921         pci_write_config_dword(pci_root, 0xD0, mcr);
 922         pci_dev_put(pci_root);
 923 }
 924
 925 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 926 {
 927         struct drm_psb_private *dev_priv = dev->dev_private;
 928         return ioread32(dev_priv->vdc_reg + reg);
 929 }
 930
 931 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 932
 933 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 934                                       uint32_t val)
 935 {
 936         struct drm_psb_private *dev_priv = dev->dev_private;
 937         iowrite32((val), dev_priv->vdc_reg + (reg));
 938 }
 939
 940 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 941
 942 static inline void REGISTER_WRITE16(struct drm_device *dev,
 943                                         uint32_t reg, uint32_t val)
 944 {
 945         struct drm_psb_private *dev_priv = dev->dev_private;
 946         iowrite16((val), dev_priv->vdc_reg + (reg));
 947 }
 948
 949 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 950
 951 static inline void REGISTER_WRITE8(struct drm_device *dev,
 952                                        uint32_t reg, uint32_t val)
 953 {
 954         struct drm_psb_private *dev_priv = dev->dev_private;
 955         iowrite8((val), dev_priv->vdc_reg + (reg));
 956 }
 957
 958 #define REG_WRITE8(reg, val)            REGISTER_WRITE8(dev, (reg), (val))
 959
 960 #define PSB_WVDC32(_val, _offs)         iowrite32(_val, dev_priv->vdc_reg + (_offs))
 961 #define PSB_RVDC32(_offs)               ioread32(dev_priv->vdc_reg + (_offs))
 962
 963 /* #define TRAP_SGX_PM_FAULT 1 */
 964 #ifdef TRAP_SGX_PM_FAULT
 965 #define PSB_RSGX32(_offs)                                               \
 966 ({                                                                      \
 967         if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {              \
 968                 printk(KERN_ERR                                         \
 969                         "access sgx when it's off!! (READ) %s, %d\n",   \
 970                __FILE__, __LINE__);                                     \
 971                 melay(1000);                                            \
 972         }                                                               \
 973         ioread32(dev_priv->sgx_reg + (_offs));                          \
 974 })
 975 #else
 976 #define PSB_RSGX32(_offs)               ioread32(dev_priv->sgx_reg + (_offs))
 977 #endif
 978 #define PSB_WSGX32(_val, _offs)         iowrite32(_val, dev_priv->sgx_reg + (_offs))
 979
 980 #define MSVDX_REG_DUMP 0
 981
 982 #define PSB_WMSVDX32(_val, _offs)       iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 983 #define PSB_RMSVDX32(_offs)             ioread32(dev_priv->msvdx_reg + (_offs))
 984
 985 #endif