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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
blobeb7af5b430aa757aa4749172b1d5e2c29f9f2319
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include "i915_drv.h"
32
33 static const char *yesno(int v)
34 {
35 return v ? "yes" : "no";
36 }
37
38 static const char *ring_str(int ring)
39 {
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47 }
48
49 static const char *pin_flag(int pinned)
50 {
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57 }
58
59 static const char *tiling_flag(int tiling)
60 {
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67 }
68
69 static const char *dirty_flag(int dirty)
70 {
71 return dirty ? " dirty" : "";
72 }
73
74 static const char *purgeable_flag(int purgeable)
75 {
76 return purgeable ? " purgeable" : "";
77 }
78
79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80 {
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91 }
92
93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95 {
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108 }
109
110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112 {
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134 }
135
136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138 {
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
146 va_list tmp;
147
148 va_copy(tmp, args);
149 len = vsnprintf(NULL, 0, f, tmp);
150 va_end(tmp);
151
152 if (!__i915_error_seek(e, len))
153 return;
154 }
155
156 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
157 if (len >= e->size - e->bytes)
158 len = e->size - e->bytes - 1;
159
160 __i915_error_advance(e, len);
161 }
162
163 static void i915_error_puts(struct drm_i915_error_state_buf *e,
164 const char *str)
165 {
166 unsigned len;
167
168 if (!__i915_error_ok(e))
169 return;
170
171 len = strlen(str);
172
173 /* Seek the first printf which is hits start position */
174 if (e->pos < e->start) {
175 if (!__i915_error_seek(e, len))
176 return;
177 }
178
179 if (len >= e->size - e->bytes)
180 len = e->size - e->bytes - 1;
181 memcpy(e->buf + e->bytes, str, len);
182
183 __i915_error_advance(e, len);
184 }
185
186 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
187 #define err_puts(e, s) i915_error_puts(e, s)
188
189 static void print_error_buffers(struct drm_i915_error_state_buf *m,
190 const char *name,
191 struct drm_i915_error_buffer *err,
192 int count)
193 {
194 err_printf(m, "%s [%d]:\n", name, count);
195
196 while (count--) {
197 err_printf(m, " %08x %8u %02x %02x %x %x",
198 err->gtt_offset,
199 err->size,
200 err->read_domains,
201 err->write_domain,
202 err->rseqno, err->wseqno);
203 err_puts(m, pin_flag(err->pinned));
204 err_puts(m, tiling_flag(err->tiling));
205 err_puts(m, dirty_flag(err->dirty));
206 err_puts(m, purgeable_flag(err->purgeable));
207 err_puts(m, err->ring != -1 ? " " : "");
208 err_puts(m, ring_str(err->ring));
209 err_puts(m, i915_cache_level_str(err->cache_level));
210
211 if (err->name)
212 err_printf(m, " (name: %d)", err->name);
213 if (err->fence_reg != I915_FENCE_REG_NONE)
214 err_printf(m, " (fence: %d)", err->fence_reg);
215
216 err_puts(m, "\n");
217 err++;
218 }
219 }
220
221 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
222 struct drm_device *dev,
223 struct drm_i915_error_state *error,
224 unsigned ring)
225 {
226 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
227 if (!error->ring[ring].valid)
228 return;
229
230 err_printf(m, "%s command stream:\n", ring_str(ring));
231 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
232 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
233 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
234 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
235 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
236 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
237 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
238 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
239 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
240
241 if (INTEL_INFO(dev)->gen >= 4)
242 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
243 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
244 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
245 if (INTEL_INFO(dev)->gen >= 6) {
246 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
247 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
248 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
249 error->semaphore_mboxes[ring][0],
250 error->semaphore_seqno[ring][0]);
251 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
252 error->semaphore_mboxes[ring][1],
253 error->semaphore_seqno[ring][1]);
254 if (HAS_VEBOX(dev)) {
255 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
256 error->semaphore_mboxes[ring][2],
257 error->semaphore_seqno[ring][2]);
258 }
259 }
260 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
261 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
262 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
263 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
264 }
265
266 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
267 {
268 va_list args;
269
270 va_start(args, f);
271 i915_error_vprintf(e, f, args);
272 va_end(args);
273 }
274
275 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
276 const struct i915_error_state_file_priv *error_priv)
277 {
278 struct drm_device *dev = error_priv->dev;
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 struct drm_i915_error_state *error = error_priv->error;
281 int i, j, page, offset, elt;
282
283 if (!error) {
284 err_printf(m, "no error state collected\n");
285 goto out;
286 }
287
288 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
289 error->time.tv_usec);
290 err_printf(m, "Kernel: " UTS_RELEASE "\n");
291 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
292 err_printf(m, "EIR: 0x%08x\n", error->eir);
293 err_printf(m, "IER: 0x%08x\n", error->ier);
294 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
295 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
296 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
297 err_printf(m, "CCID: 0x%08x\n", error->ccid);
298
299 for (i = 0; i < dev_priv->num_fence_regs; i++)
300 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
301
302 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
303 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
304 error->extra_instdone[i]);
305
306 if (INTEL_INFO(dev)->gen >= 6) {
307 err_printf(m, "ERROR: 0x%08x\n", error->error);
308 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
309 }
310
311 if (INTEL_INFO(dev)->gen == 7)
312 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
313
314 for (i = 0; i < ARRAY_SIZE(error->ring); i++)
315 i915_ring_error_state(m, dev, error, i);
316
317 if (error->active_bo)
318 print_error_buffers(m, "Active",
319 error->active_bo[0],
320 error->active_bo_count[0]);
321
322 if (error->pinned_bo)
323 print_error_buffers(m, "Pinned",
324 error->pinned_bo[0],
325 error->pinned_bo_count[0]);
326
327 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
328 struct drm_i915_error_object *obj;
329
330 if ((obj = error->ring[i].batchbuffer)) {
331 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
332 dev_priv->ring[i].name,
333 obj->gtt_offset);
334 offset = 0;
335 for (page = 0; page < obj->page_count; page++) {
336 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
337 err_printf(m, "%08x : %08x\n", offset,
338 obj->pages[page][elt]);
339 offset += 4;
340 }
341 }
342 }
343
344 if (error->ring[i].num_requests) {
345 err_printf(m, "%s --- %d requests\n",
346 dev_priv->ring[i].name,
347 error->ring[i].num_requests);
348 for (j = 0; j < error->ring[i].num_requests; j++) {
349 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
350 error->ring[i].requests[j].seqno,
351 error->ring[i].requests[j].jiffies,
352 error->ring[i].requests[j].tail);
353 }
354 }
355
356 if ((obj = error->ring[i].ringbuffer)) {
357 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
358 dev_priv->ring[i].name,
359 obj->gtt_offset);
360 offset = 0;
361 for (page = 0; page < obj->page_count; page++) {
362 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
363 err_printf(m, "%08x : %08x\n",
364 offset,
365 obj->pages[page][elt]);
366 offset += 4;
367 }
368 }
369 }
370
371 if ((obj = error->ring[i].ctx)) {
372 err_printf(m, "%s --- HW Context = 0x%08x\n",
373 dev_priv->ring[i].name,
374 obj->gtt_offset);
375 offset = 0;
376 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
377 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
378 offset,
379 obj->pages[0][elt],
380 obj->pages[0][elt+1],
381 obj->pages[0][elt+2],
382 obj->pages[0][elt+3]);
383 offset += 16;
384 }
385 }
386 }
387
388 if (error->overlay)
389 intel_overlay_print_error_state(m, error->overlay);
390
391 if (error->display)
392 intel_display_print_error_state(m, dev, error->display);
393
394 out:
395 if (m->bytes == 0 && m->err)
396 return m->err;
397
398 return 0;
399 }
400
401 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
402 size_t count, loff_t pos)
403 {
404 memset(ebuf, 0, sizeof(*ebuf));
405
406 /* We need to have enough room to store any i915_error_state printf
407 * so that we can move it to start position.
408 */
409 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
410 ebuf->buf = kmalloc(ebuf->size,
411 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
412
413 if (ebuf->buf == NULL) {
414 ebuf->size = PAGE_SIZE;
415 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
416 }
417
418 if (ebuf->buf == NULL) {
419 ebuf->size = 128;
420 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
421 }
422
423 if (ebuf->buf == NULL)
424 return -ENOMEM;
425
426 ebuf->start = pos;
427
428 return 0;
429 }
430
431 static void i915_error_object_free(struct drm_i915_error_object *obj)
432 {
433 int page;
434
435 if (obj == NULL)
436 return;
437
438 for (page = 0; page < obj->page_count; page++)
439 kfree(obj->pages[page]);
440
441 kfree(obj);
442 }
443
444 static void i915_error_state_free(struct kref *error_ref)
445 {
446 struct drm_i915_error_state *error = container_of(error_ref,
447 typeof(*error), ref);
448 int i;
449
450 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
451 i915_error_object_free(error->ring[i].batchbuffer);
452 i915_error_object_free(error->ring[i].ringbuffer);
453 i915_error_object_free(error->ring[i].ctx);
454 kfree(error->ring[i].requests);
455 }
456
457 kfree(error->active_bo);
458 kfree(error->overlay);
459 kfree(error->display);
460 kfree(error);
461 }
462
463 static struct drm_i915_error_object *
464 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
465 struct drm_i915_gem_object *src,
466 const int num_pages)
467 {
468 struct drm_i915_error_object *dst;
469 int i;
470 u32 reloc_offset;
471
472 if (src == NULL || src->pages == NULL)
473 return NULL;
474
475 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
476 if (dst == NULL)
477 return NULL;
478
479 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
480 for (i = 0; i < num_pages; i++) {
481 unsigned long flags;
482 void *d;
483
484 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
485 if (d == NULL)
486 goto unwind;
487
488 local_irq_save(flags);
489 if (reloc_offset < dev_priv->gtt.mappable_end &&
490 src->has_global_gtt_mapping) {
491 void __iomem *s;
492
493 /* Simply ignore tiling or any overlapping fence.
494 * It's part of the error state, and this hopefully
495 * captures what the GPU read.
496 */
497
498 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
499 reloc_offset);
500 memcpy_fromio(d, s, PAGE_SIZE);
501 io_mapping_unmap_atomic(s);
502 } else if (src->stolen) {
503 unsigned long offset;
504
505 offset = dev_priv->mm.stolen_base;
506 offset += src->stolen->start;
507 offset += i << PAGE_SHIFT;
508
509 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
510 } else {
511 struct page *page;
512 void *s;
513
514 page = i915_gem_object_get_page(src, i);
515
516 drm_clflush_pages(&page, 1);
517
518 s = kmap_atomic(page);
519 memcpy(d, s, PAGE_SIZE);
520 kunmap_atomic(s);
521
522 drm_clflush_pages(&page, 1);
523 }
524 local_irq_restore(flags);
525
526 dst->pages[i] = d;
527
528 reloc_offset += PAGE_SIZE;
529 }
530 dst->page_count = num_pages;
531
532 return dst;
533
534 unwind:
535 while (i--)
536 kfree(dst->pages[i]);
537 kfree(dst);
538 return NULL;
539 }
540 #define i915_error_object_create(dev_priv, src) \
541 i915_error_object_create_sized((dev_priv), (src), \
542 (src)->base.size>>PAGE_SHIFT)
543
544 static void capture_bo(struct drm_i915_error_buffer *err,
545 struct drm_i915_gem_object *obj)
546 {
547 err->size = obj->base.size;
548 err->name = obj->base.name;
549 err->rseqno = obj->last_read_seqno;
550 err->wseqno = obj->last_write_seqno;
551 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
552 err->read_domains = obj->base.read_domains;
553 err->write_domain = obj->base.write_domain;
554 err->fence_reg = obj->fence_reg;
555 err->pinned = 0;
556 if (obj->pin_count > 0)
557 err->pinned = 1;
558 if (obj->user_pin_count > 0)
559 err->pinned = -1;
560 err->tiling = obj->tiling_mode;
561 err->dirty = obj->dirty;
562 err->purgeable = obj->madv != I915_MADV_WILLNEED;
563 err->ring = obj->ring ? obj->ring->id : -1;
564 err->cache_level = obj->cache_level;
565 }
566
567 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
568 int count, struct list_head *head)
569 {
570 struct i915_vma *vma;
571 int i = 0;
572
573 list_for_each_entry(vma, head, mm_list) {
574 capture_bo(err++, vma->obj);
575 if (++i == count)
576 break;
577 }
578
579 return i;
580 }
581
582 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
583 int count, struct list_head *head)
584 {
585 struct drm_i915_gem_object *obj;
586 int i = 0;
587
588 list_for_each_entry(obj, head, global_list) {
589 if (obj->pin_count == 0)
590 continue;
591
592 capture_bo(err++, obj);
593 if (++i == count)
594 break;
595 }
596
597 return i;
598 }
599
600 static void i915_gem_record_fences(struct drm_device *dev,
601 struct drm_i915_error_state *error)
602 {
603 struct drm_i915_private *dev_priv = dev->dev_private;
604 int i;
605
606 /* Fences */
607 switch (INTEL_INFO(dev)->gen) {
608 case 7:
609 case 6:
610 for (i = 0; i < dev_priv->num_fence_regs; i++)
611 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
612 break;
613 case 5:
614 case 4:
615 for (i = 0; i < 16; i++)
616 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
617 break;
618 case 3:
619 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
620 for (i = 0; i < 8; i++)
621 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
622 case 2:
623 for (i = 0; i < 8; i++)
624 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
625 break;
626
627 default:
628 BUG();
629 }
630 }
631
632 static struct drm_i915_error_object *
633 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
634 struct intel_ring_buffer *ring)
635 {
636 struct i915_address_space *vm;
637 struct i915_vma *vma;
638 struct drm_i915_gem_object *obj;
639 u32 seqno;
640
641 if (!ring->get_seqno)
642 return NULL;
643
644 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
645 u32 acthd = I915_READ(ACTHD);
646
647 if (WARN_ON(ring->id != RCS))
648 return NULL;
649
650 obj = ring->scratch.obj;
651 if (obj != NULL &&
652 acthd >= i915_gem_obj_ggtt_offset(obj) &&
653 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
654 return i915_error_object_create(dev_priv, obj);
655 }
656
657 seqno = ring->get_seqno(ring, false);
658 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
659 list_for_each_entry(vma, &vm->active_list, mm_list) {
660 obj = vma->obj;
661 if (obj->ring != ring)
662 continue;
663
664 if (i915_seqno_passed(seqno, obj->last_read_seqno))
665 continue;
666
667 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
668 continue;
669
670 /* We need to copy these to an anonymous buffer as the simplest
671 * method to avoid being overwritten by userspace.
672 */
673 return i915_error_object_create(dev_priv, obj);
674 }
675 }
676
677 return NULL;
678 }
679
680 static void i915_record_ring_state(struct drm_device *dev,
681 struct drm_i915_error_state *error,
682 struct intel_ring_buffer *ring)
683 {
684 struct drm_i915_private *dev_priv = dev->dev_private;
685
686 if (INTEL_INFO(dev)->gen >= 6) {
687 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
688 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
689 error->semaphore_mboxes[ring->id][0]
690 = I915_READ(RING_SYNC_0(ring->mmio_base));
691 error->semaphore_mboxes[ring->id][1]
692 = I915_READ(RING_SYNC_1(ring->mmio_base));
693 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
694 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
695 }
696
697 if (HAS_VEBOX(dev)) {
698 error->semaphore_mboxes[ring->id][2] =
699 I915_READ(RING_SYNC_2(ring->mmio_base));
700 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
701 }
702
703 if (INTEL_INFO(dev)->gen >= 4) {
704 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
705 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
706 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
707 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
708 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
709 if (ring->id == RCS)
710 error->bbaddr = I915_READ64(BB_ADDR);
711 } else {
712 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
713 error->ipeir[ring->id] = I915_READ(IPEIR);
714 error->ipehr[ring->id] = I915_READ(IPEHR);
715 error->instdone[ring->id] = I915_READ(INSTDONE);
716 }
717
718 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
719 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
720 error->seqno[ring->id] = ring->get_seqno(ring, false);
721 error->acthd[ring->id] = intel_ring_get_active_head(ring);
722 error->head[ring->id] = I915_READ_HEAD(ring);
723 error->tail[ring->id] = I915_READ_TAIL(ring);
724 error->ctl[ring->id] = I915_READ_CTL(ring);
725
726 error->cpu_ring_head[ring->id] = ring->head;
727 error->cpu_ring_tail[ring->id] = ring->tail;
728 }
729
730
731 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
732 struct drm_i915_error_state *error,
733 struct drm_i915_error_ring *ering)
734 {
735 struct drm_i915_private *dev_priv = ring->dev->dev_private;
736 struct drm_i915_gem_object *obj;
737
738 /* Currently render ring is the only HW context user */
739 if (ring->id != RCS || !error->ccid)
740 return;
741
742 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
743 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
744 ering->ctx = i915_error_object_create_sized(dev_priv,
745 obj, 1);
746 break;
747 }
748 }
749 }
750
751 static void i915_gem_record_rings(struct drm_device *dev,
752 struct drm_i915_error_state *error)
753 {
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 struct drm_i915_gem_request *request;
756 int i, count;
757
758 for (i = 0; i < I915_NUM_RINGS; i++) {
759 struct intel_ring_buffer *ring = &dev_priv->ring[i];
760
761 if (ring->dev == NULL)
762 continue;
763
764 error->ring[i].valid = true;
765
766 i915_record_ring_state(dev, error, ring);
767
768 error->ring[i].batchbuffer =
769 i915_error_first_batchbuffer(dev_priv, ring);
770
771 error->ring[i].ringbuffer =
772 i915_error_object_create(dev_priv, ring->obj);
773
774
775 i915_gem_record_active_context(ring, error, &error->ring[i]);
776
777 count = 0;
778 list_for_each_entry(request, &ring->request_list, list)
779 count++;
780
781 error->ring[i].num_requests = count;
782 error->ring[i].requests =
783 kmalloc(count*sizeof(struct drm_i915_error_request),
784 GFP_ATOMIC);
785 if (error->ring[i].requests == NULL) {
786 error->ring[i].num_requests = 0;
787 continue;
788 }
789
790 count = 0;
791 list_for_each_entry(request, &ring->request_list, list) {
792 struct drm_i915_error_request *erq;
793
794 erq = &error->ring[i].requests[count++];
795 erq->seqno = request->seqno;
796 erq->jiffies = request->emitted_jiffies;
797 erq->tail = request->tail;
798 }
799 }
800 }
801
802 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
803 * VM.
804 */
805 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
806 struct drm_i915_error_state *error,
807 struct i915_address_space *vm,
808 const int ndx)
809 {
810 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
811 struct drm_i915_gem_object *obj;
812 struct i915_vma *vma;
813 int i;
814
815 i = 0;
816 list_for_each_entry(vma, &vm->active_list, mm_list)
817 i++;
818 error->active_bo_count[ndx] = i;
819 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
820 if (obj->pin_count)
821 i++;
822 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
823
824 if (i) {
825 active_bo = kmalloc(sizeof(*active_bo)*i, GFP_ATOMIC);
826 if (active_bo)
827 pinned_bo = active_bo + error->active_bo_count[ndx];
828 }
829
830 if (active_bo)
831 error->active_bo_count[ndx] =
832 capture_active_bo(active_bo,
833 error->active_bo_count[ndx],
834 &vm->active_list);
835
836 if (pinned_bo)
837 error->pinned_bo_count[ndx] =
838 capture_pinned_bo(pinned_bo,
839 error->pinned_bo_count[ndx],
840 &dev_priv->mm.bound_list);
841 error->active_bo[ndx] = active_bo;
842 error->pinned_bo[ndx] = pinned_bo;
843 }
844
845 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
846 struct drm_i915_error_state *error)
847 {
848 struct i915_address_space *vm;
849 int cnt = 0, i = 0;
850
851 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
852 cnt++;
853
854 if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
855 cnt = 1;
856
857 vm = &dev_priv->gtt.base;
858
859 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
860 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
861 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
862 GFP_ATOMIC);
863 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
864 GFP_ATOMIC);
865
866 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
867 i915_gem_capture_vm(dev_priv, error, vm, i++);
868 }
869
870 /**
871 * i915_capture_error_state - capture an error record for later analysis
872 * @dev: drm device
873 *
874 * Should be called when an error is detected (either a hang or an error
875 * interrupt) to capture error state from the time of the error. Fills
876 * out a structure which becomes available in debugfs for user level tools
877 * to pick up.
878 */
879 void i915_capture_error_state(struct drm_device *dev)
880 {
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct drm_i915_error_state *error;
883 unsigned long flags;
884 int pipe;
885
886 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
887 error = dev_priv->gpu_error.first_error;
888 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
889 if (error)
890 return;
891
892 /* Account for pipe specific data like PIPE*STAT */
893 error = kzalloc(sizeof(*error), GFP_ATOMIC);
894 if (!error) {
895 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
896 return;
897 }
898
899 DRM_INFO("capturing error event; look for more information in "
900 "/sys/class/drm/card%d/error\n", dev->primary->index);
901
902 kref_init(&error->ref);
903 error->eir = I915_READ(EIR);
904 error->pgtbl_er = I915_READ(PGTBL_ER);
905 if (HAS_HW_CONTEXTS(dev))
906 error->ccid = I915_READ(CCID);
907
908 if (HAS_PCH_SPLIT(dev))
909 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
910 else if (IS_VALLEYVIEW(dev))
911 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
912 else if (IS_GEN2(dev))
913 error->ier = I915_READ16(IER);
914 else
915 error->ier = I915_READ(IER);
916
917 if (INTEL_INFO(dev)->gen >= 6)
918 error->derrmr = I915_READ(DERRMR);
919
920 if (IS_VALLEYVIEW(dev))
921 error->forcewake = I915_READ(FORCEWAKE_VLV);
922 else if (INTEL_INFO(dev)->gen >= 7)
923 error->forcewake = I915_READ(FORCEWAKE_MT);
924 else if (INTEL_INFO(dev)->gen == 6)
925 error->forcewake = I915_READ(FORCEWAKE);
926
927 if (!HAS_PCH_SPLIT(dev))
928 for_each_pipe(pipe)
929 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
930
931 if (INTEL_INFO(dev)->gen >= 6) {
932 error->error = I915_READ(ERROR_GEN6);
933 error->done_reg = I915_READ(DONE_REG);
934 }
935
936 if (INTEL_INFO(dev)->gen == 7)
937 error->err_int = I915_READ(GEN7_ERR_INT);
938
939 i915_get_extra_instdone(dev, error->extra_instdone);
940
941 i915_gem_capture_buffers(dev_priv, error);
942 i915_gem_record_fences(dev, error);
943 i915_gem_record_rings(dev, error);
944
945 do_gettimeofday(&error->time);
946
947 error->overlay = intel_overlay_capture_error_state(dev);
948 error->display = intel_display_capture_error_state(dev);
949
950 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
951 if (dev_priv->gpu_error.first_error == NULL) {
952 dev_priv->gpu_error.first_error = error;
953 error = NULL;
954 }
955 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
956
957 if (error)
958 i915_error_state_free(&error->ref);
959 }
960
961 void i915_error_state_get(struct drm_device *dev,
962 struct i915_error_state_file_priv *error_priv)
963 {
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 unsigned long flags;
966
967 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
968 error_priv->error = dev_priv->gpu_error.first_error;
969 if (error_priv->error)
970 kref_get(&error_priv->error->ref);
971 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
972
973 }
974
975 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
976 {
977 if (error_priv->error)
978 kref_put(&error_priv->error->ref, i915_error_state_free);
979 }
980
981 void i915_destroy_error_state(struct drm_device *dev)
982 {
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct drm_i915_error_state *error;
985 unsigned long flags;
986
987 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
988 error = dev_priv->gpu_error.first_error;
989 dev_priv->gpu_error.first_error = NULL;
990 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
991
992 if (error)
993 kref_put(&error->ref, i915_error_state_free);
994 }
995
996 const char *i915_cache_level_str(int type)
997 {
998 switch (type) {
999 case I915_CACHE_NONE: return " uncached";
1000 case I915_CACHE_LLC: return " snooped or LLC";
1001 case I915_CACHE_L3_LLC: return " L3+LLC";
1002 default: return "";
1003 }
1004 }
1005
1006 /* NB: please notice the memset */
1007 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1008 {
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1011
1012 switch (INTEL_INFO(dev)->gen) {
1013 case 2:
1014 case 3:
1015 instdone[0] = I915_READ(INSTDONE);
1016 break;
1017 case 4:
1018 case 5:
1019 case 6:
1020 instdone[0] = I915_READ(INSTDONE_I965);
1021 instdone[1] = I915_READ(INSTDONE1);
1022 break;
1023 default:
1024 WARN_ONCE(1, "Unsupported platform\n");
1025 case 7:
1026 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1027 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1028 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1029 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1030 break;
1031 }
1032 }
Linux with added FPC-III support