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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob837cc6cd747229c6f25552ecaf36482b63d4ba58
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
57 typedef struct {
58 int min, max;
59 } intel_range_t;
60
61 typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64 } intel_p2_t;
65
66 typedef struct intel_limit intel_limit_t;
67 struct intel_limit {
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
70 };
71
72 /* FDI */
73 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
75 int
76 intel_pch_rawclk(struct drm_device *dev)
77 {
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83 }
84
85 static inline u32 /* units of 100MHz */
86 intel_fdi_link_freq(struct drm_device *dev)
87 {
88 if (IS_GEN5(dev)) {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 } else
92 return 27;
93 }
94
95 static const intel_limit_t intel_limits_i8xx_dac = {
96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
106 };
107
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
119 };
120
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
132 };
133
134 static const intel_limit_t intel_limits_i9xx_sdvo = {
135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
145 };
146
147 static const intel_limit_t intel_limits_i9xx_lvds = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
158 };
159
160
161 static const intel_limit_t intel_limits_g4x_sdvo = {
162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
171 .p2_slow = 10,
172 .p2_fast = 10
173 },
174 };
175
176 static const intel_limit_t intel_limits_g4x_hdmi = {
177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
187 };
188
189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
200 },
201 };
202
203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
214 },
215 };
216
217 static const intel_limit_t intel_limits_pineview_sdvo = {
218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
220 /* Pineview's Ncounter is a ring counter */
221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
223 /* Pineview only has one combined m divider, which we treat as m2. */
224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
230 };
231
232 static const intel_limit_t intel_limits_pineview_lvds = {
233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
243 };
244
245 /* Ironlake / Sandybridge
246 *
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
249 */
250 static const intel_limit_t intel_limits_ironlake_dac = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
261 };
262
263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
274 };
275
276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
287 };
288
289 /* LVDS 100mhz refclk limits. */
290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
298 .p1 = { .min = 2, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
301 };
302
303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
311 .p1 = { .min = 2, .max = 6 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
314 };
315
316 static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
324 .p1 = { .min = 1, .max = 3 },
325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
327 };
328
329 static const intel_limit_t intel_limits_vlv_hdmi = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
340 };
341
342 static const intel_limit_t intel_limits_vlv_dp = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 },
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 };
354
355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 int refclk)
357 {
358 struct drm_device *dev = crtc->dev;
359 const intel_limit_t *limit;
360
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
362 if (intel_is_dual_link_lvds(dev)) {
363 if (refclk == 100000)
364 limit = &intel_limits_ironlake_dual_lvds_100m;
365 else
366 limit = &intel_limits_ironlake_dual_lvds;
367 } else {
368 if (refclk == 100000)
369 limit = &intel_limits_ironlake_single_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_single_lvds;
372 }
373 } else
374 limit = &intel_limits_ironlake_dac;
375
376 return limit;
377 }
378
379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
380 {
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
385 if (intel_is_dual_link_lvds(dev))
386 limit = &intel_limits_g4x_dual_channel_lvds;
387 else
388 limit = &intel_limits_g4x_single_channel_lvds;
389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
391 limit = &intel_limits_g4x_hdmi;
392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
393 limit = &intel_limits_g4x_sdvo;
394 } else /* The option is for other outputs */
395 limit = &intel_limits_i9xx_sdvo;
396
397 return limit;
398 }
399
400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
401 {
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
404
405 if (HAS_PCH_SPLIT(dev))
406 limit = intel_ironlake_limit(crtc, refclk);
407 else if (IS_G4X(dev)) {
408 limit = intel_g4x_limit(crtc);
409 } else if (IS_PINEVIEW(dev)) {
410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
411 limit = &intel_limits_pineview_lvds;
412 else
413 limit = &intel_limits_pineview_sdvo;
414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
419 else
420 limit = &intel_limits_vlv_dp;
421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_i8xx_lvds;
429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
430 limit = &intel_limits_i8xx_dvo;
431 else
432 limit = &intel_limits_i8xx_dac;
433 }
434 return limit;
435 }
436
437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
438 static void pineview_clock(int refclk, intel_clock_t *clock)
439 {
440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444 }
445
446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447 {
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449 }
450
451 static void i9xx_clock(int refclk, intel_clock_t *clock)
452 {
453 clock->m = i9xx_dpll_compute_m(clock);
454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457 }
458
459 /**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
463 {
464 struct drm_device *dev = crtc->dev;
465 struct intel_encoder *encoder;
466
467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
469 return true;
470
471 return false;
472 }
473
474 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
475 /**
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
478 */
479
480 static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
483 {
484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
485 INTELPllInvalid("p1 out of range\n");
486 if (clock->p < limit->p.min || limit->p.max < clock->p)
487 INTELPllInvalid("p out of range\n");
488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
489 INTELPllInvalid("m2 out of range\n");
490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
491 INTELPllInvalid("m1 out of range\n");
492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
493 INTELPllInvalid("m1 <= m2\n");
494 if (clock->m < limit->m.min || limit->m.max < clock->m)
495 INTELPllInvalid("m out of range\n");
496 if (clock->n < limit->n.min || limit->n.max < clock->n)
497 INTELPllInvalid("n out of range\n");
498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
499 INTELPllInvalid("vco out of range\n");
500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
502 */
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
504 INTELPllInvalid("dot out of range\n");
505
506 return true;
507 }
508
509 static bool
510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
513 {
514 struct drm_device *dev = crtc->dev;
515 intel_clock_t clock;
516 int err = target;
517
518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
519 /*
520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
523 */
524 if (intel_is_dual_link_lvds(dev))
525 clock.p2 = limit->p2.p2_fast;
526 else
527 clock.p2 = limit->p2.p2_slow;
528 } else {
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
531 else
532 clock.p2 = limit->p2.p2_fast;
533 }
534
535 memset(best_clock, 0, sizeof(*best_clock));
536
537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
538 clock.m1++) {
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
541 if (clock.m2 >= clock.m1)
542 break;
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
547 int this_err;
548
549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
551 &clock))
552 continue;
553 if (match_clock &&
554 clock.p != match_clock->p)
555 continue;
556
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
559 *best_clock = clock;
560 err = this_err;
561 }
562 }
563 }
564 }
565 }
566
567 return (err != target);
568 }
569
570 static bool
571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
574 {
575 struct drm_device *dev = crtc->dev;
576 intel_clock_t clock;
577 int err = target;
578
579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
580 /*
581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
584 */
585 if (intel_is_dual_link_lvds(dev))
586 clock.p2 = limit->p2.p2_fast;
587 else
588 clock.p2 = limit->p2.p2_slow;
589 } else {
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
592 else
593 clock.p2 = limit->p2.p2_fast;
594 }
595
596 memset(best_clock, 0, sizeof(*best_clock));
597
598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
599 clock.m1++) {
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
606 int this_err;
607
608 pineview_clock(refclk, &clock);
609 if (!intel_PLL_is_valid(dev, limit,
610 &clock))
611 continue;
612 if (match_clock &&
613 clock.p != match_clock->p)
614 continue;
615
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
618 *best_clock = clock;
619 err = this_err;
620 }
621 }
622 }
623 }
624 }
625
626 return (err != target);
627 }
628
629 static bool
630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
633 {
634 struct drm_device *dev = crtc->dev;
635 intel_clock_t clock;
636 int max_n;
637 bool found;
638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
640 found = false;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (intel_is_dual_link_lvds(dev))
644 clock.p2 = limit->p2.p2_fast;
645 else
646 clock.p2 = limit->p2.p2_slow;
647 } else {
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
650 else
651 clock.p2 = limit->p2.p2_fast;
652 }
653
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
656 /* based on hardware requirement, prefer smaller n to precision */
657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
658 /* based on hardware requirement, prefere larger m1,m2 */
659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
665 int this_err;
666
667 i9xx_clock(refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
670 continue;
671
672 this_err = abs(clock.dot - target);
673 if (this_err < err_most) {
674 *best_clock = clock;
675 err_most = this_err;
676 max_n = clock.n;
677 found = true;
678 }
679 }
680 }
681 }
682 }
683 return found;
684 }
685
686 static bool
687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
690 {
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
692 u32 m, n, fastclk;
693 u32 updrate, minupdate, p;
694 unsigned long bestppm, ppm, absppm;
695 int dotclk, flag;
696
697 flag = 0;
698 dotclk = target * 1000;
699 bestppm = 1000000;
700 ppm = absppm = 0;
701 fastclk = dotclk / (2*100);
702 updrate = 0;
703 minupdate = 19200;
704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
706
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
712 if (p2 > 10)
713 p2 = p2 - 1;
714 p = p1 * p2;
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
719 m = m1 * m2;
720 vco = updrate * m;
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
725 bestppm = 0;
726 flag = 1;
727 }
728 if (absppm < bestppm - 10) {
729 bestppm = absppm;
730 flag = 1;
731 }
732 if (flag) {
733 bestn = n;
734 bestm1 = m1;
735 bestm2 = m2;
736 bestp1 = p1;
737 bestp2 = p2;
738 flag = 0;
739 }
740 }
741 }
742 }
743 }
744 }
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
750
751 return true;
752 }
753
754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756 {
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
760 return intel_crtc->config.cpu_transcoder;
761 }
762
763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764 {
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772 }
773
774 /**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
783 {
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 int pipestat_reg = PIPESTAT(pipe);
786
787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
808 /* Wait for vblank interrupt bit to set */
809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
812 DRM_DEBUG_KMS("vblank wait timed out\n");
813 }
814
815 /*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
830 *
831 */
832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
833 {
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
837
838 if (INTEL_INFO(dev)->gen >= 4) {
839 int reg = PIPECONF(cpu_transcoder);
840
841 /* Wait for the Pipe State to go off */
842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
844 WARN(1, "pipe_off wait timed out\n");
845 } else {
846 u32 last_line, line_mask;
847 int reg = PIPEDSL(pipe);
848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
855 /* Wait for the display line to settle */
856 do {
857 last_line = I915_READ(reg) & line_mask;
858 mdelay(5);
859 } while (((I915_READ(reg) & line_mask) != last_line) &&
860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
862 WARN(1, "pipe_off wait timed out\n");
863 }
864 }
865
866 /*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875 {
876 u32 bit;
877
878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
906 }
907
908 return I915_READ(SDEISR) & bit;
909 }
910
911 static const char *state_string(bool enabled)
912 {
913 return enabled ? "on" : "off";
914 }
915
916 /* Only for pre-ILK configs */
917 void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
919 {
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930 }
931
932 struct intel_shared_dpll *
933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934 {
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
937 if (crtc->config.shared_dpll < 0)
938 return NULL;
939
940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
941 }
942
943 /* For ILK+ */
944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
947 {
948 bool cur_state;
949 struct intel_dpll_hw_state hw_state;
950
951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
956 if (WARN (!pll,
957 "asserting DPLL %s with no DPLL\n", state_string(state)))
958 return;
959
960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
961 WARN(cur_state != state,
962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
964 }
965
966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968 {
969 int reg;
970 u32 val;
971 bool cur_state;
972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
974
975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
978 val = I915_READ(reg);
979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988 }
989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994 {
995 int reg;
996 u32 val;
997 bool cur_state;
998
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011 {
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020 if (HAS_DDI(dev_priv->dev))
1021 return;
1022
1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
1030 {
1031 int reg;
1032 u32 val;
1033 bool cur_state;
1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041 }
1042
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045 {
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
1049 bool locked = true;
1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
1069 pipe_name(pipe));
1070 }
1071
1072 void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1074 {
1075 int reg;
1076 u32 val;
1077 bool cur_state;
1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 pipe);
1080
1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083 state = true;
1084
1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1087 cur_state = false;
1088 } else {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1092 }
1093
1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
1096 pipe_name(pipe), state_string(state), state_string(cur_state));
1097 }
1098
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
1101 {
1102 int reg;
1103 u32 val;
1104 bool cur_state;
1105
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
1112 }
1113
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118 enum pipe pipe)
1119 {
1120 struct drm_device *dev = dev_priv->dev;
1121 int reg, i;
1122 u32 val;
1123 int cur_pipe;
1124
1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1131 plane_name(pipe));
1132 return;
1133 }
1134
1135 /* Need to check both planes against the pipe */
1136 for_each_pipe(i) {
1137 reg = DSPCNTR(i);
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
1144 }
1145 }
1146
1147 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148 enum pipe pipe)
1149 {
1150 struct drm_device *dev = dev_priv->dev;
1151 int reg, i;
1152 u32 val;
1153
1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1161 }
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1163 reg = SPRCTL(pipe);
1164 val = I915_READ(reg);
1165 WARN((val & SPRITE_ENABLE),
1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
1170 val = I915_READ(reg);
1171 WARN((val & DVS_ENABLE),
1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(pipe), pipe_name(pipe));
1174 }
1175 }
1176
1177 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178 {
1179 u32 val;
1180 bool enabled;
1181
1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184 return;
1185 }
1186
1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191 }
1192
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195 {
1196 int reg;
1197 u32 val;
1198 bool enabled;
1199
1200 reg = PCH_TRANSCONF(pipe);
1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
1203 WARN(enabled,
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205 pipe_name(pipe));
1206 }
1207
1208 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
1210 {
1211 if ((val & DP_PORT_EN) == 0)
1212 return false;
1213
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218 return false;
1219 } else {
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221 return false;
1222 }
1223 return true;
1224 }
1225
1226 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1228 {
1229 if ((val & SDVO_ENABLE) == 0)
1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1234 return false;
1235 } else {
1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1237 return false;
1238 }
1239 return true;
1240 }
1241
1242 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244 {
1245 if ((val & LVDS_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250 return false;
1251 } else {
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253 return false;
1254 }
1255 return true;
1256 }
1257
1258 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260 {
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1262 return false;
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265 return false;
1266 } else {
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268 return false;
1269 }
1270 return true;
1271 }
1272
1273 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, int reg, u32 port_sel)
1275 {
1276 u32 val = I915_READ(reg);
1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279 reg, pipe_name(pipe));
1280
1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
1283 "IBX PCH dp port still using transcoder B\n");
1284 }
1285
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1288 {
1289 u32 val = I915_READ(reg);
1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292 reg, pipe_name(pipe));
1293
1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295 && (val & SDVO_PIPE_B_SELECT),
1296 "IBX PCH hdmi port still using transcoder B\n");
1297 }
1298
1299 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301 {
1302 int reg;
1303 u32 val;
1304
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1308
1309 reg = PCH_ADPA;
1310 val = I915_READ(reg);
1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
1313 pipe_name(pipe));
1314
1315 reg = PCH_LVDS;
1316 val = I915_READ(reg);
1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1319 pipe_name(pipe));
1320
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1324 }
1325
1326 static void vlv_enable_pll(struct intel_crtc *crtc)
1327 {
1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
1332
1333 assert_pipe_disabled(dev_priv, crtc->pipe);
1334
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340 assert_panel_unlocked(dev_priv, crtc->pipe);
1341
1342 I915_WRITE(reg, dpll);
1343 POSTING_READ(reg);
1344 udelay(150);
1345
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
1351
1352 /* We do this three times for luck */
1353 I915_WRITE(reg, dpll);
1354 POSTING_READ(reg);
1355 udelay(150); /* wait for warmup */
1356 I915_WRITE(reg, dpll);
1357 POSTING_READ(reg);
1358 udelay(150); /* wait for warmup */
1359 I915_WRITE(reg, dpll);
1360 POSTING_READ(reg);
1361 udelay(150); /* wait for warmup */
1362 }
1363
1364 static void i9xx_enable_pll(struct intel_crtc *crtc)
1365 {
1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
1370
1371 assert_pipe_disabled(dev_priv, crtc->pipe);
1372
1373 /* No really, not for ILK+ */
1374 BUG_ON(dev_priv->info->gen >= 5);
1375
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
1379
1380 I915_WRITE(reg, dpll);
1381
1382 /* Wait for the clocks to stabilize. */
1383 POSTING_READ(reg);
1384 udelay(150);
1385
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1389 } else {
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1392 *
1393 * So write it again.
1394 */
1395 I915_WRITE(reg, dpll);
1396 }
1397
1398 /* We do this three times for luck */
1399 I915_WRITE(reg, dpll);
1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg, dpll);
1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg, dpll);
1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408 }
1409
1410 /**
1411 * i9xx_disable_pll - disable a PLL
1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1414 *
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1416 *
1417 * Note! This is for pre-ILK only.
1418 */
1419 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1420 {
1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423 return;
1424
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1427
1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
1430 }
1431
1432 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1433 {
1434 u32 val = 0;
1435
1436 /* Make sure the pipe isn't still relying on us */
1437 assert_pipe_disabled(dev_priv, pipe);
1438
1439 /* Leave integrated clock source enabled */
1440 if (pipe == PIPE_B)
1441 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1442 I915_WRITE(DPLL(pipe), val);
1443 POSTING_READ(DPLL(pipe));
1444 }
1445
1446 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1447 {
1448 u32 port_mask;
1449
1450 if (!port)
1451 port_mask = DPLL_PORTB_READY_MASK;
1452 else
1453 port_mask = DPLL_PORTC_READY_MASK;
1454
1455 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1456 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1457 'B' + port, I915_READ(DPLL(0)));
1458 }
1459
1460 /**
1461 * ironlake_enable_shared_dpll - enable PCH PLL
1462 * @dev_priv: i915 private structure
1463 * @pipe: pipe PLL to enable
1464 *
1465 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1466 * drives the transcoder clock.
1467 */
1468 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1469 {
1470 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1471 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1472
1473 /* PCH PLLs only available on ILK, SNB and IVB */
1474 BUG_ON(dev_priv->info->gen < 5);
1475 if (WARN_ON(pll == NULL))
1476 return;
1477
1478 if (WARN_ON(pll->refcount == 0))
1479 return;
1480
1481 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1482 pll->name, pll->active, pll->on,
1483 crtc->base.base.id);
1484
1485 if (pll->active++) {
1486 WARN_ON(!pll->on);
1487 assert_shared_dpll_enabled(dev_priv, pll);
1488 return;
1489 }
1490 WARN_ON(pll->on);
1491
1492 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1493 pll->enable(dev_priv, pll);
1494 pll->on = true;
1495 }
1496
1497 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1498 {
1499 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1500 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1501
1502 /* PCH only available on ILK+ */
1503 BUG_ON(dev_priv->info->gen < 5);
1504 if (WARN_ON(pll == NULL))
1505 return;
1506
1507 if (WARN_ON(pll->refcount == 0))
1508 return;
1509
1510 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1511 pll->name, pll->active, pll->on,
1512 crtc->base.base.id);
1513
1514 if (WARN_ON(pll->active == 0)) {
1515 assert_shared_dpll_disabled(dev_priv, pll);
1516 return;
1517 }
1518
1519 assert_shared_dpll_enabled(dev_priv, pll);
1520 WARN_ON(!pll->on);
1521 if (--pll->active)
1522 return;
1523
1524 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1525 pll->disable(dev_priv, pll);
1526 pll->on = false;
1527 }
1528
1529 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1530 enum pipe pipe)
1531 {
1532 struct drm_device *dev = dev_priv->dev;
1533 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1535 uint32_t reg, val, pipeconf_val;
1536
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1539
1540 /* Make sure PCH DPLL is enabled */
1541 assert_shared_dpll_enabled(dev_priv,
1542 intel_crtc_to_shared_dpll(intel_crtc));
1543
1544 /* FDI must be feeding us bits for PCH ports */
1545 assert_fdi_tx_enabled(dev_priv, pipe);
1546 assert_fdi_rx_enabled(dev_priv, pipe);
1547
1548 if (HAS_PCH_CPT(dev)) {
1549 /* Workaround: Set the timing override bit before enabling the
1550 * pch transcoder. */
1551 reg = TRANS_CHICKEN2(pipe);
1552 val = I915_READ(reg);
1553 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1554 I915_WRITE(reg, val);
1555 }
1556
1557 reg = PCH_TRANSCONF(pipe);
1558 val = I915_READ(reg);
1559 pipeconf_val = I915_READ(PIPECONF(pipe));
1560
1561 if (HAS_PCH_IBX(dev_priv->dev)) {
1562 /*
1563 * make the BPC in transcoder be consistent with
1564 * that in pipeconf reg.
1565 */
1566 val &= ~PIPECONF_BPC_MASK;
1567 val |= pipeconf_val & PIPECONF_BPC_MASK;
1568 }
1569
1570 val &= ~TRANS_INTERLACE_MASK;
1571 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1572 if (HAS_PCH_IBX(dev_priv->dev) &&
1573 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1574 val |= TRANS_LEGACY_INTERLACED_ILK;
1575 else
1576 val |= TRANS_INTERLACED;
1577 else
1578 val |= TRANS_PROGRESSIVE;
1579
1580 I915_WRITE(reg, val | TRANS_ENABLE);
1581 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1582 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1583 }
1584
1585 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1586 enum transcoder cpu_transcoder)
1587 {
1588 u32 val, pipeconf_val;
1589
1590 /* PCH only available on ILK+ */
1591 BUG_ON(dev_priv->info->gen < 5);
1592
1593 /* FDI must be feeding us bits for PCH ports */
1594 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1595 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1596
1597 /* Workaround: set timing override bit. */
1598 val = I915_READ(_TRANSA_CHICKEN2);
1599 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1600 I915_WRITE(_TRANSA_CHICKEN2, val);
1601
1602 val = TRANS_ENABLE;
1603 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1604
1605 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1606 PIPECONF_INTERLACED_ILK)
1607 val |= TRANS_INTERLACED;
1608 else
1609 val |= TRANS_PROGRESSIVE;
1610
1611 I915_WRITE(LPT_TRANSCONF, val);
1612 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1613 DRM_ERROR("Failed to enable PCH transcoder\n");
1614 }
1615
1616 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1617 enum pipe pipe)
1618 {
1619 struct drm_device *dev = dev_priv->dev;
1620 uint32_t reg, val;
1621
1622 /* FDI relies on the transcoder */
1623 assert_fdi_tx_disabled(dev_priv, pipe);
1624 assert_fdi_rx_disabled(dev_priv, pipe);
1625
1626 /* Ports must be off as well */
1627 assert_pch_ports_disabled(dev_priv, pipe);
1628
1629 reg = PCH_TRANSCONF(pipe);
1630 val = I915_READ(reg);
1631 val &= ~TRANS_ENABLE;
1632 I915_WRITE(reg, val);
1633 /* wait for PCH transcoder off, transcoder state */
1634 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1635 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1636
1637 if (!HAS_PCH_IBX(dev)) {
1638 /* Workaround: Clear the timing override chicken bit again. */
1639 reg = TRANS_CHICKEN2(pipe);
1640 val = I915_READ(reg);
1641 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1642 I915_WRITE(reg, val);
1643 }
1644 }
1645
1646 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1647 {
1648 u32 val;
1649
1650 val = I915_READ(LPT_TRANSCONF);
1651 val &= ~TRANS_ENABLE;
1652 I915_WRITE(LPT_TRANSCONF, val);
1653 /* wait for PCH transcoder off, transcoder state */
1654 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1655 DRM_ERROR("Failed to disable PCH transcoder\n");
1656
1657 /* Workaround: clear timing override bit. */
1658 val = I915_READ(_TRANSA_CHICKEN2);
1659 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1660 I915_WRITE(_TRANSA_CHICKEN2, val);
1661 }
1662
1663 /**
1664 * intel_enable_pipe - enable a pipe, asserting requirements
1665 * @dev_priv: i915 private structure
1666 * @pipe: pipe to enable
1667 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1668 *
1669 * Enable @pipe, making sure that various hardware specific requirements
1670 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1671 *
1672 * @pipe should be %PIPE_A or %PIPE_B.
1673 *
1674 * Will wait until the pipe is actually running (i.e. first vblank) before
1675 * returning.
1676 */
1677 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1678 bool pch_port)
1679 {
1680 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1681 pipe);
1682 enum pipe pch_transcoder;
1683 int reg;
1684 u32 val;
1685
1686 assert_planes_disabled(dev_priv, pipe);
1687 assert_sprites_disabled(dev_priv, pipe);
1688
1689 if (HAS_PCH_LPT(dev_priv->dev))
1690 pch_transcoder = TRANSCODER_A;
1691 else
1692 pch_transcoder = pipe;
1693
1694 /*
1695 * A pipe without a PLL won't actually be able to drive bits from
1696 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1697 * need the check.
1698 */
1699 if (!HAS_PCH_SPLIT(dev_priv->dev))
1700 assert_pll_enabled(dev_priv, pipe);
1701 else {
1702 if (pch_port) {
1703 /* if driving the PCH, we need FDI enabled */
1704 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1705 assert_fdi_tx_pll_enabled(dev_priv,
1706 (enum pipe) cpu_transcoder);
1707 }
1708 /* FIXME: assert CPU port conditions for SNB+ */
1709 }
1710
1711 reg = PIPECONF(cpu_transcoder);
1712 val = I915_READ(reg);
1713 if (val & PIPECONF_ENABLE)
1714 return;
1715
1716 I915_WRITE(reg, val | PIPECONF_ENABLE);
1717 intel_wait_for_vblank(dev_priv->dev, pipe);
1718 }
1719
1720 /**
1721 * intel_disable_pipe - disable a pipe, asserting requirements
1722 * @dev_priv: i915 private structure
1723 * @pipe: pipe to disable
1724 *
1725 * Disable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe has shut down before returning.
1731 */
1732 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1733 enum pipe pipe)
1734 {
1735 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1736 pipe);
1737 int reg;
1738 u32 val;
1739
1740 /*
1741 * Make sure planes won't keep trying to pump pixels to us,
1742 * or we might hang the display.
1743 */
1744 assert_planes_disabled(dev_priv, pipe);
1745 assert_sprites_disabled(dev_priv, pipe);
1746
1747 /* Don't disable pipe A or pipe A PLLs if needed */
1748 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1749 return;
1750
1751 reg = PIPECONF(cpu_transcoder);
1752 val = I915_READ(reg);
1753 if ((val & PIPECONF_ENABLE) == 0)
1754 return;
1755
1756 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1757 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1758 }
1759
1760 /*
1761 * Plane regs are double buffered, going from enabled->disabled needs a
1762 * trigger in order to latch. The display address reg provides this.
1763 */
1764 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1765 enum plane plane)
1766 {
1767 if (dev_priv->info->gen >= 4)
1768 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1769 else
1770 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1771 }
1772
1773 /**
1774 * intel_enable_plane - enable a display plane on a given pipe
1775 * @dev_priv: i915 private structure
1776 * @plane: plane to enable
1777 * @pipe: pipe being fed
1778 *
1779 * Enable @plane on @pipe, making sure that @pipe is running first.
1780 */
1781 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1782 enum plane plane, enum pipe pipe)
1783 {
1784 int reg;
1785 u32 val;
1786
1787 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1788 assert_pipe_enabled(dev_priv, pipe);
1789
1790 reg = DSPCNTR(plane);
1791 val = I915_READ(reg);
1792 if (val & DISPLAY_PLANE_ENABLE)
1793 return;
1794
1795 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1796 intel_flush_display_plane(dev_priv, plane);
1797 intel_wait_for_vblank(dev_priv->dev, pipe);
1798 }
1799
1800 /**
1801 * intel_disable_plane - disable a display plane
1802 * @dev_priv: i915 private structure
1803 * @plane: plane to disable
1804 * @pipe: pipe consuming the data
1805 *
1806 * Disable @plane; should be an independent operation.
1807 */
1808 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1809 enum plane plane, enum pipe pipe)
1810 {
1811 int reg;
1812 u32 val;
1813
1814 reg = DSPCNTR(plane);
1815 val = I915_READ(reg);
1816 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1817 return;
1818
1819 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1820 intel_flush_display_plane(dev_priv, plane);
1821 intel_wait_for_vblank(dev_priv->dev, pipe);
1822 }
1823
1824 static bool need_vtd_wa(struct drm_device *dev)
1825 {
1826 #ifdef CONFIG_INTEL_IOMMU
1827 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1828 return true;
1829 #endif
1830 return false;
1831 }
1832
1833 int
1834 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1835 struct drm_i915_gem_object *obj,
1836 struct intel_ring_buffer *pipelined)
1837 {
1838 struct drm_i915_private *dev_priv = dev->dev_private;
1839 u32 alignment;
1840 int ret;
1841
1842 switch (obj->tiling_mode) {
1843 case I915_TILING_NONE:
1844 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1845 alignment = 128 * 1024;
1846 else if (INTEL_INFO(dev)->gen >= 4)
1847 alignment = 4 * 1024;
1848 else
1849 alignment = 64 * 1024;
1850 break;
1851 case I915_TILING_X:
1852 /* pin() will align the object as required by fence */
1853 alignment = 0;
1854 break;
1855 case I915_TILING_Y:
1856 /* Despite that we check this in framebuffer_init userspace can
1857 * screw us over and change the tiling after the fact. Only
1858 * pinned buffers can't change their tiling. */
1859 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1860 return -EINVAL;
1861 default:
1862 BUG();
1863 }
1864
1865 /* Note that the w/a also requires 64 PTE of padding following the
1866 * bo. We currently fill all unused PTE with the shadow page and so
1867 * we should always have valid PTE following the scanout preventing
1868 * the VT-d warning.
1869 */
1870 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1871 alignment = 256 * 1024;
1872
1873 dev_priv->mm.interruptible = false;
1874 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1875 if (ret)
1876 goto err_interruptible;
1877
1878 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1879 * fence, whereas 965+ only requires a fence if using
1880 * framebuffer compression. For simplicity, we always install
1881 * a fence as the cost is not that onerous.
1882 */
1883 ret = i915_gem_object_get_fence(obj);
1884 if (ret)
1885 goto err_unpin;
1886
1887 i915_gem_object_pin_fence(obj);
1888
1889 dev_priv->mm.interruptible = true;
1890 return 0;
1891
1892 err_unpin:
1893 i915_gem_object_unpin_from_display_plane(obj);
1894 err_interruptible:
1895 dev_priv->mm.interruptible = true;
1896 return ret;
1897 }
1898
1899 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1900 {
1901 i915_gem_object_unpin_fence(obj);
1902 i915_gem_object_unpin_from_display_plane(obj);
1903 }
1904
1905 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1906 * is assumed to be a power-of-two. */
1907 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1908 unsigned int tiling_mode,
1909 unsigned int cpp,
1910 unsigned int pitch)
1911 {
1912 if (tiling_mode != I915_TILING_NONE) {
1913 unsigned int tile_rows, tiles;
1914
1915 tile_rows = *y / 8;
1916 *y %= 8;
1917
1918 tiles = *x / (512/cpp);
1919 *x %= 512/cpp;
1920
1921 return tile_rows * pitch * 8 + tiles * 4096;
1922 } else {
1923 unsigned int offset;
1924
1925 offset = *y * pitch + *x * cpp;
1926 *y = 0;
1927 *x = (offset & 4095) / cpp;
1928 return offset & -4096;
1929 }
1930 }
1931
1932 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1933 int x, int y)
1934 {
1935 struct drm_device *dev = crtc->dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1938 struct intel_framebuffer *intel_fb;
1939 struct drm_i915_gem_object *obj;
1940 int plane = intel_crtc->plane;
1941 unsigned long linear_offset;
1942 u32 dspcntr;
1943 u32 reg;
1944
1945 switch (plane) {
1946 case 0:
1947 case 1:
1948 break;
1949 default:
1950 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1951 return -EINVAL;
1952 }
1953
1954 intel_fb = to_intel_framebuffer(fb);
1955 obj = intel_fb->obj;
1956
1957 reg = DSPCNTR(plane);
1958 dspcntr = I915_READ(reg);
1959 /* Mask out pixel format bits in case we change it */
1960 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1961 switch (fb->pixel_format) {
1962 case DRM_FORMAT_C8:
1963 dspcntr |= DISPPLANE_8BPP;
1964 break;
1965 case DRM_FORMAT_XRGB1555:
1966 case DRM_FORMAT_ARGB1555:
1967 dspcntr |= DISPPLANE_BGRX555;
1968 break;
1969 case DRM_FORMAT_RGB565:
1970 dspcntr |= DISPPLANE_BGRX565;
1971 break;
1972 case DRM_FORMAT_XRGB8888:
1973 case DRM_FORMAT_ARGB8888:
1974 dspcntr |= DISPPLANE_BGRX888;
1975 break;
1976 case DRM_FORMAT_XBGR8888:
1977 case DRM_FORMAT_ABGR8888:
1978 dspcntr |= DISPPLANE_RGBX888;
1979 break;
1980 case DRM_FORMAT_XRGB2101010:
1981 case DRM_FORMAT_ARGB2101010:
1982 dspcntr |= DISPPLANE_BGRX101010;
1983 break;
1984 case DRM_FORMAT_XBGR2101010:
1985 case DRM_FORMAT_ABGR2101010:
1986 dspcntr |= DISPPLANE_RGBX101010;
1987 break;
1988 default:
1989 BUG();
1990 }
1991
1992 if (INTEL_INFO(dev)->gen >= 4) {
1993 if (obj->tiling_mode != I915_TILING_NONE)
1994 dspcntr |= DISPPLANE_TILED;
1995 else
1996 dspcntr &= ~DISPPLANE_TILED;
1997 }
1998
1999 if (IS_G4X(dev))
2000 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2001
2002 I915_WRITE(reg, dspcntr);
2003
2004 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2005
2006 if (INTEL_INFO(dev)->gen >= 4) {
2007 intel_crtc->dspaddr_offset =
2008 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2009 fb->bits_per_pixel / 8,
2010 fb->pitches[0]);
2011 linear_offset -= intel_crtc->dspaddr_offset;
2012 } else {
2013 intel_crtc->dspaddr_offset = linear_offset;
2014 }
2015
2016 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2017 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2018 fb->pitches[0]);
2019 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2020 if (INTEL_INFO(dev)->gen >= 4) {
2021 I915_MODIFY_DISPBASE(DSPSURF(plane),
2022 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2023 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2024 I915_WRITE(DSPLINOFF(plane), linear_offset);
2025 } else
2026 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2027 POSTING_READ(reg);
2028
2029 return 0;
2030 }
2031
2032 static int ironlake_update_plane(struct drm_crtc *crtc,
2033 struct drm_framebuffer *fb, int x, int y)
2034 {
2035 struct drm_device *dev = crtc->dev;
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2038 struct intel_framebuffer *intel_fb;
2039 struct drm_i915_gem_object *obj;
2040 int plane = intel_crtc->plane;
2041 unsigned long linear_offset;
2042 u32 dspcntr;
2043 u32 reg;
2044
2045 switch (plane) {
2046 case 0:
2047 case 1:
2048 case 2:
2049 break;
2050 default:
2051 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2052 return -EINVAL;
2053 }
2054
2055 intel_fb = to_intel_framebuffer(fb);
2056 obj = intel_fb->obj;
2057
2058 reg = DSPCNTR(plane);
2059 dspcntr = I915_READ(reg);
2060 /* Mask out pixel format bits in case we change it */
2061 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2062 switch (fb->pixel_format) {
2063 case DRM_FORMAT_C8:
2064 dspcntr |= DISPPLANE_8BPP;
2065 break;
2066 case DRM_FORMAT_RGB565:
2067 dspcntr |= DISPPLANE_BGRX565;
2068 break;
2069 case DRM_FORMAT_XRGB8888:
2070 case DRM_FORMAT_ARGB8888:
2071 dspcntr |= DISPPLANE_BGRX888;
2072 break;
2073 case DRM_FORMAT_XBGR8888:
2074 case DRM_FORMAT_ABGR8888:
2075 dspcntr |= DISPPLANE_RGBX888;
2076 break;
2077 case DRM_FORMAT_XRGB2101010:
2078 case DRM_FORMAT_ARGB2101010:
2079 dspcntr |= DISPPLANE_BGRX101010;
2080 break;
2081 case DRM_FORMAT_XBGR2101010:
2082 case DRM_FORMAT_ABGR2101010:
2083 dspcntr |= DISPPLANE_RGBX101010;
2084 break;
2085 default:
2086 BUG();
2087 }
2088
2089 if (obj->tiling_mode != I915_TILING_NONE)
2090 dspcntr |= DISPPLANE_TILED;
2091 else
2092 dspcntr &= ~DISPPLANE_TILED;
2093
2094 if (IS_HASWELL(dev))
2095 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2096 else
2097 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2098
2099 I915_WRITE(reg, dspcntr);
2100
2101 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2102 intel_crtc->dspaddr_offset =
2103 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2104 fb->bits_per_pixel / 8,
2105 fb->pitches[0]);
2106 linear_offset -= intel_crtc->dspaddr_offset;
2107
2108 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2109 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2110 fb->pitches[0]);
2111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2112 I915_MODIFY_DISPBASE(DSPSURF(plane),
2113 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2114 if (IS_HASWELL(dev)) {
2115 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2116 } else {
2117 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2118 I915_WRITE(DSPLINOFF(plane), linear_offset);
2119 }
2120 POSTING_READ(reg);
2121
2122 return 0;
2123 }
2124
2125 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2126 static int
2127 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2128 int x, int y, enum mode_set_atomic state)
2129 {
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132
2133 if (dev_priv->display.disable_fbc)
2134 dev_priv->display.disable_fbc(dev);
2135 intel_increase_pllclock(crtc);
2136
2137 return dev_priv->display.update_plane(crtc, fb, x, y);
2138 }
2139
2140 void intel_display_handle_reset(struct drm_device *dev)
2141 {
2142 struct drm_i915_private *dev_priv = dev->dev_private;
2143 struct drm_crtc *crtc;
2144
2145 /*
2146 * Flips in the rings have been nuked by the reset,
2147 * so complete all pending flips so that user space
2148 * will get its events and not get stuck.
2149 *
2150 * Also update the base address of all primary
2151 * planes to the the last fb to make sure we're
2152 * showing the correct fb after a reset.
2153 *
2154 * Need to make two loops over the crtcs so that we
2155 * don't try to grab a crtc mutex before the
2156 * pending_flip_queue really got woken up.
2157 */
2158
2159 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161 enum plane plane = intel_crtc->plane;
2162
2163 intel_prepare_page_flip(dev, plane);
2164 intel_finish_page_flip_plane(dev, plane);
2165 }
2166
2167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 mutex_lock(&crtc->mutex);
2171 if (intel_crtc->active)
2172 dev_priv->display.update_plane(crtc, crtc->fb,
2173 crtc->x, crtc->y);
2174 mutex_unlock(&crtc->mutex);
2175 }
2176 }
2177
2178 static int
2179 intel_finish_fb(struct drm_framebuffer *old_fb)
2180 {
2181 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2182 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2183 bool was_interruptible = dev_priv->mm.interruptible;
2184 int ret;
2185
2186 /* Big Hammer, we also need to ensure that any pending
2187 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2188 * current scanout is retired before unpinning the old
2189 * framebuffer.
2190 *
2191 * This should only fail upon a hung GPU, in which case we
2192 * can safely continue.
2193 */
2194 dev_priv->mm.interruptible = false;
2195 ret = i915_gem_object_finish_gpu(obj);
2196 dev_priv->mm.interruptible = was_interruptible;
2197
2198 return ret;
2199 }
2200
2201 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2202 {
2203 struct drm_device *dev = crtc->dev;
2204 struct drm_i915_master_private *master_priv;
2205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2206
2207 if (!dev->primary->master)
2208 return;
2209
2210 master_priv = dev->primary->master->driver_priv;
2211 if (!master_priv->sarea_priv)
2212 return;
2213
2214 switch (intel_crtc->pipe) {
2215 case 0:
2216 master_priv->sarea_priv->pipeA_x = x;
2217 master_priv->sarea_priv->pipeA_y = y;
2218 break;
2219 case 1:
2220 master_priv->sarea_priv->pipeB_x = x;
2221 master_priv->sarea_priv->pipeB_y = y;
2222 break;
2223 default:
2224 break;
2225 }
2226 }
2227
2228 static int
2229 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2230 struct drm_framebuffer *fb)
2231 {
2232 struct drm_device *dev = crtc->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235 struct drm_framebuffer *old_fb;
2236 int ret;
2237
2238 /* no fb bound */
2239 if (!fb) {
2240 DRM_ERROR("No FB bound\n");
2241 return 0;
2242 }
2243
2244 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2245 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2246 plane_name(intel_crtc->plane),
2247 INTEL_INFO(dev)->num_pipes);
2248 return -EINVAL;
2249 }
2250
2251 mutex_lock(&dev->struct_mutex);
2252 ret = intel_pin_and_fence_fb_obj(dev,
2253 to_intel_framebuffer(fb)->obj,
2254 NULL);
2255 if (ret != 0) {
2256 mutex_unlock(&dev->struct_mutex);
2257 DRM_ERROR("pin & fence failed\n");
2258 return ret;
2259 }
2260
2261 /* Update pipe size and adjust fitter if needed */
2262 if (i915_fastboot) {
2263 I915_WRITE(PIPESRC(intel_crtc->pipe),
2264 ((crtc->mode.hdisplay - 1) << 16) |
2265 (crtc->mode.vdisplay - 1));
2266 if (!intel_crtc->config.pch_pfit.enabled &&
2267 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2268 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2269 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2270 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2271 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2272 }
2273 }
2274
2275 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2276 if (ret) {
2277 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2278 mutex_unlock(&dev->struct_mutex);
2279 DRM_ERROR("failed to update base address\n");
2280 return ret;
2281 }
2282
2283 old_fb = crtc->fb;
2284 crtc->fb = fb;
2285 crtc->x = x;
2286 crtc->y = y;
2287
2288 if (old_fb) {
2289 if (intel_crtc->active && old_fb != fb)
2290 intel_wait_for_vblank(dev, intel_crtc->pipe);
2291 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2292 }
2293
2294 intel_update_fbc(dev);
2295 intel_edp_psr_update(dev);
2296 mutex_unlock(&dev->struct_mutex);
2297
2298 intel_crtc_update_sarea_pos(crtc, x, y);
2299
2300 return 0;
2301 }
2302
2303 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2304 {
2305 struct drm_device *dev = crtc->dev;
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308 int pipe = intel_crtc->pipe;
2309 u32 reg, temp;
2310
2311 /* enable normal train */
2312 reg = FDI_TX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 if (IS_IVYBRIDGE(dev)) {
2315 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2316 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2317 } else {
2318 temp &= ~FDI_LINK_TRAIN_NONE;
2319 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2320 }
2321 I915_WRITE(reg, temp);
2322
2323 reg = FDI_RX_CTL(pipe);
2324 temp = I915_READ(reg);
2325 if (HAS_PCH_CPT(dev)) {
2326 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2327 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2328 } else {
2329 temp &= ~FDI_LINK_TRAIN_NONE;
2330 temp |= FDI_LINK_TRAIN_NONE;
2331 }
2332 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2333
2334 /* wait one idle pattern time */
2335 POSTING_READ(reg);
2336 udelay(1000);
2337
2338 /* IVB wants error correction enabled */
2339 if (IS_IVYBRIDGE(dev))
2340 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2341 FDI_FE_ERRC_ENABLE);
2342 }
2343
2344 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2345 {
2346 return crtc->base.enabled && crtc->active &&
2347 crtc->config.has_pch_encoder;
2348 }
2349
2350 static void ivb_modeset_global_resources(struct drm_device *dev)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct intel_crtc *pipe_B_crtc =
2354 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2355 struct intel_crtc *pipe_C_crtc =
2356 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2357 uint32_t temp;
2358
2359 /*
2360 * When everything is off disable fdi C so that we could enable fdi B
2361 * with all lanes. Note that we don't care about enabled pipes without
2362 * an enabled pch encoder.
2363 */
2364 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2365 !pipe_has_enabled_pch(pipe_C_crtc)) {
2366 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2367 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2368
2369 temp = I915_READ(SOUTH_CHICKEN1);
2370 temp &= ~FDI_BC_BIFURCATION_SELECT;
2371 DRM_DEBUG_KMS("disabling fdi C rx\n");
2372 I915_WRITE(SOUTH_CHICKEN1, temp);
2373 }
2374 }
2375
2376 /* The FDI link training functions for ILK/Ibexpeak. */
2377 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2378 {
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 int pipe = intel_crtc->pipe;
2383 int plane = intel_crtc->plane;
2384 u32 reg, temp, tries;
2385
2386 /* FDI needs bits from pipe & plane first */
2387 assert_pipe_enabled(dev_priv, pipe);
2388 assert_plane_enabled(dev_priv, plane);
2389
2390 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2391 for train result */
2392 reg = FDI_RX_IMR(pipe);
2393 temp = I915_READ(reg);
2394 temp &= ~FDI_RX_SYMBOL_LOCK;
2395 temp &= ~FDI_RX_BIT_LOCK;
2396 I915_WRITE(reg, temp);
2397 I915_READ(reg);
2398 udelay(150);
2399
2400 /* enable CPU FDI TX and PCH FDI RX */
2401 reg = FDI_TX_CTL(pipe);
2402 temp = I915_READ(reg);
2403 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2404 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_PATTERN_1;
2407 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2408
2409 reg = FDI_RX_CTL(pipe);
2410 temp = I915_READ(reg);
2411 temp &= ~FDI_LINK_TRAIN_NONE;
2412 temp |= FDI_LINK_TRAIN_PATTERN_1;
2413 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2414
2415 POSTING_READ(reg);
2416 udelay(150);
2417
2418 /* Ironlake workaround, enable clock pointer after FDI enable*/
2419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2421 FDI_RX_PHASE_SYNC_POINTER_EN);
2422
2423 reg = FDI_RX_IIR(pipe);
2424 for (tries = 0; tries < 5; tries++) {
2425 temp = I915_READ(reg);
2426 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2427
2428 if ((temp & FDI_RX_BIT_LOCK)) {
2429 DRM_DEBUG_KMS("FDI train 1 done.\n");
2430 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2431 break;
2432 }
2433 }
2434 if (tries == 5)
2435 DRM_ERROR("FDI train 1 fail!\n");
2436
2437 /* Train 2 */
2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
2440 temp &= ~FDI_LINK_TRAIN_NONE;
2441 temp |= FDI_LINK_TRAIN_PATTERN_2;
2442 I915_WRITE(reg, temp);
2443
2444 reg = FDI_RX_CTL(pipe);
2445 temp = I915_READ(reg);
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_2;
2448 I915_WRITE(reg, temp);
2449
2450 POSTING_READ(reg);
2451 udelay(150);
2452
2453 reg = FDI_RX_IIR(pipe);
2454 for (tries = 0; tries < 5; tries++) {
2455 temp = I915_READ(reg);
2456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2457
2458 if (temp & FDI_RX_SYMBOL_LOCK) {
2459 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2460 DRM_DEBUG_KMS("FDI train 2 done.\n");
2461 break;
2462 }
2463 }
2464 if (tries == 5)
2465 DRM_ERROR("FDI train 2 fail!\n");
2466
2467 DRM_DEBUG_KMS("FDI train done\n");
2468
2469 }
2470
2471 static const int snb_b_fdi_train_param[] = {
2472 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2473 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2474 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2475 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2476 };
2477
2478 /* The FDI link training functions for SNB/Cougarpoint. */
2479 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2480 {
2481 struct drm_device *dev = crtc->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2484 int pipe = intel_crtc->pipe;
2485 u32 reg, temp, i, retry;
2486
2487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2488 for train result */
2489 reg = FDI_RX_IMR(pipe);
2490 temp = I915_READ(reg);
2491 temp &= ~FDI_RX_SYMBOL_LOCK;
2492 temp &= ~FDI_RX_BIT_LOCK;
2493 I915_WRITE(reg, temp);
2494
2495 POSTING_READ(reg);
2496 udelay(150);
2497
2498 /* enable CPU FDI TX and PCH FDI RX */
2499 reg = FDI_TX_CTL(pipe);
2500 temp = I915_READ(reg);
2501 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2502 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2503 temp &= ~FDI_LINK_TRAIN_NONE;
2504 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2506 /* SNB-B */
2507 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2508 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2509
2510 I915_WRITE(FDI_RX_MISC(pipe),
2511 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2512
2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
2515 if (HAS_PCH_CPT(dev)) {
2516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2517 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2518 } else {
2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_1;
2521 }
2522 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2523
2524 POSTING_READ(reg);
2525 udelay(150);
2526
2527 for (i = 0; i < 4; i++) {
2528 reg = FDI_TX_CTL(pipe);
2529 temp = I915_READ(reg);
2530 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2531 temp |= snb_b_fdi_train_param[i];
2532 I915_WRITE(reg, temp);
2533
2534 POSTING_READ(reg);
2535 udelay(500);
2536
2537 for (retry = 0; retry < 5; retry++) {
2538 reg = FDI_RX_IIR(pipe);
2539 temp = I915_READ(reg);
2540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541 if (temp & FDI_RX_BIT_LOCK) {
2542 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2543 DRM_DEBUG_KMS("FDI train 1 done.\n");
2544 break;
2545 }
2546 udelay(50);
2547 }
2548 if (retry < 5)
2549 break;
2550 }
2551 if (i == 4)
2552 DRM_ERROR("FDI train 1 fail!\n");
2553
2554 /* Train 2 */
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
2559 if (IS_GEN6(dev)) {
2560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561 /* SNB-B */
2562 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2563 }
2564 I915_WRITE(reg, temp);
2565
2566 reg = FDI_RX_CTL(pipe);
2567 temp = I915_READ(reg);
2568 if (HAS_PCH_CPT(dev)) {
2569 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2570 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2571 } else {
2572 temp &= ~FDI_LINK_TRAIN_NONE;
2573 temp |= FDI_LINK_TRAIN_PATTERN_2;
2574 }
2575 I915_WRITE(reg, temp);
2576
2577 POSTING_READ(reg);
2578 udelay(150);
2579
2580 for (i = 0; i < 4; i++) {
2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
2583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584 temp |= snb_b_fdi_train_param[i];
2585 I915_WRITE(reg, temp);
2586
2587 POSTING_READ(reg);
2588 udelay(500);
2589
2590 for (retry = 0; retry < 5; retry++) {
2591 reg = FDI_RX_IIR(pipe);
2592 temp = I915_READ(reg);
2593 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2594 if (temp & FDI_RX_SYMBOL_LOCK) {
2595 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2596 DRM_DEBUG_KMS("FDI train 2 done.\n");
2597 break;
2598 }
2599 udelay(50);
2600 }
2601 if (retry < 5)
2602 break;
2603 }
2604 if (i == 4)
2605 DRM_ERROR("FDI train 2 fail!\n");
2606
2607 DRM_DEBUG_KMS("FDI train done.\n");
2608 }
2609
2610 /* Manual link training for Ivy Bridge A0 parts */
2611 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2612 {
2613 struct drm_device *dev = crtc->dev;
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616 int pipe = intel_crtc->pipe;
2617 u32 reg, temp, i, j;
2618
2619 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2620 for train result */
2621 reg = FDI_RX_IMR(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_RX_SYMBOL_LOCK;
2624 temp &= ~FDI_RX_BIT_LOCK;
2625 I915_WRITE(reg, temp);
2626
2627 POSTING_READ(reg);
2628 udelay(150);
2629
2630 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2631 I915_READ(FDI_RX_IIR(pipe)));
2632
2633 /* Try each vswing and preemphasis setting twice before moving on */
2634 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2635 /* disable first in case we need to retry */
2636 reg = FDI_TX_CTL(pipe);
2637 temp = I915_READ(reg);
2638 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2639 temp &= ~FDI_TX_ENABLE;
2640 I915_WRITE(reg, temp);
2641
2642 reg = FDI_RX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_AUTO;
2645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646 temp &= ~FDI_RX_ENABLE;
2647 I915_WRITE(reg, temp);
2648
2649 /* enable CPU FDI TX and PCH FDI RX */
2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
2652 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2653 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2654 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 temp |= snb_b_fdi_train_param[j/2];
2657 temp |= FDI_COMPOSITE_SYNC;
2658 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2659
2660 I915_WRITE(FDI_RX_MISC(pipe),
2661 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2662
2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2666 temp |= FDI_COMPOSITE_SYNC;
2667 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2668
2669 POSTING_READ(reg);
2670 udelay(1); /* should be 0.5us */
2671
2672 for (i = 0; i < 4; i++) {
2673 reg = FDI_RX_IIR(pipe);
2674 temp = I915_READ(reg);
2675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676
2677 if (temp & FDI_RX_BIT_LOCK ||
2678 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2679 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2680 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2681 i);
2682 break;
2683 }
2684 udelay(1); /* should be 0.5us */
2685 }
2686 if (i == 4) {
2687 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2688 continue;
2689 }
2690
2691 /* Train 2 */
2692 reg = FDI_TX_CTL(pipe);
2693 temp = I915_READ(reg);
2694 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2695 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2696 I915_WRITE(reg, temp);
2697
2698 reg = FDI_RX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2701 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
2705 udelay(2); /* should be 1.5us */
2706
2707 for (i = 0; i < 4; i++) {
2708 reg = FDI_RX_IIR(pipe);
2709 temp = I915_READ(reg);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711
2712 if (temp & FDI_RX_SYMBOL_LOCK ||
2713 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2714 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2715 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2716 i);
2717 goto train_done;
2718 }
2719 udelay(2); /* should be 1.5us */
2720 }
2721 if (i == 4)
2722 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2723 }
2724
2725 train_done:
2726 DRM_DEBUG_KMS("FDI train done.\n");
2727 }
2728
2729 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2730 {
2731 struct drm_device *dev = intel_crtc->base.dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp;
2735
2736
2737 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2738 reg = FDI_RX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2741 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2742 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2743 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2744
2745 POSTING_READ(reg);
2746 udelay(200);
2747
2748 /* Switch from Rawclk to PCDclk */
2749 temp = I915_READ(reg);
2750 I915_WRITE(reg, temp | FDI_PCDCLK);
2751
2752 POSTING_READ(reg);
2753 udelay(200);
2754
2755 /* Enable CPU FDI TX PLL, always on for Ironlake */
2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2759 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2760
2761 POSTING_READ(reg);
2762 udelay(100);
2763 }
2764 }
2765
2766 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2767 {
2768 struct drm_device *dev = intel_crtc->base.dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* Switch from PCDclk to Rawclk */
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2777
2778 /* Disable CPU FDI TX PLL */
2779 reg = FDI_TX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2782
2783 POSTING_READ(reg);
2784 udelay(100);
2785
2786 reg = FDI_RX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2789
2790 /* Wait for the clocks to turn off. */
2791 POSTING_READ(reg);
2792 udelay(100);
2793 }
2794
2795 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2796 {
2797 struct drm_device *dev = crtc->dev;
2798 struct drm_i915_private *dev_priv = dev->dev_private;
2799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2800 int pipe = intel_crtc->pipe;
2801 u32 reg, temp;
2802
2803 /* disable CPU FDI tx and PCH FDI rx */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2807 POSTING_READ(reg);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~(0x7 << 16);
2812 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2813 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2814
2815 POSTING_READ(reg);
2816 udelay(100);
2817
2818 /* Ironlake workaround, disable clock pointer after downing FDI */
2819 if (HAS_PCH_IBX(dev)) {
2820 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2821 }
2822
2823 /* still set train pattern 1 */
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~FDI_LINK_TRAIN_NONE;
2827 temp |= FDI_LINK_TRAIN_PATTERN_1;
2828 I915_WRITE(reg, temp);
2829
2830 reg = FDI_RX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 if (HAS_PCH_CPT(dev)) {
2833 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2834 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2835 } else {
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 }
2839 /* BPC in FDI rx is consistent with that in PIPECONF */
2840 temp &= ~(0x07 << 16);
2841 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2842 I915_WRITE(reg, temp);
2843
2844 POSTING_READ(reg);
2845 udelay(100);
2846 }
2847
2848 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2849 {
2850 struct drm_device *dev = crtc->dev;
2851 struct drm_i915_private *dev_priv = dev->dev_private;
2852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2853 unsigned long flags;
2854 bool pending;
2855
2856 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2857 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2858 return false;
2859
2860 spin_lock_irqsave(&dev->event_lock, flags);
2861 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2862 spin_unlock_irqrestore(&dev->event_lock, flags);
2863
2864 return pending;
2865 }
2866
2867 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2868 {
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871
2872 if (crtc->fb == NULL)
2873 return;
2874
2875 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2876
2877 wait_event(dev_priv->pending_flip_queue,
2878 !intel_crtc_has_pending_flip(crtc));
2879
2880 mutex_lock(&dev->struct_mutex);
2881 intel_finish_fb(crtc->fb);
2882 mutex_unlock(&dev->struct_mutex);
2883 }
2884
2885 /* Program iCLKIP clock to the desired frequency */
2886 static void lpt_program_iclkip(struct drm_crtc *crtc)
2887 {
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2891 u32 temp;
2892
2893 mutex_lock(&dev_priv->dpio_lock);
2894
2895 /* It is necessary to ungate the pixclk gate prior to programming
2896 * the divisors, and gate it back when it is done.
2897 */
2898 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2899
2900 /* Disable SSCCTL */
2901 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2902 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2903 SBI_SSCCTL_DISABLE,
2904 SBI_ICLK);
2905
2906 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2907 if (crtc->mode.clock == 20000) {
2908 auxdiv = 1;
2909 divsel = 0x41;
2910 phaseinc = 0x20;
2911 } else {
2912 /* The iCLK virtual clock root frequency is in MHz,
2913 * but the crtc->mode.clock in in KHz. To get the divisors,
2914 * it is necessary to divide one by another, so we
2915 * convert the virtual clock precision to KHz here for higher
2916 * precision.
2917 */
2918 u32 iclk_virtual_root_freq = 172800 * 1000;
2919 u32 iclk_pi_range = 64;
2920 u32 desired_divisor, msb_divisor_value, pi_value;
2921
2922 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2923 msb_divisor_value = desired_divisor / iclk_pi_range;
2924 pi_value = desired_divisor % iclk_pi_range;
2925
2926 auxdiv = 0;
2927 divsel = msb_divisor_value - 2;
2928 phaseinc = pi_value;
2929 }
2930
2931 /* This should not happen with any sane values */
2932 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2933 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2934 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2935 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2936
2937 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2938 crtc->mode.clock,
2939 auxdiv,
2940 divsel,
2941 phasedir,
2942 phaseinc);
2943
2944 /* Program SSCDIVINTPHASE6 */
2945 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2946 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2947 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2948 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2949 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2950 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2951 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2952 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2953
2954 /* Program SSCAUXDIV */
2955 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2956 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2957 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2958 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2959
2960 /* Enable modulator and associated divider */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2962 temp &= ~SBI_SSCCTL_DISABLE;
2963 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2964
2965 /* Wait for initialization time */
2966 udelay(24);
2967
2968 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2969
2970 mutex_unlock(&dev_priv->dpio_lock);
2971 }
2972
2973 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2974 enum pipe pch_transcoder)
2975 {
2976 struct drm_device *dev = crtc->base.dev;
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2979
2980 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2981 I915_READ(HTOTAL(cpu_transcoder)));
2982 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2983 I915_READ(HBLANK(cpu_transcoder)));
2984 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2985 I915_READ(HSYNC(cpu_transcoder)));
2986
2987 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2988 I915_READ(VTOTAL(cpu_transcoder)));
2989 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2990 I915_READ(VBLANK(cpu_transcoder)));
2991 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2992 I915_READ(VSYNC(cpu_transcoder)));
2993 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2994 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2995 }
2996
2997 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
2998 {
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 uint32_t temp;
3001
3002 temp = I915_READ(SOUTH_CHICKEN1);
3003 if (temp & FDI_BC_BIFURCATION_SELECT)
3004 return;
3005
3006 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3007 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3008
3009 temp |= FDI_BC_BIFURCATION_SELECT;
3010 DRM_DEBUG_KMS("enabling fdi C rx\n");
3011 I915_WRITE(SOUTH_CHICKEN1, temp);
3012 POSTING_READ(SOUTH_CHICKEN1);
3013 }
3014
3015 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3016 {
3017 struct drm_device *dev = intel_crtc->base.dev;
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019
3020 switch (intel_crtc->pipe) {
3021 case PIPE_A:
3022 break;
3023 case PIPE_B:
3024 if (intel_crtc->config.fdi_lanes > 2)
3025 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3026 else
3027 cpt_enable_fdi_bc_bifurcation(dev);
3028
3029 break;
3030 case PIPE_C:
3031 cpt_enable_fdi_bc_bifurcation(dev);
3032
3033 break;
3034 default:
3035 BUG();
3036 }
3037 }
3038
3039 /*
3040 * Enable PCH resources required for PCH ports:
3041 * - PCH PLLs
3042 * - FDI training & RX/TX
3043 * - update transcoder timings
3044 * - DP transcoding bits
3045 * - transcoder
3046 */
3047 static void ironlake_pch_enable(struct drm_crtc *crtc)
3048 {
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 int pipe = intel_crtc->pipe;
3053 u32 reg, temp;
3054
3055 assert_pch_transcoder_disabled(dev_priv, pipe);
3056
3057 if (IS_IVYBRIDGE(dev))
3058 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3059
3060 /* Write the TU size bits before fdi link training, so that error
3061 * detection works. */
3062 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3063 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3064
3065 /* For PCH output, training FDI link */
3066 dev_priv->display.fdi_link_train(crtc);
3067
3068 /* We need to program the right clock selection before writing the pixel
3069 * mutliplier into the DPLL. */
3070 if (HAS_PCH_CPT(dev)) {
3071 u32 sel;
3072
3073 temp = I915_READ(PCH_DPLL_SEL);
3074 temp |= TRANS_DPLL_ENABLE(pipe);
3075 sel = TRANS_DPLLB_SEL(pipe);
3076 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3077 temp |= sel;
3078 else
3079 temp &= ~sel;
3080 I915_WRITE(PCH_DPLL_SEL, temp);
3081 }
3082
3083 /* XXX: pch pll's can be enabled any time before we enable the PCH
3084 * transcoder, and we actually should do this to not upset any PCH
3085 * transcoder that already use the clock when we share it.
3086 *
3087 * Note that enable_shared_dpll tries to do the right thing, but
3088 * get_shared_dpll unconditionally resets the pll - we need that to have
3089 * the right LVDS enable sequence. */
3090 ironlake_enable_shared_dpll(intel_crtc);
3091
3092 /* set transcoder timing, panel must allow it */
3093 assert_panel_unlocked(dev_priv, pipe);
3094 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3095
3096 intel_fdi_normal_train(crtc);
3097
3098 /* For PCH DP, enable TRANS_DP_CTL */
3099 if (HAS_PCH_CPT(dev) &&
3100 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3101 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3102 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3103 reg = TRANS_DP_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3106 TRANS_DP_SYNC_MASK |
3107 TRANS_DP_BPC_MASK);
3108 temp |= (TRANS_DP_OUTPUT_ENABLE |
3109 TRANS_DP_ENH_FRAMING);
3110 temp |= bpc << 9; /* same format but at 11:9 */
3111
3112 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3113 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3114 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3115 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3116
3117 switch (intel_trans_dp_port_sel(crtc)) {
3118 case PCH_DP_B:
3119 temp |= TRANS_DP_PORT_SEL_B;
3120 break;
3121 case PCH_DP_C:
3122 temp |= TRANS_DP_PORT_SEL_C;
3123 break;
3124 case PCH_DP_D:
3125 temp |= TRANS_DP_PORT_SEL_D;
3126 break;
3127 default:
3128 BUG();
3129 }
3130
3131 I915_WRITE(reg, temp);
3132 }
3133
3134 ironlake_enable_pch_transcoder(dev_priv, pipe);
3135 }
3136
3137 static void lpt_pch_enable(struct drm_crtc *crtc)
3138 {
3139 struct drm_device *dev = crtc->dev;
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3142 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3143
3144 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3145
3146 lpt_program_iclkip(crtc);
3147
3148 /* Set transcoder timing. */
3149 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3150
3151 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3152 }
3153
3154 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3155 {
3156 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3157
3158 if (pll == NULL)
3159 return;
3160
3161 if (pll->refcount == 0) {
3162 WARN(1, "bad %s refcount\n", pll->name);
3163 return;
3164 }
3165
3166 if (--pll->refcount == 0) {
3167 WARN_ON(pll->on);
3168 WARN_ON(pll->active);
3169 }
3170
3171 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3172 }
3173
3174 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3175 {
3176 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3177 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3178 enum intel_dpll_id i;
3179
3180 if (pll) {
3181 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3182 crtc->base.base.id, pll->name);
3183 intel_put_shared_dpll(crtc);
3184 }
3185
3186 if (HAS_PCH_IBX(dev_priv->dev)) {
3187 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3188 i = (enum intel_dpll_id) crtc->pipe;
3189 pll = &dev_priv->shared_dplls[i];
3190
3191 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3192 crtc->base.base.id, pll->name);
3193
3194 goto found;
3195 }
3196
3197 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3198 pll = &dev_priv->shared_dplls[i];
3199
3200 /* Only want to check enabled timings first */
3201 if (pll->refcount == 0)
3202 continue;
3203
3204 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3205 sizeof(pll->hw_state)) == 0) {
3206 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3207 crtc->base.base.id,
3208 pll->name, pll->refcount, pll->active);
3209
3210 goto found;
3211 }
3212 }
3213
3214 /* Ok no matching timings, maybe there's a free one? */
3215 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3216 pll = &dev_priv->shared_dplls[i];
3217 if (pll->refcount == 0) {
3218 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3219 crtc->base.base.id, pll->name);
3220 goto found;
3221 }
3222 }
3223
3224 return NULL;
3225
3226 found:
3227 crtc->config.shared_dpll = i;
3228 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3229 pipe_name(crtc->pipe));
3230
3231 if (pll->active == 0) {
3232 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3233 sizeof(pll->hw_state));
3234
3235 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3236 WARN_ON(pll->on);
3237 assert_shared_dpll_disabled(dev_priv, pll);
3238
3239 pll->mode_set(dev_priv, pll);
3240 }
3241 pll->refcount++;
3242
3243 return pll;
3244 }
3245
3246 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3247 {
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 int dslreg = PIPEDSL(pipe);
3250 u32 temp;
3251
3252 temp = I915_READ(dslreg);
3253 udelay(500);
3254 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3255 if (wait_for(I915_READ(dslreg) != temp, 5))
3256 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3257 }
3258 }
3259
3260 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3261 {
3262 struct drm_device *dev = crtc->base.dev;
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 int pipe = crtc->pipe;
3265
3266 if (crtc->config.pch_pfit.enabled) {
3267 /* Force use of hard-coded filter coefficients
3268 * as some pre-programmed values are broken,
3269 * e.g. x201.
3270 */
3271 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3272 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3273 PF_PIPE_SEL_IVB(pipe));
3274 else
3275 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3276 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3277 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3278 }
3279 }
3280
3281 static void intel_enable_planes(struct drm_crtc *crtc)
3282 {
3283 struct drm_device *dev = crtc->dev;
3284 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3285 struct intel_plane *intel_plane;
3286
3287 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3288 if (intel_plane->pipe == pipe)
3289 intel_plane_restore(&intel_plane->base);
3290 }
3291
3292 static void intel_disable_planes(struct drm_crtc *crtc)
3293 {
3294 struct drm_device *dev = crtc->dev;
3295 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3296 struct intel_plane *intel_plane;
3297
3298 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3299 if (intel_plane->pipe == pipe)
3300 intel_plane_disable(&intel_plane->base);
3301 }
3302
3303 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3304 {
3305 struct drm_device *dev = crtc->dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3308 struct intel_encoder *encoder;
3309 int pipe = intel_crtc->pipe;
3310 int plane = intel_crtc->plane;
3311
3312 WARN_ON(!crtc->enabled);
3313
3314 if (intel_crtc->active)
3315 return;
3316
3317 intel_crtc->active = true;
3318
3319 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3320 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3321
3322 intel_update_watermarks(dev);
3323
3324 for_each_encoder_on_crtc(dev, crtc, encoder)
3325 if (encoder->pre_enable)
3326 encoder->pre_enable(encoder);
3327
3328 if (intel_crtc->config.has_pch_encoder) {
3329 /* Note: FDI PLL enabling _must_ be done before we enable the
3330 * cpu pipes, hence this is separate from all the other fdi/pch
3331 * enabling. */
3332 ironlake_fdi_pll_enable(intel_crtc);
3333 } else {
3334 assert_fdi_tx_disabled(dev_priv, pipe);
3335 assert_fdi_rx_disabled(dev_priv, pipe);
3336 }
3337
3338 ironlake_pfit_enable(intel_crtc);
3339
3340 /*
3341 * On ILK+ LUT must be loaded before the pipe is running but with
3342 * clocks enabled
3343 */
3344 intel_crtc_load_lut(crtc);
3345
3346 intel_enable_pipe(dev_priv, pipe,
3347 intel_crtc->config.has_pch_encoder);
3348 intel_enable_plane(dev_priv, plane, pipe);
3349 intel_enable_planes(crtc);
3350 intel_crtc_update_cursor(crtc, true);
3351
3352 if (intel_crtc->config.has_pch_encoder)
3353 ironlake_pch_enable(crtc);
3354
3355 mutex_lock(&dev->struct_mutex);
3356 intel_update_fbc(dev);
3357 mutex_unlock(&dev->struct_mutex);
3358
3359 for_each_encoder_on_crtc(dev, crtc, encoder)
3360 encoder->enable(encoder);
3361
3362 if (HAS_PCH_CPT(dev))
3363 cpt_verify_modeset(dev, intel_crtc->pipe);
3364
3365 /*
3366 * There seems to be a race in PCH platform hw (at least on some
3367 * outputs) where an enabled pipe still completes any pageflip right
3368 * away (as if the pipe is off) instead of waiting for vblank. As soon
3369 * as the first vblank happend, everything works as expected. Hence just
3370 * wait for one vblank before returning to avoid strange things
3371 * happening.
3372 */
3373 intel_wait_for_vblank(dev, intel_crtc->pipe);
3374 }
3375
3376 /* IPS only exists on ULT machines and is tied to pipe A. */
3377 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3378 {
3379 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3380 }
3381
3382 static void hsw_enable_ips(struct intel_crtc *crtc)
3383 {
3384 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3385
3386 if (!crtc->config.ips_enabled)
3387 return;
3388
3389 /* We can only enable IPS after we enable a plane and wait for a vblank.
3390 * We guarantee that the plane is enabled by calling intel_enable_ips
3391 * only after intel_enable_plane. And intel_enable_plane already waits
3392 * for a vblank, so all we need to do here is to enable the IPS bit. */
3393 assert_plane_enabled(dev_priv, crtc->plane);
3394 I915_WRITE(IPS_CTL, IPS_ENABLE);
3395 }
3396
3397 static void hsw_disable_ips(struct intel_crtc *crtc)
3398 {
3399 struct drm_device *dev = crtc->base.dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401
3402 if (!crtc->config.ips_enabled)
3403 return;
3404
3405 assert_plane_enabled(dev_priv, crtc->plane);
3406 I915_WRITE(IPS_CTL, 0);
3407
3408 /* We need to wait for a vblank before we can disable the plane. */
3409 intel_wait_for_vblank(dev, crtc->pipe);
3410 }
3411
3412 static void haswell_crtc_enable(struct drm_crtc *crtc)
3413 {
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3417 struct intel_encoder *encoder;
3418 int pipe = intel_crtc->pipe;
3419 int plane = intel_crtc->plane;
3420
3421 WARN_ON(!crtc->enabled);
3422
3423 if (intel_crtc->active)
3424 return;
3425
3426 intel_crtc->active = true;
3427
3428 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3429 if (intel_crtc->config.has_pch_encoder)
3430 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3431
3432 intel_update_watermarks(dev);
3433
3434 if (intel_crtc->config.has_pch_encoder)
3435 dev_priv->display.fdi_link_train(crtc);
3436
3437 for_each_encoder_on_crtc(dev, crtc, encoder)
3438 if (encoder->pre_enable)
3439 encoder->pre_enable(encoder);
3440
3441 intel_ddi_enable_pipe_clock(intel_crtc);
3442
3443 ironlake_pfit_enable(intel_crtc);
3444
3445 /*
3446 * On ILK+ LUT must be loaded before the pipe is running but with
3447 * clocks enabled
3448 */
3449 intel_crtc_load_lut(crtc);
3450
3451 intel_ddi_set_pipe_settings(crtc);
3452 intel_ddi_enable_transcoder_func(crtc);
3453
3454 intel_enable_pipe(dev_priv, pipe,
3455 intel_crtc->config.has_pch_encoder);
3456 intel_enable_plane(dev_priv, plane, pipe);
3457 intel_enable_planes(crtc);
3458 intel_crtc_update_cursor(crtc, true);
3459
3460 hsw_enable_ips(intel_crtc);
3461
3462 if (intel_crtc->config.has_pch_encoder)
3463 lpt_pch_enable(crtc);
3464
3465 mutex_lock(&dev->struct_mutex);
3466 intel_update_fbc(dev);
3467 mutex_unlock(&dev->struct_mutex);
3468
3469 for_each_encoder_on_crtc(dev, crtc, encoder)
3470 encoder->enable(encoder);
3471
3472 /*
3473 * There seems to be a race in PCH platform hw (at least on some
3474 * outputs) where an enabled pipe still completes any pageflip right
3475 * away (as if the pipe is off) instead of waiting for vblank. As soon
3476 * as the first vblank happend, everything works as expected. Hence just
3477 * wait for one vblank before returning to avoid strange things
3478 * happening.
3479 */
3480 intel_wait_for_vblank(dev, intel_crtc->pipe);
3481 }
3482
3483 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3484 {
3485 struct drm_device *dev = crtc->base.dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 int pipe = crtc->pipe;
3488
3489 /* To avoid upsetting the power well on haswell only disable the pfit if
3490 * it's in use. The hw state code will make sure we get this right. */
3491 if (crtc->config.pch_pfit.enabled) {
3492 I915_WRITE(PF_CTL(pipe), 0);
3493 I915_WRITE(PF_WIN_POS(pipe), 0);
3494 I915_WRITE(PF_WIN_SZ(pipe), 0);
3495 }
3496 }
3497
3498 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3499 {
3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3503 struct intel_encoder *encoder;
3504 int pipe = intel_crtc->pipe;
3505 int plane = intel_crtc->plane;
3506 u32 reg, temp;
3507
3508
3509 if (!intel_crtc->active)
3510 return;
3511
3512 for_each_encoder_on_crtc(dev, crtc, encoder)
3513 encoder->disable(encoder);
3514
3515 intel_crtc_wait_for_pending_flips(crtc);
3516 drm_vblank_off(dev, pipe);
3517
3518 if (dev_priv->fbc.plane == plane)
3519 intel_disable_fbc(dev);
3520
3521 intel_crtc_update_cursor(crtc, false);
3522 intel_disable_planes(crtc);
3523 intel_disable_plane(dev_priv, plane, pipe);
3524
3525 if (intel_crtc->config.has_pch_encoder)
3526 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3527
3528 intel_disable_pipe(dev_priv, pipe);
3529
3530 ironlake_pfit_disable(intel_crtc);
3531
3532 for_each_encoder_on_crtc(dev, crtc, encoder)
3533 if (encoder->post_disable)
3534 encoder->post_disable(encoder);
3535
3536 if (intel_crtc->config.has_pch_encoder) {
3537 ironlake_fdi_disable(crtc);
3538
3539 ironlake_disable_pch_transcoder(dev_priv, pipe);
3540 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3541
3542 if (HAS_PCH_CPT(dev)) {
3543 /* disable TRANS_DP_CTL */
3544 reg = TRANS_DP_CTL(pipe);
3545 temp = I915_READ(reg);
3546 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3547 TRANS_DP_PORT_SEL_MASK);
3548 temp |= TRANS_DP_PORT_SEL_NONE;
3549 I915_WRITE(reg, temp);
3550
3551 /* disable DPLL_SEL */
3552 temp = I915_READ(PCH_DPLL_SEL);
3553 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3554 I915_WRITE(PCH_DPLL_SEL, temp);
3555 }
3556
3557 /* disable PCH DPLL */
3558 intel_disable_shared_dpll(intel_crtc);
3559
3560 ironlake_fdi_pll_disable(intel_crtc);
3561 }
3562
3563 intel_crtc->active = false;
3564 intel_update_watermarks(dev);
3565
3566 mutex_lock(&dev->struct_mutex);
3567 intel_update_fbc(dev);
3568 mutex_unlock(&dev->struct_mutex);
3569 }
3570
3571 static void haswell_crtc_disable(struct drm_crtc *crtc)
3572 {
3573 struct drm_device *dev = crtc->dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576 struct intel_encoder *encoder;
3577 int pipe = intel_crtc->pipe;
3578 int plane = intel_crtc->plane;
3579 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3580
3581 if (!intel_crtc->active)
3582 return;
3583
3584 for_each_encoder_on_crtc(dev, crtc, encoder)
3585 encoder->disable(encoder);
3586
3587 intel_crtc_wait_for_pending_flips(crtc);
3588 drm_vblank_off(dev, pipe);
3589
3590 /* FBC must be disabled before disabling the plane on HSW. */
3591 if (dev_priv->fbc.plane == plane)
3592 intel_disable_fbc(dev);
3593
3594 hsw_disable_ips(intel_crtc);
3595
3596 intel_crtc_update_cursor(crtc, false);
3597 intel_disable_planes(crtc);
3598 intel_disable_plane(dev_priv, plane, pipe);
3599
3600 if (intel_crtc->config.has_pch_encoder)
3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3602 intel_disable_pipe(dev_priv, pipe);
3603
3604 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3605
3606 ironlake_pfit_disable(intel_crtc);
3607
3608 intel_ddi_disable_pipe_clock(intel_crtc);
3609
3610 for_each_encoder_on_crtc(dev, crtc, encoder)
3611 if (encoder->post_disable)
3612 encoder->post_disable(encoder);
3613
3614 if (intel_crtc->config.has_pch_encoder) {
3615 lpt_disable_pch_transcoder(dev_priv);
3616 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3617 intel_ddi_fdi_disable(crtc);
3618 }
3619
3620 intel_crtc->active = false;
3621 intel_update_watermarks(dev);
3622
3623 mutex_lock(&dev->struct_mutex);
3624 intel_update_fbc(dev);
3625 mutex_unlock(&dev->struct_mutex);
3626 }
3627
3628 static void ironlake_crtc_off(struct drm_crtc *crtc)
3629 {
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 intel_put_shared_dpll(intel_crtc);
3632 }
3633
3634 static void haswell_crtc_off(struct drm_crtc *crtc)
3635 {
3636 intel_ddi_put_crtc_pll(crtc);
3637 }
3638
3639 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3640 {
3641 if (!enable && intel_crtc->overlay) {
3642 struct drm_device *dev = intel_crtc->base.dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644
3645 mutex_lock(&dev->struct_mutex);
3646 dev_priv->mm.interruptible = false;
3647 (void) intel_overlay_switch_off(intel_crtc->overlay);
3648 dev_priv->mm.interruptible = true;
3649 mutex_unlock(&dev->struct_mutex);
3650 }
3651
3652 /* Let userspace switch the overlay on again. In most cases userspace
3653 * has to recompute where to put it anyway.
3654 */
3655 }
3656
3657 /**
3658 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3659 * cursor plane briefly if not already running after enabling the display
3660 * plane.
3661 * This workaround avoids occasional blank screens when self refresh is
3662 * enabled.
3663 */
3664 static void
3665 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3666 {
3667 u32 cntl = I915_READ(CURCNTR(pipe));
3668
3669 if ((cntl & CURSOR_MODE) == 0) {
3670 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3671
3672 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3673 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3674 intel_wait_for_vblank(dev_priv->dev, pipe);
3675 I915_WRITE(CURCNTR(pipe), cntl);
3676 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3677 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3678 }
3679 }
3680
3681 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3682 {
3683 struct drm_device *dev = crtc->base.dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc_config *pipe_config = &crtc->config;
3686
3687 if (!crtc->config.gmch_pfit.control)
3688 return;
3689
3690 /*
3691 * The panel fitter should only be adjusted whilst the pipe is disabled,
3692 * according to register description and PRM.
3693 */
3694 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3695 assert_pipe_disabled(dev_priv, crtc->pipe);
3696
3697 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3698 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3699
3700 /* Border color in case we don't scale up to the full screen. Black by
3701 * default, change to something else for debugging. */
3702 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3703 }
3704
3705 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3706 {
3707 struct drm_device *dev = crtc->dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3710 struct intel_encoder *encoder;
3711 int pipe = intel_crtc->pipe;
3712 int plane = intel_crtc->plane;
3713
3714 WARN_ON(!crtc->enabled);
3715
3716 if (intel_crtc->active)
3717 return;
3718
3719 intel_crtc->active = true;
3720 intel_update_watermarks(dev);
3721
3722 for_each_encoder_on_crtc(dev, crtc, encoder)
3723 if (encoder->pre_pll_enable)
3724 encoder->pre_pll_enable(encoder);
3725
3726 vlv_enable_pll(intel_crtc);
3727
3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 if (encoder->pre_enable)
3730 encoder->pre_enable(encoder);
3731
3732 i9xx_pfit_enable(intel_crtc);
3733
3734 intel_crtc_load_lut(crtc);
3735
3736 intel_enable_pipe(dev_priv, pipe, false);
3737 intel_enable_plane(dev_priv, plane, pipe);
3738 intel_enable_planes(crtc);
3739 intel_crtc_update_cursor(crtc, true);
3740
3741 intel_update_fbc(dev);
3742
3743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->enable(encoder);
3745 }
3746
3747 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3748 {
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3752 struct intel_encoder *encoder;
3753 int pipe = intel_crtc->pipe;
3754 int plane = intel_crtc->plane;
3755
3756 WARN_ON(!crtc->enabled);
3757
3758 if (intel_crtc->active)
3759 return;
3760
3761 intel_crtc->active = true;
3762 intel_update_watermarks(dev);
3763
3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 if (encoder->pre_enable)
3766 encoder->pre_enable(encoder);
3767
3768 i9xx_enable_pll(intel_crtc);
3769
3770 i9xx_pfit_enable(intel_crtc);
3771
3772 intel_crtc_load_lut(crtc);
3773
3774 intel_enable_pipe(dev_priv, pipe, false);
3775 intel_enable_plane(dev_priv, plane, pipe);
3776 intel_enable_planes(crtc);
3777 /* The fixup needs to happen before cursor is enabled */
3778 if (IS_G4X(dev))
3779 g4x_fixup_plane(dev_priv, pipe);
3780 intel_crtc_update_cursor(crtc, true);
3781
3782 /* Give the overlay scaler a chance to enable if it's on this pipe */
3783 intel_crtc_dpms_overlay(intel_crtc, true);
3784
3785 intel_update_fbc(dev);
3786
3787 for_each_encoder_on_crtc(dev, crtc, encoder)
3788 encoder->enable(encoder);
3789 }
3790
3791 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3792 {
3793 struct drm_device *dev = crtc->base.dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795
3796 if (!crtc->config.gmch_pfit.control)
3797 return;
3798
3799 assert_pipe_disabled(dev_priv, crtc->pipe);
3800
3801 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3802 I915_READ(PFIT_CONTROL));
3803 I915_WRITE(PFIT_CONTROL, 0);
3804 }
3805
3806 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3807 {
3808 struct drm_device *dev = crtc->dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3811 struct intel_encoder *encoder;
3812 int pipe = intel_crtc->pipe;
3813 int plane = intel_crtc->plane;
3814
3815 if (!intel_crtc->active)
3816 return;
3817
3818 for_each_encoder_on_crtc(dev, crtc, encoder)
3819 encoder->disable(encoder);
3820
3821 /* Give the overlay scaler a chance to disable if it's on this pipe */
3822 intel_crtc_wait_for_pending_flips(crtc);
3823 drm_vblank_off(dev, pipe);
3824
3825 if (dev_priv->fbc.plane == plane)
3826 intel_disable_fbc(dev);
3827
3828 intel_crtc_dpms_overlay(intel_crtc, false);
3829 intel_crtc_update_cursor(crtc, false);
3830 intel_disable_planes(crtc);
3831 intel_disable_plane(dev_priv, plane, pipe);
3832
3833 intel_disable_pipe(dev_priv, pipe);
3834
3835 i9xx_pfit_disable(intel_crtc);
3836
3837 for_each_encoder_on_crtc(dev, crtc, encoder)
3838 if (encoder->post_disable)
3839 encoder->post_disable(encoder);
3840
3841 if (IS_VALLEYVIEW(dev))
3842 vlv_disable_pll(dev_priv, pipe);
3843 else
3844 i9xx_disable_pll(dev_priv, pipe);
3845
3846 intel_crtc->active = false;
3847 intel_update_fbc(dev);
3848 intel_update_watermarks(dev);
3849 }
3850
3851 static void i9xx_crtc_off(struct drm_crtc *crtc)
3852 {
3853 }
3854
3855 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3856 bool enabled)
3857 {
3858 struct drm_device *dev = crtc->dev;
3859 struct drm_i915_master_private *master_priv;
3860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3861 int pipe = intel_crtc->pipe;
3862
3863 if (!dev->primary->master)
3864 return;
3865
3866 master_priv = dev->primary->master->driver_priv;
3867 if (!master_priv->sarea_priv)
3868 return;
3869
3870 switch (pipe) {
3871 case 0:
3872 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3873 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3874 break;
3875 case 1:
3876 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3877 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3878 break;
3879 default:
3880 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3881 break;
3882 }
3883 }
3884
3885 /**
3886 * Sets the power management mode of the pipe and plane.
3887 */
3888 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3889 {
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_encoder *intel_encoder;
3893 bool enable = false;
3894
3895 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3896 enable |= intel_encoder->connectors_active;
3897
3898 if (enable)
3899 dev_priv->display.crtc_enable(crtc);
3900 else
3901 dev_priv->display.crtc_disable(crtc);
3902
3903 intel_crtc_update_sarea(crtc, enable);
3904 }
3905
3906 static void intel_crtc_disable(struct drm_crtc *crtc)
3907 {
3908 struct drm_device *dev = crtc->dev;
3909 struct drm_connector *connector;
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3912
3913 /* crtc should still be enabled when we disable it. */
3914 WARN_ON(!crtc->enabled);
3915
3916 dev_priv->display.crtc_disable(crtc);
3917 intel_crtc->eld_vld = false;
3918 intel_crtc_update_sarea(crtc, false);
3919 dev_priv->display.off(crtc);
3920
3921 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3922 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3923
3924 if (crtc->fb) {
3925 mutex_lock(&dev->struct_mutex);
3926 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3927 mutex_unlock(&dev->struct_mutex);
3928 crtc->fb = NULL;
3929 }
3930
3931 /* Update computed state. */
3932 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3933 if (!connector->encoder || !connector->encoder->crtc)
3934 continue;
3935
3936 if (connector->encoder->crtc != crtc)
3937 continue;
3938
3939 connector->dpms = DRM_MODE_DPMS_OFF;
3940 to_intel_encoder(connector->encoder)->connectors_active = false;
3941 }
3942 }
3943
3944 void intel_encoder_destroy(struct drm_encoder *encoder)
3945 {
3946 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3947
3948 drm_encoder_cleanup(encoder);
3949 kfree(intel_encoder);
3950 }
3951
3952 /* Simple dpms helper for encoders with just one connector, no cloning and only
3953 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3954 * state of the entire output pipe. */
3955 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3956 {
3957 if (mode == DRM_MODE_DPMS_ON) {
3958 encoder->connectors_active = true;
3959
3960 intel_crtc_update_dpms(encoder->base.crtc);
3961 } else {
3962 encoder->connectors_active = false;
3963
3964 intel_crtc_update_dpms(encoder->base.crtc);
3965 }
3966 }
3967
3968 /* Cross check the actual hw state with our own modeset state tracking (and it's
3969 * internal consistency). */
3970 static void intel_connector_check_state(struct intel_connector *connector)
3971 {
3972 if (connector->get_hw_state(connector)) {
3973 struct intel_encoder *encoder = connector->encoder;
3974 struct drm_crtc *crtc;
3975 bool encoder_enabled;
3976 enum pipe pipe;
3977
3978 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3979 connector->base.base.id,
3980 drm_get_connector_name(&connector->base));
3981
3982 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3983 "wrong connector dpms state\n");
3984 WARN(connector->base.encoder != &encoder->base,
3985 "active connector not linked to encoder\n");
3986 WARN(!encoder->connectors_active,
3987 "encoder->connectors_active not set\n");
3988
3989 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3990 WARN(!encoder_enabled, "encoder not enabled\n");
3991 if (WARN_ON(!encoder->base.crtc))
3992 return;
3993
3994 crtc = encoder->base.crtc;
3995
3996 WARN(!crtc->enabled, "crtc not enabled\n");
3997 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3998 WARN(pipe != to_intel_crtc(crtc)->pipe,
3999 "encoder active on the wrong pipe\n");
4000 }
4001 }
4002
4003 /* Even simpler default implementation, if there's really no special case to
4004 * consider. */
4005 void intel_connector_dpms(struct drm_connector *connector, int mode)
4006 {
4007 /* All the simple cases only support two dpms states. */
4008 if (mode != DRM_MODE_DPMS_ON)
4009 mode = DRM_MODE_DPMS_OFF;
4010
4011 if (mode == connector->dpms)
4012 return;
4013
4014 connector->dpms = mode;
4015
4016 /* Only need to change hw state when actually enabled */
4017 if (connector->encoder)
4018 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4019
4020 intel_modeset_check_state(connector->dev);
4021 }
4022
4023 /* Simple connector->get_hw_state implementation for encoders that support only
4024 * one connector and no cloning and hence the encoder state determines the state
4025 * of the connector. */
4026 bool intel_connector_get_hw_state(struct intel_connector *connector)
4027 {
4028 enum pipe pipe = 0;
4029 struct intel_encoder *encoder = connector->encoder;
4030
4031 return encoder->get_hw_state(encoder, &pipe);
4032 }
4033
4034 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4035 struct intel_crtc_config *pipe_config)
4036 {
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_crtc *pipe_B_crtc =
4039 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4040
4041 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4042 pipe_name(pipe), pipe_config->fdi_lanes);
4043 if (pipe_config->fdi_lanes > 4) {
4044 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4045 pipe_name(pipe), pipe_config->fdi_lanes);
4046 return false;
4047 }
4048
4049 if (IS_HASWELL(dev)) {
4050 if (pipe_config->fdi_lanes > 2) {
4051 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4052 pipe_config->fdi_lanes);
4053 return false;
4054 } else {
4055 return true;
4056 }
4057 }
4058
4059 if (INTEL_INFO(dev)->num_pipes == 2)
4060 return true;
4061
4062 /* Ivybridge 3 pipe is really complicated */
4063 switch (pipe) {
4064 case PIPE_A:
4065 return true;
4066 case PIPE_B:
4067 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4068 pipe_config->fdi_lanes > 2) {
4069 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4070 pipe_name(pipe), pipe_config->fdi_lanes);
4071 return false;
4072 }
4073 return true;
4074 case PIPE_C:
4075 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4076 pipe_B_crtc->config.fdi_lanes <= 2) {
4077 if (pipe_config->fdi_lanes > 2) {
4078 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4079 pipe_name(pipe), pipe_config->fdi_lanes);
4080 return false;
4081 }
4082 } else {
4083 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4084 return false;
4085 }
4086 return true;
4087 default:
4088 BUG();
4089 }
4090 }
4091
4092 #define RETRY 1
4093 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4094 struct intel_crtc_config *pipe_config)
4095 {
4096 struct drm_device *dev = intel_crtc->base.dev;
4097 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4098 int lane, link_bw, fdi_dotclock;
4099 bool setup_ok, needs_recompute = false;
4100
4101 retry:
4102 /* FDI is a binary signal running at ~2.7GHz, encoding
4103 * each output octet as 10 bits. The actual frequency
4104 * is stored as a divider into a 100MHz clock, and the
4105 * mode pixel clock is stored in units of 1KHz.
4106 * Hence the bw of each lane in terms of the mode signal
4107 * is:
4108 */
4109 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4110
4111 fdi_dotclock = adjusted_mode->clock;
4112 fdi_dotclock /= pipe_config->pixel_multiplier;
4113
4114 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4115 pipe_config->pipe_bpp);
4116
4117 pipe_config->fdi_lanes = lane;
4118
4119 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4120 link_bw, &pipe_config->fdi_m_n);
4121
4122 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4123 intel_crtc->pipe, pipe_config);
4124 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4125 pipe_config->pipe_bpp -= 2*3;
4126 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4127 pipe_config->pipe_bpp);
4128 needs_recompute = true;
4129 pipe_config->bw_constrained = true;
4130
4131 goto retry;
4132 }
4133
4134 if (needs_recompute)
4135 return RETRY;
4136
4137 return setup_ok ? 0 : -EINVAL;
4138 }
4139
4140 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4141 struct intel_crtc_config *pipe_config)
4142 {
4143 pipe_config->ips_enabled = i915_enable_ips &&
4144 hsw_crtc_supports_ips(crtc) &&
4145 pipe_config->pipe_bpp <= 24;
4146 }
4147
4148 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4149 struct intel_crtc_config *pipe_config)
4150 {
4151 struct drm_device *dev = crtc->base.dev;
4152 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4153
4154 if (HAS_PCH_SPLIT(dev)) {
4155 /* FDI link clock is fixed at 2.7G */
4156 if (pipe_config->requested_mode.clock * 3
4157 > IRONLAKE_FDI_FREQ * 4)
4158 return -EINVAL;
4159 }
4160
4161 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4162 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4163 */
4164 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4165 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4166 return -EINVAL;
4167
4168 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4169 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4170 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4171 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4172 * for lvds. */
4173 pipe_config->pipe_bpp = 8*3;
4174 }
4175
4176 if (HAS_IPS(dev))
4177 hsw_compute_ips_config(crtc, pipe_config);
4178
4179 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4180 * clock survives for now. */
4181 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4182 pipe_config->shared_dpll = crtc->config.shared_dpll;
4183
4184 if (pipe_config->has_pch_encoder)
4185 return ironlake_fdi_compute_config(crtc, pipe_config);
4186
4187 return 0;
4188 }
4189
4190 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4191 {
4192 return 400000; /* FIXME */
4193 }
4194
4195 static int i945_get_display_clock_speed(struct drm_device *dev)
4196 {
4197 return 400000;
4198 }
4199
4200 static int i915_get_display_clock_speed(struct drm_device *dev)
4201 {
4202 return 333000;
4203 }
4204
4205 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4206 {
4207 return 200000;
4208 }
4209
4210 static int pnv_get_display_clock_speed(struct drm_device *dev)
4211 {
4212 u16 gcfgc = 0;
4213
4214 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4215
4216 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4217 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4218 return 267000;
4219 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4220 return 333000;
4221 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4222 return 444000;
4223 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4224 return 200000;
4225 default:
4226 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4227 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4228 return 133000;
4229 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4230 return 167000;
4231 }
4232 }
4233
4234 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4235 {
4236 u16 gcfgc = 0;
4237
4238 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4239
4240 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4241 return 133000;
4242 else {
4243 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4244 case GC_DISPLAY_CLOCK_333_MHZ:
4245 return 333000;
4246 default:
4247 case GC_DISPLAY_CLOCK_190_200_MHZ:
4248 return 190000;
4249 }
4250 }
4251 }
4252
4253 static int i865_get_display_clock_speed(struct drm_device *dev)
4254 {
4255 return 266000;
4256 }
4257
4258 static int i855_get_display_clock_speed(struct drm_device *dev)
4259 {
4260 u16 hpllcc = 0;
4261 /* Assume that the hardware is in the high speed state. This
4262 * should be the default.
4263 */
4264 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4265 case GC_CLOCK_133_200:
4266 case GC_CLOCK_100_200:
4267 return 200000;
4268 case GC_CLOCK_166_250:
4269 return 250000;
4270 case GC_CLOCK_100_133:
4271 return 133000;
4272 }
4273
4274 /* Shouldn't happen */
4275 return 0;
4276 }
4277
4278 static int i830_get_display_clock_speed(struct drm_device *dev)
4279 {
4280 return 133000;
4281 }
4282
4283 static void
4284 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4285 {
4286 while (*num > DATA_LINK_M_N_MASK ||
4287 *den > DATA_LINK_M_N_MASK) {
4288 *num >>= 1;
4289 *den >>= 1;
4290 }
4291 }
4292
4293 static void compute_m_n(unsigned int m, unsigned int n,
4294 uint32_t *ret_m, uint32_t *ret_n)
4295 {
4296 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4297 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4298 intel_reduce_m_n_ratio(ret_m, ret_n);
4299 }
4300
4301 void
4302 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4303 int pixel_clock, int link_clock,
4304 struct intel_link_m_n *m_n)
4305 {
4306 m_n->tu = 64;
4307
4308 compute_m_n(bits_per_pixel * pixel_clock,
4309 link_clock * nlanes * 8,
4310 &m_n->gmch_m, &m_n->gmch_n);
4311
4312 compute_m_n(pixel_clock, link_clock,
4313 &m_n->link_m, &m_n->link_n);
4314 }
4315
4316 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4317 {
4318 if (i915_panel_use_ssc >= 0)
4319 return i915_panel_use_ssc != 0;
4320 return dev_priv->vbt.lvds_use_ssc
4321 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4322 }
4323
4324 static int vlv_get_refclk(struct drm_crtc *crtc)
4325 {
4326 struct drm_device *dev = crtc->dev;
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 int refclk = 27000; /* for DP & HDMI */
4329
4330 return 100000; /* only one validated so far */
4331
4332 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4333 refclk = 96000;
4334 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4335 if (intel_panel_use_ssc(dev_priv))
4336 refclk = 100000;
4337 else
4338 refclk = 96000;
4339 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4340 refclk = 100000;
4341 }
4342
4343 return refclk;
4344 }
4345
4346 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4347 {
4348 struct drm_device *dev = crtc->dev;
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 int refclk;
4351
4352 if (IS_VALLEYVIEW(dev)) {
4353 refclk = vlv_get_refclk(crtc);
4354 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4355 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4356 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4357 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4358 refclk / 1000);
4359 } else if (!IS_GEN2(dev)) {
4360 refclk = 96000;
4361 } else {
4362 refclk = 48000;
4363 }
4364
4365 return refclk;
4366 }
4367
4368 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4369 {
4370 return (1 << dpll->n) << 16 | dpll->m2;
4371 }
4372
4373 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4374 {
4375 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4376 }
4377
4378 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4379 intel_clock_t *reduced_clock)
4380 {
4381 struct drm_device *dev = crtc->base.dev;
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 int pipe = crtc->pipe;
4384 u32 fp, fp2 = 0;
4385
4386 if (IS_PINEVIEW(dev)) {
4387 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4388 if (reduced_clock)
4389 fp2 = pnv_dpll_compute_fp(reduced_clock);
4390 } else {
4391 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4392 if (reduced_clock)
4393 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4394 }
4395
4396 I915_WRITE(FP0(pipe), fp);
4397 crtc->config.dpll_hw_state.fp0 = fp;
4398
4399 crtc->lowfreq_avail = false;
4400 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4401 reduced_clock && i915_powersave) {
4402 I915_WRITE(FP1(pipe), fp2);
4403 crtc->config.dpll_hw_state.fp1 = fp2;
4404 crtc->lowfreq_avail = true;
4405 } else {
4406 I915_WRITE(FP1(pipe), fp);
4407 crtc->config.dpll_hw_state.fp1 = fp;
4408 }
4409 }
4410
4411 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4412 {
4413 u32 reg_val;
4414
4415 /*
4416 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4417 * and set it to a reasonable value instead.
4418 */
4419 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4420 reg_val &= 0xffffff00;
4421 reg_val |= 0x00000030;
4422 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4423
4424 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4425 reg_val &= 0x8cffffff;
4426 reg_val = 0x8c000000;
4427 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4428
4429 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4430 reg_val &= 0xffffff00;
4431 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4432
4433 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4434 reg_val &= 0x00ffffff;
4435 reg_val |= 0xb0000000;
4436 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4437 }
4438
4439 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4440 struct intel_link_m_n *m_n)
4441 {
4442 struct drm_device *dev = crtc->base.dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444 int pipe = crtc->pipe;
4445
4446 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4447 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4448 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4449 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4450 }
4451
4452 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4453 struct intel_link_m_n *m_n)
4454 {
4455 struct drm_device *dev = crtc->base.dev;
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457 int pipe = crtc->pipe;
4458 enum transcoder transcoder = crtc->config.cpu_transcoder;
4459
4460 if (INTEL_INFO(dev)->gen >= 5) {
4461 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4462 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4463 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4464 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4465 } else {
4466 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4467 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4468 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4469 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4470 }
4471 }
4472
4473 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4474 {
4475 if (crtc->config.has_pch_encoder)
4476 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4477 else
4478 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4479 }
4480
4481 static void vlv_update_pll(struct intel_crtc *crtc)
4482 {
4483 struct drm_device *dev = crtc->base.dev;
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485 int pipe = crtc->pipe;
4486 u32 dpll, mdiv;
4487 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4488 u32 coreclk, reg_val, dpll_md;
4489
4490 mutex_lock(&dev_priv->dpio_lock);
4491
4492 bestn = crtc->config.dpll.n;
4493 bestm1 = crtc->config.dpll.m1;
4494 bestm2 = crtc->config.dpll.m2;
4495 bestp1 = crtc->config.dpll.p1;
4496 bestp2 = crtc->config.dpll.p2;
4497
4498 /* See eDP HDMI DPIO driver vbios notes doc */
4499
4500 /* PLL B needs special handling */
4501 if (pipe)
4502 vlv_pllb_recal_opamp(dev_priv);
4503
4504 /* Set up Tx target for periodic Rcomp update */
4505 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4506
4507 /* Disable target IRef on PLL */
4508 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4509 reg_val &= 0x00ffffff;
4510 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4511
4512 /* Disable fast lock */
4513 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4514
4515 /* Set idtafcrecal before PLL is enabled */
4516 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4517 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4518 mdiv |= ((bestn << DPIO_N_SHIFT));
4519 mdiv |= (1 << DPIO_K_SHIFT);
4520
4521 /*
4522 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4523 * but we don't support that).
4524 * Note: don't use the DAC post divider as it seems unstable.
4525 */
4526 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4527 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4528
4529 mdiv |= DPIO_ENABLE_CALIBRATION;
4530 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4531
4532 /* Set HBR and RBR LPF coefficients */
4533 if (crtc->config.port_clock == 162000 ||
4534 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4535 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4536 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4537 0x009f0003);
4538 else
4539 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4540 0x00d0000f);
4541
4542 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4543 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4544 /* Use SSC source */
4545 if (!pipe)
4546 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4547 0x0df40000);
4548 else
4549 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4550 0x0df70000);
4551 } else { /* HDMI or VGA */
4552 /* Use bend source */
4553 if (!pipe)
4554 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4555 0x0df70000);
4556 else
4557 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4558 0x0df40000);
4559 }
4560
4561 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4562 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4563 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4564 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4565 coreclk |= 0x01000000;
4566 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4567
4568 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4569
4570 /* Enable DPIO clock input */
4571 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4572 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4573 /* We should never disable this, set it here for state tracking */
4574 if (pipe == PIPE_B)
4575 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4576 dpll |= DPLL_VCO_ENABLE;
4577 crtc->config.dpll_hw_state.dpll = dpll;
4578
4579 dpll_md = (crtc->config.pixel_multiplier - 1)
4580 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4581 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4582
4583 if (crtc->config.has_dp_encoder)
4584 intel_dp_set_m_n(crtc);
4585
4586 mutex_unlock(&dev_priv->dpio_lock);
4587 }
4588
4589 static void i9xx_update_pll(struct intel_crtc *crtc,
4590 intel_clock_t *reduced_clock,
4591 int num_connectors)
4592 {
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 u32 dpll;
4596 bool is_sdvo;
4597 struct dpll *clock = &crtc->config.dpll;
4598
4599 i9xx_update_pll_dividers(crtc, reduced_clock);
4600
4601 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4602 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4603
4604 dpll = DPLL_VGA_MODE_DIS;
4605
4606 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4607 dpll |= DPLLB_MODE_LVDS;
4608 else
4609 dpll |= DPLLB_MODE_DAC_SERIAL;
4610
4611 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4612 dpll |= (crtc->config.pixel_multiplier - 1)
4613 << SDVO_MULTIPLIER_SHIFT_HIRES;
4614 }
4615
4616 if (is_sdvo)
4617 dpll |= DPLL_SDVO_HIGH_SPEED;
4618
4619 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4620 dpll |= DPLL_SDVO_HIGH_SPEED;
4621
4622 /* compute bitmask from p1 value */
4623 if (IS_PINEVIEW(dev))
4624 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4625 else {
4626 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4627 if (IS_G4X(dev) && reduced_clock)
4628 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4629 }
4630 switch (clock->p2) {
4631 case 5:
4632 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4633 break;
4634 case 7:
4635 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4636 break;
4637 case 10:
4638 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4639 break;
4640 case 14:
4641 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4642 break;
4643 }
4644 if (INTEL_INFO(dev)->gen >= 4)
4645 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4646
4647 if (crtc->config.sdvo_tv_clock)
4648 dpll |= PLL_REF_INPUT_TVCLKINBC;
4649 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4650 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4651 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4652 else
4653 dpll |= PLL_REF_INPUT_DREFCLK;
4654
4655 dpll |= DPLL_VCO_ENABLE;
4656 crtc->config.dpll_hw_state.dpll = dpll;
4657
4658 if (INTEL_INFO(dev)->gen >= 4) {
4659 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4660 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4661 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4662 }
4663
4664 if (crtc->config.has_dp_encoder)
4665 intel_dp_set_m_n(crtc);
4666 }
4667
4668 static void i8xx_update_pll(struct intel_crtc *crtc,
4669 intel_clock_t *reduced_clock,
4670 int num_connectors)
4671 {
4672 struct drm_device *dev = crtc->base.dev;
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674 u32 dpll;
4675 struct dpll *clock = &crtc->config.dpll;
4676
4677 i9xx_update_pll_dividers(crtc, reduced_clock);
4678
4679 dpll = DPLL_VGA_MODE_DIS;
4680
4681 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4682 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4683 } else {
4684 if (clock->p1 == 2)
4685 dpll |= PLL_P1_DIVIDE_BY_TWO;
4686 else
4687 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4688 if (clock->p2 == 4)
4689 dpll |= PLL_P2_DIVIDE_BY_4;
4690 }
4691
4692 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4693 dpll |= DPLL_DVO_2X_MODE;
4694
4695 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4696 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4697 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4698 else
4699 dpll |= PLL_REF_INPUT_DREFCLK;
4700
4701 dpll |= DPLL_VCO_ENABLE;
4702 crtc->config.dpll_hw_state.dpll = dpll;
4703 }
4704
4705 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4706 {
4707 struct drm_device *dev = intel_crtc->base.dev;
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4709 enum pipe pipe = intel_crtc->pipe;
4710 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4711 struct drm_display_mode *adjusted_mode =
4712 &intel_crtc->config.adjusted_mode;
4713 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4714 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4715
4716 /* We need to be careful not to changed the adjusted mode, for otherwise
4717 * the hw state checker will get angry at the mismatch. */
4718 crtc_vtotal = adjusted_mode->crtc_vtotal;
4719 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4720
4721 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4722 /* the chip adds 2 halflines automatically */
4723 crtc_vtotal -= 1;
4724 crtc_vblank_end -= 1;
4725 vsyncshift = adjusted_mode->crtc_hsync_start
4726 - adjusted_mode->crtc_htotal / 2;
4727 } else {
4728 vsyncshift = 0;
4729 }
4730
4731 if (INTEL_INFO(dev)->gen > 3)
4732 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4733
4734 I915_WRITE(HTOTAL(cpu_transcoder),
4735 (adjusted_mode->crtc_hdisplay - 1) |
4736 ((adjusted_mode->crtc_htotal - 1) << 16));
4737 I915_WRITE(HBLANK(cpu_transcoder),
4738 (adjusted_mode->crtc_hblank_start - 1) |
4739 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4740 I915_WRITE(HSYNC(cpu_transcoder),
4741 (adjusted_mode->crtc_hsync_start - 1) |
4742 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4743
4744 I915_WRITE(VTOTAL(cpu_transcoder),
4745 (adjusted_mode->crtc_vdisplay - 1) |
4746 ((crtc_vtotal - 1) << 16));
4747 I915_WRITE(VBLANK(cpu_transcoder),
4748 (adjusted_mode->crtc_vblank_start - 1) |
4749 ((crtc_vblank_end - 1) << 16));
4750 I915_WRITE(VSYNC(cpu_transcoder),
4751 (adjusted_mode->crtc_vsync_start - 1) |
4752 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4753
4754 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4755 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4756 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4757 * bits. */
4758 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4759 (pipe == PIPE_B || pipe == PIPE_C))
4760 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4761
4762 /* pipesrc controls the size that is scaled from, which should
4763 * always be the user's requested size.
4764 */
4765 I915_WRITE(PIPESRC(pipe),
4766 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4767 }
4768
4769 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4770 struct intel_crtc_config *pipe_config)
4771 {
4772 struct drm_device *dev = crtc->base.dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4775 uint32_t tmp;
4776
4777 tmp = I915_READ(HTOTAL(cpu_transcoder));
4778 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4779 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4780 tmp = I915_READ(HBLANK(cpu_transcoder));
4781 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4782 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4783 tmp = I915_READ(HSYNC(cpu_transcoder));
4784 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4785 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4786
4787 tmp = I915_READ(VTOTAL(cpu_transcoder));
4788 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4789 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4790 tmp = I915_READ(VBLANK(cpu_transcoder));
4791 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4792 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4793 tmp = I915_READ(VSYNC(cpu_transcoder));
4794 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4795 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4796
4797 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4798 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4799 pipe_config->adjusted_mode.crtc_vtotal += 1;
4800 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4801 }
4802
4803 tmp = I915_READ(PIPESRC(crtc->pipe));
4804 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4805 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4806 }
4807
4808 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4809 struct intel_crtc_config *pipe_config)
4810 {
4811 struct drm_crtc *crtc = &intel_crtc->base;
4812
4813 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4814 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4815 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4816 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4817
4818 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4819 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4820 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4821 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4822
4823 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4824
4825 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4826 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4827 }
4828
4829 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4830 {
4831 struct drm_device *dev = intel_crtc->base.dev;
4832 struct drm_i915_private *dev_priv = dev->dev_private;
4833 uint32_t pipeconf;
4834
4835 pipeconf = 0;
4836
4837 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4838 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4839 pipeconf |= PIPECONF_ENABLE;
4840
4841 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4842 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4843 * core speed.
4844 *
4845 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4846 * pipe == 0 check?
4847 */
4848 if (intel_crtc->config.requested_mode.clock >
4849 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4850 pipeconf |= PIPECONF_DOUBLE_WIDE;
4851 }
4852
4853 /* only g4x and later have fancy bpc/dither controls */
4854 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4855 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4856 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4857 pipeconf |= PIPECONF_DITHER_EN |
4858 PIPECONF_DITHER_TYPE_SP;
4859
4860 switch (intel_crtc->config.pipe_bpp) {
4861 case 18:
4862 pipeconf |= PIPECONF_6BPC;
4863 break;
4864 case 24:
4865 pipeconf |= PIPECONF_8BPC;
4866 break;
4867 case 30:
4868 pipeconf |= PIPECONF_10BPC;
4869 break;
4870 default:
4871 /* Case prevented by intel_choose_pipe_bpp_dither. */
4872 BUG();
4873 }
4874 }
4875
4876 if (HAS_PIPE_CXSR(dev)) {
4877 if (intel_crtc->lowfreq_avail) {
4878 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4879 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4880 } else {
4881 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4882 }
4883 }
4884
4885 if (!IS_GEN2(dev) &&
4886 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4887 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4888 else
4889 pipeconf |= PIPECONF_PROGRESSIVE;
4890
4891 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4892 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4893
4894 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4895 POSTING_READ(PIPECONF(intel_crtc->pipe));
4896 }
4897
4898 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4899 int x, int y,
4900 struct drm_framebuffer *fb)
4901 {
4902 struct drm_device *dev = crtc->dev;
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4906 int pipe = intel_crtc->pipe;
4907 int plane = intel_crtc->plane;
4908 int refclk, num_connectors = 0;
4909 intel_clock_t clock, reduced_clock;
4910 u32 dspcntr;
4911 bool ok, has_reduced_clock = false;
4912 bool is_lvds = false;
4913 struct intel_encoder *encoder;
4914 const intel_limit_t *limit;
4915 int ret;
4916
4917 for_each_encoder_on_crtc(dev, crtc, encoder) {
4918 switch (encoder->type) {
4919 case INTEL_OUTPUT_LVDS:
4920 is_lvds = true;
4921 break;
4922 }
4923
4924 num_connectors++;
4925 }
4926
4927 refclk = i9xx_get_refclk(crtc, num_connectors);
4928
4929 /*
4930 * Returns a set of divisors for the desired target clock with the given
4931 * refclk, or FALSE. The returned values represent the clock equation:
4932 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4933 */
4934 limit = intel_limit(crtc, refclk);
4935 ok = dev_priv->display.find_dpll(limit, crtc,
4936 intel_crtc->config.port_clock,
4937 refclk, NULL, &clock);
4938 if (!ok && !intel_crtc->config.clock_set) {
4939 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4940 return -EINVAL;
4941 }
4942
4943 if (is_lvds && dev_priv->lvds_downclock_avail) {
4944 /*
4945 * Ensure we match the reduced clock's P to the target clock.
4946 * If the clocks don't match, we can't switch the display clock
4947 * by using the FP0/FP1. In such case we will disable the LVDS
4948 * downclock feature.
4949 */
4950 has_reduced_clock =
4951 dev_priv->display.find_dpll(limit, crtc,
4952 dev_priv->lvds_downclock,
4953 refclk, &clock,
4954 &reduced_clock);
4955 }
4956 /* Compat-code for transition, will disappear. */
4957 if (!intel_crtc->config.clock_set) {
4958 intel_crtc->config.dpll.n = clock.n;
4959 intel_crtc->config.dpll.m1 = clock.m1;
4960 intel_crtc->config.dpll.m2 = clock.m2;
4961 intel_crtc->config.dpll.p1 = clock.p1;
4962 intel_crtc->config.dpll.p2 = clock.p2;
4963 }
4964
4965 if (IS_GEN2(dev))
4966 i8xx_update_pll(intel_crtc,
4967 has_reduced_clock ? &reduced_clock : NULL,
4968 num_connectors);
4969 else if (IS_VALLEYVIEW(dev))
4970 vlv_update_pll(intel_crtc);
4971 else
4972 i9xx_update_pll(intel_crtc,
4973 has_reduced_clock ? &reduced_clock : NULL,
4974 num_connectors);
4975
4976 /* Set up the display plane register */
4977 dspcntr = DISPPLANE_GAMMA_ENABLE;
4978
4979 if (!IS_VALLEYVIEW(dev)) {
4980 if (pipe == 0)
4981 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4982 else
4983 dspcntr |= DISPPLANE_SEL_PIPE_B;
4984 }
4985
4986 intel_set_pipe_timings(intel_crtc);
4987
4988 /* pipesrc and dspsize control the size that is scaled from,
4989 * which should always be the user's requested size.
4990 */
4991 I915_WRITE(DSPSIZE(plane),
4992 ((mode->vdisplay - 1) << 16) |
4993 (mode->hdisplay - 1));
4994 I915_WRITE(DSPPOS(plane), 0);
4995
4996 i9xx_set_pipeconf(intel_crtc);
4997
4998 I915_WRITE(DSPCNTR(plane), dspcntr);
4999 POSTING_READ(DSPCNTR(plane));
5000
5001 ret = intel_pipe_set_base(crtc, x, y, fb);
5002
5003 intel_update_watermarks(dev);
5004
5005 return ret;
5006 }
5007
5008 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5009 struct intel_crtc_config *pipe_config)
5010 {
5011 struct drm_device *dev = crtc->base.dev;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 uint32_t tmp;
5014
5015 tmp = I915_READ(PFIT_CONTROL);
5016 if (!(tmp & PFIT_ENABLE))
5017 return;
5018
5019 /* Check whether the pfit is attached to our pipe. */
5020 if (INTEL_INFO(dev)->gen < 4) {
5021 if (crtc->pipe != PIPE_B)
5022 return;
5023 } else {
5024 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5025 return;
5026 }
5027
5028 pipe_config->gmch_pfit.control = tmp;
5029 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5030 if (INTEL_INFO(dev)->gen < 5)
5031 pipe_config->gmch_pfit.lvds_border_bits =
5032 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5033 }
5034
5035 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5036 struct intel_crtc_config *pipe_config)
5037 {
5038 struct drm_device *dev = crtc->base.dev;
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 int pipe = pipe_config->cpu_transcoder;
5041 intel_clock_t clock;
5042 u32 mdiv;
5043 int refclk = 100000;
5044
5045 mutex_lock(&dev_priv->dpio_lock);
5046 mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe));
5047 mutex_unlock(&dev_priv->dpio_lock);
5048
5049 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5050 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5051 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5052 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5053 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5054
5055 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5056 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5057
5058 pipe_config->adjusted_mode.clock = clock.dot / 10;
5059 }
5060
5061 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5062 struct intel_crtc_config *pipe_config)
5063 {
5064 struct drm_device *dev = crtc->base.dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066 uint32_t tmp;
5067
5068 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5069 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5070
5071 tmp = I915_READ(PIPECONF(crtc->pipe));
5072 if (!(tmp & PIPECONF_ENABLE))
5073 return false;
5074
5075 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5076 switch (tmp & PIPECONF_BPC_MASK) {
5077 case PIPECONF_6BPC:
5078 pipe_config->pipe_bpp = 18;
5079 break;
5080 case PIPECONF_8BPC:
5081 pipe_config->pipe_bpp = 24;
5082 break;
5083 case PIPECONF_10BPC:
5084 pipe_config->pipe_bpp = 30;
5085 break;
5086 default:
5087 break;
5088 }
5089 }
5090
5091 intel_get_pipe_timings(crtc, pipe_config);
5092
5093 i9xx_get_pfit_config(crtc, pipe_config);
5094
5095 if (INTEL_INFO(dev)->gen >= 4) {
5096 tmp = I915_READ(DPLL_MD(crtc->pipe));
5097 pipe_config->pixel_multiplier =
5098 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5099 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5100 pipe_config->dpll_hw_state.dpll_md = tmp;
5101 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5102 tmp = I915_READ(DPLL(crtc->pipe));
5103 pipe_config->pixel_multiplier =
5104 ((tmp & SDVO_MULTIPLIER_MASK)
5105 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5106 } else {
5107 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5108 * port and will be fixed up in the encoder->get_config
5109 * function. */
5110 pipe_config->pixel_multiplier = 1;
5111 }
5112 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5113 if (!IS_VALLEYVIEW(dev)) {
5114 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5115 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5116 } else {
5117 /* Mask out read-only status bits. */
5118 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5119 DPLL_PORTC_READY_MASK |
5120 DPLL_PORTB_READY_MASK);
5121 }
5122
5123 return true;
5124 }
5125
5126 static void ironlake_init_pch_refclk(struct drm_device *dev)
5127 {
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct drm_mode_config *mode_config = &dev->mode_config;
5130 struct intel_encoder *encoder;
5131 u32 val, final;
5132 bool has_lvds = false;
5133 bool has_cpu_edp = false;
5134 bool has_panel = false;
5135 bool has_ck505 = false;
5136 bool can_ssc = false;
5137
5138 /* We need to take the global config into account */
5139 list_for_each_entry(encoder, &mode_config->encoder_list,
5140 base.head) {
5141 switch (encoder->type) {
5142 case INTEL_OUTPUT_LVDS:
5143 has_panel = true;
5144 has_lvds = true;
5145 break;
5146 case INTEL_OUTPUT_EDP:
5147 has_panel = true;
5148 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5149 has_cpu_edp = true;
5150 break;
5151 }
5152 }
5153
5154 if (HAS_PCH_IBX(dev)) {
5155 has_ck505 = dev_priv->vbt.display_clock_mode;
5156 can_ssc = has_ck505;
5157 } else {
5158 has_ck505 = false;
5159 can_ssc = true;
5160 }
5161
5162 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5163 has_panel, has_lvds, has_ck505);
5164
5165 /* Ironlake: try to setup display ref clock before DPLL
5166 * enabling. This is only under driver's control after
5167 * PCH B stepping, previous chipset stepping should be
5168 * ignoring this setting.
5169 */
5170 val = I915_READ(PCH_DREF_CONTROL);
5171
5172 /* As we must carefully and slowly disable/enable each source in turn,
5173 * compute the final state we want first and check if we need to
5174 * make any changes at all.
5175 */
5176 final = val;
5177 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5178 if (has_ck505)
5179 final |= DREF_NONSPREAD_CK505_ENABLE;
5180 else
5181 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5182
5183 final &= ~DREF_SSC_SOURCE_MASK;
5184 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5185 final &= ~DREF_SSC1_ENABLE;
5186
5187 if (has_panel) {
5188 final |= DREF_SSC_SOURCE_ENABLE;
5189
5190 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5191 final |= DREF_SSC1_ENABLE;
5192
5193 if (has_cpu_edp) {
5194 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5195 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5196 else
5197 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5198 } else
5199 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5200 } else {
5201 final |= DREF_SSC_SOURCE_DISABLE;
5202 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5203 }
5204
5205 if (final == val)
5206 return;
5207
5208 /* Always enable nonspread source */
5209 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5210
5211 if (has_ck505)
5212 val |= DREF_NONSPREAD_CK505_ENABLE;
5213 else
5214 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5215
5216 if (has_panel) {
5217 val &= ~DREF_SSC_SOURCE_MASK;
5218 val |= DREF_SSC_SOURCE_ENABLE;
5219
5220 /* SSC must be turned on before enabling the CPU output */
5221 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5222 DRM_DEBUG_KMS("Using SSC on panel\n");
5223 val |= DREF_SSC1_ENABLE;
5224 } else
5225 val &= ~DREF_SSC1_ENABLE;
5226
5227 /* Get SSC going before enabling the outputs */
5228 I915_WRITE(PCH_DREF_CONTROL, val);
5229 POSTING_READ(PCH_DREF_CONTROL);
5230 udelay(200);
5231
5232 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5233
5234 /* Enable CPU source on CPU attached eDP */
5235 if (has_cpu_edp) {
5236 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5237 DRM_DEBUG_KMS("Using SSC on eDP\n");
5238 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5239 }
5240 else
5241 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5242 } else
5243 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5244
5245 I915_WRITE(PCH_DREF_CONTROL, val);
5246 POSTING_READ(PCH_DREF_CONTROL);
5247 udelay(200);
5248 } else {
5249 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5250
5251 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5252
5253 /* Turn off CPU output */
5254 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5255
5256 I915_WRITE(PCH_DREF_CONTROL, val);
5257 POSTING_READ(PCH_DREF_CONTROL);
5258 udelay(200);
5259
5260 /* Turn off the SSC source */
5261 val &= ~DREF_SSC_SOURCE_MASK;
5262 val |= DREF_SSC_SOURCE_DISABLE;
5263
5264 /* Turn off SSC1 */
5265 val &= ~DREF_SSC1_ENABLE;
5266
5267 I915_WRITE(PCH_DREF_CONTROL, val);
5268 POSTING_READ(PCH_DREF_CONTROL);
5269 udelay(200);
5270 }
5271
5272 BUG_ON(val != final);
5273 }
5274
5275 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5276 {
5277 uint32_t tmp;
5278
5279 tmp = I915_READ(SOUTH_CHICKEN2);
5280 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5281 I915_WRITE(SOUTH_CHICKEN2, tmp);
5282
5283 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5284 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5285 DRM_ERROR("FDI mPHY reset assert timeout\n");
5286
5287 tmp = I915_READ(SOUTH_CHICKEN2);
5288 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5289 I915_WRITE(SOUTH_CHICKEN2, tmp);
5290
5291 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5292 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5293 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5294 }
5295
5296 /* WaMPhyProgramming:hsw */
5297 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5298 {
5299 uint32_t tmp;
5300
5301 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5302 tmp &= ~(0xFF << 24);
5303 tmp |= (0x12 << 24);
5304 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5305
5306 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5307 tmp |= (1 << 11);
5308 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5309
5310 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5311 tmp |= (1 << 11);
5312 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5313
5314 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5315 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5316 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5317
5318 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5319 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5320 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5321
5322 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5323 tmp &= ~(7 << 13);
5324 tmp |= (5 << 13);
5325 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5326
5327 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5328 tmp &= ~(7 << 13);
5329 tmp |= (5 << 13);
5330 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5331
5332 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5333 tmp &= ~0xFF;
5334 tmp |= 0x1C;
5335 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5336
5337 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5338 tmp &= ~0xFF;
5339 tmp |= 0x1C;
5340 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5341
5342 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5343 tmp &= ~(0xFF << 16);
5344 tmp |= (0x1C << 16);
5345 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5346
5347 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5348 tmp &= ~(0xFF << 16);
5349 tmp |= (0x1C << 16);
5350 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5351
5352 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5353 tmp |= (1 << 27);
5354 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5355
5356 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5357 tmp |= (1 << 27);
5358 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5359
5360 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5361 tmp &= ~(0xF << 28);
5362 tmp |= (4 << 28);
5363 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5364
5365 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5366 tmp &= ~(0xF << 28);
5367 tmp |= (4 << 28);
5368 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5369 }
5370
5371 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5372 * Programming" based on the parameters passed:
5373 * - Sequence to enable CLKOUT_DP
5374 * - Sequence to enable CLKOUT_DP without spread
5375 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5376 */
5377 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5378 bool with_fdi)
5379 {
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 uint32_t reg, tmp;
5382
5383 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5384 with_spread = true;
5385 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5386 with_fdi, "LP PCH doesn't have FDI\n"))
5387 with_fdi = false;
5388
5389 mutex_lock(&dev_priv->dpio_lock);
5390
5391 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5392 tmp &= ~SBI_SSCCTL_DISABLE;
5393 tmp |= SBI_SSCCTL_PATHALT;
5394 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5395
5396 udelay(24);
5397
5398 if (with_spread) {
5399 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5400 tmp &= ~SBI_SSCCTL_PATHALT;
5401 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5402
5403 if (with_fdi) {
5404 lpt_reset_fdi_mphy(dev_priv);
5405 lpt_program_fdi_mphy(dev_priv);
5406 }
5407 }
5408
5409 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5410 SBI_GEN0 : SBI_DBUFF0;
5411 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5412 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5413 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5414
5415 mutex_unlock(&dev_priv->dpio_lock);
5416 }
5417
5418 /* Sequence to disable CLKOUT_DP */
5419 static void lpt_disable_clkout_dp(struct drm_device *dev)
5420 {
5421 struct drm_i915_private *dev_priv = dev->dev_private;
5422 uint32_t reg, tmp;
5423
5424 mutex_lock(&dev_priv->dpio_lock);
5425
5426 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5427 SBI_GEN0 : SBI_DBUFF0;
5428 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5429 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5430 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5431
5432 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5433 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5434 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5435 tmp |= SBI_SSCCTL_PATHALT;
5436 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5437 udelay(32);
5438 }
5439 tmp |= SBI_SSCCTL_DISABLE;
5440 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5441 }
5442
5443 mutex_unlock(&dev_priv->dpio_lock);
5444 }
5445
5446 static void lpt_init_pch_refclk(struct drm_device *dev)
5447 {
5448 struct drm_mode_config *mode_config = &dev->mode_config;
5449 struct intel_encoder *encoder;
5450 bool has_vga = false;
5451
5452 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5453 switch (encoder->type) {
5454 case INTEL_OUTPUT_ANALOG:
5455 has_vga = true;
5456 break;
5457 }
5458 }
5459
5460 if (has_vga)
5461 lpt_enable_clkout_dp(dev, true, true);
5462 else
5463 lpt_disable_clkout_dp(dev);
5464 }
5465
5466 /*
5467 * Initialize reference clocks when the driver loads
5468 */
5469 void intel_init_pch_refclk(struct drm_device *dev)
5470 {
5471 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5472 ironlake_init_pch_refclk(dev);
5473 else if (HAS_PCH_LPT(dev))
5474 lpt_init_pch_refclk(dev);
5475 }
5476
5477 static int ironlake_get_refclk(struct drm_crtc *crtc)
5478 {
5479 struct drm_device *dev = crtc->dev;
5480 struct drm_i915_private *dev_priv = dev->dev_private;
5481 struct intel_encoder *encoder;
5482 int num_connectors = 0;
5483 bool is_lvds = false;
5484
5485 for_each_encoder_on_crtc(dev, crtc, encoder) {
5486 switch (encoder->type) {
5487 case INTEL_OUTPUT_LVDS:
5488 is_lvds = true;
5489 break;
5490 }
5491 num_connectors++;
5492 }
5493
5494 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5495 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5496 dev_priv->vbt.lvds_ssc_freq);
5497 return dev_priv->vbt.lvds_ssc_freq * 1000;
5498 }
5499
5500 return 120000;
5501 }
5502
5503 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5504 {
5505 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 int pipe = intel_crtc->pipe;
5508 uint32_t val;
5509
5510 val = 0;
5511
5512 switch (intel_crtc->config.pipe_bpp) {
5513 case 18:
5514 val |= PIPECONF_6BPC;
5515 break;
5516 case 24:
5517 val |= PIPECONF_8BPC;
5518 break;
5519 case 30:
5520 val |= PIPECONF_10BPC;
5521 break;
5522 case 36:
5523 val |= PIPECONF_12BPC;
5524 break;
5525 default:
5526 /* Case prevented by intel_choose_pipe_bpp_dither. */
5527 BUG();
5528 }
5529
5530 if (intel_crtc->config.dither)
5531 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5532
5533 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5534 val |= PIPECONF_INTERLACED_ILK;
5535 else
5536 val |= PIPECONF_PROGRESSIVE;
5537
5538 if (intel_crtc->config.limited_color_range)
5539 val |= PIPECONF_COLOR_RANGE_SELECT;
5540
5541 I915_WRITE(PIPECONF(pipe), val);
5542 POSTING_READ(PIPECONF(pipe));
5543 }
5544
5545 /*
5546 * Set up the pipe CSC unit.
5547 *
5548 * Currently only full range RGB to limited range RGB conversion
5549 * is supported, but eventually this should handle various
5550 * RGB<->YCbCr scenarios as well.
5551 */
5552 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5553 {
5554 struct drm_device *dev = crtc->dev;
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5557 int pipe = intel_crtc->pipe;
5558 uint16_t coeff = 0x7800; /* 1.0 */
5559
5560 /*
5561 * TODO: Check what kind of values actually come out of the pipe
5562 * with these coeff/postoff values and adjust to get the best
5563 * accuracy. Perhaps we even need to take the bpc value into
5564 * consideration.
5565 */
5566
5567 if (intel_crtc->config.limited_color_range)
5568 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5569
5570 /*
5571 * GY/GU and RY/RU should be the other way around according
5572 * to BSpec, but reality doesn't agree. Just set them up in
5573 * a way that results in the correct picture.
5574 */
5575 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5576 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5577
5578 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5579 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5580
5581 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5582 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5583
5584 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5585 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5586 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5587
5588 if (INTEL_INFO(dev)->gen > 6) {
5589 uint16_t postoff = 0;
5590
5591 if (intel_crtc->config.limited_color_range)
5592 postoff = (16 * (1 << 12) / 255) & 0x1fff;
5593
5594 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5595 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5596 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5597
5598 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5599 } else {
5600 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5601
5602 if (intel_crtc->config.limited_color_range)
5603 mode |= CSC_BLACK_SCREEN_OFFSET;
5604
5605 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5606 }
5607 }
5608
5609 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5610 {
5611 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5613 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5614 uint32_t val;
5615
5616 val = 0;
5617
5618 if (intel_crtc->config.dither)
5619 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5620
5621 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5622 val |= PIPECONF_INTERLACED_ILK;
5623 else
5624 val |= PIPECONF_PROGRESSIVE;
5625
5626 I915_WRITE(PIPECONF(cpu_transcoder), val);
5627 POSTING_READ(PIPECONF(cpu_transcoder));
5628
5629 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5630 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5631 }
5632
5633 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5634 intel_clock_t *clock,
5635 bool *has_reduced_clock,
5636 intel_clock_t *reduced_clock)
5637 {
5638 struct drm_device *dev = crtc->dev;
5639 struct drm_i915_private *dev_priv = dev->dev_private;
5640 struct intel_encoder *intel_encoder;
5641 int refclk;
5642 const intel_limit_t *limit;
5643 bool ret, is_lvds = false;
5644
5645 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5646 switch (intel_encoder->type) {
5647 case INTEL_OUTPUT_LVDS:
5648 is_lvds = true;
5649 break;
5650 }
5651 }
5652
5653 refclk = ironlake_get_refclk(crtc);
5654
5655 /*
5656 * Returns a set of divisors for the desired target clock with the given
5657 * refclk, or FALSE. The returned values represent the clock equation:
5658 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5659 */
5660 limit = intel_limit(crtc, refclk);
5661 ret = dev_priv->display.find_dpll(limit, crtc,
5662 to_intel_crtc(crtc)->config.port_clock,
5663 refclk, NULL, clock);
5664 if (!ret)
5665 return false;
5666
5667 if (is_lvds && dev_priv->lvds_downclock_avail) {
5668 /*
5669 * Ensure we match the reduced clock's P to the target clock.
5670 * If the clocks don't match, we can't switch the display clock
5671 * by using the FP0/FP1. In such case we will disable the LVDS
5672 * downclock feature.
5673 */
5674 *has_reduced_clock =
5675 dev_priv->display.find_dpll(limit, crtc,
5676 dev_priv->lvds_downclock,
5677 refclk, clock,
5678 reduced_clock);
5679 }
5680
5681 return true;
5682 }
5683
5684 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5685 {
5686 /*
5687 * Account for spread spectrum to avoid
5688 * oversubscribing the link. Max center spread
5689 * is 2.5%; use 5% for safety's sake.
5690 */
5691 u32 bps = target_clock * bpp * 21 / 20;
5692 return bps / (link_bw * 8) + 1;
5693 }
5694
5695 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5696 {
5697 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5698 }
5699
5700 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5701 u32 *fp,
5702 intel_clock_t *reduced_clock, u32 *fp2)
5703 {
5704 struct drm_crtc *crtc = &intel_crtc->base;
5705 struct drm_device *dev = crtc->dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707 struct intel_encoder *intel_encoder;
5708 uint32_t dpll;
5709 int factor, num_connectors = 0;
5710 bool is_lvds = false, is_sdvo = false;
5711
5712 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5713 switch (intel_encoder->type) {
5714 case INTEL_OUTPUT_LVDS:
5715 is_lvds = true;
5716 break;
5717 case INTEL_OUTPUT_SDVO:
5718 case INTEL_OUTPUT_HDMI:
5719 is_sdvo = true;
5720 break;
5721 }
5722
5723 num_connectors++;
5724 }
5725
5726 /* Enable autotuning of the PLL clock (if permissible) */
5727 factor = 21;
5728 if (is_lvds) {
5729 if ((intel_panel_use_ssc(dev_priv) &&
5730 dev_priv->vbt.lvds_ssc_freq == 100) ||
5731 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5732 factor = 25;
5733 } else if (intel_crtc->config.sdvo_tv_clock)
5734 factor = 20;
5735
5736 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5737 *fp |= FP_CB_TUNE;
5738
5739 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5740 *fp2 |= FP_CB_TUNE;
5741
5742 dpll = 0;
5743
5744 if (is_lvds)
5745 dpll |= DPLLB_MODE_LVDS;
5746 else
5747 dpll |= DPLLB_MODE_DAC_SERIAL;
5748
5749 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5750 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5751
5752 if (is_sdvo)
5753 dpll |= DPLL_SDVO_HIGH_SPEED;
5754 if (intel_crtc->config.has_dp_encoder)
5755 dpll |= DPLL_SDVO_HIGH_SPEED;
5756
5757 /* compute bitmask from p1 value */
5758 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5759 /* also FPA1 */
5760 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5761
5762 switch (intel_crtc->config.dpll.p2) {
5763 case 5:
5764 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5765 break;
5766 case 7:
5767 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5768 break;
5769 case 10:
5770 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5771 break;
5772 case 14:
5773 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5774 break;
5775 }
5776
5777 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5778 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5779 else
5780 dpll |= PLL_REF_INPUT_DREFCLK;
5781
5782 return dpll | DPLL_VCO_ENABLE;
5783 }
5784
5785 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5786 int x, int y,
5787 struct drm_framebuffer *fb)
5788 {
5789 struct drm_device *dev = crtc->dev;
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5792 int pipe = intel_crtc->pipe;
5793 int plane = intel_crtc->plane;
5794 int num_connectors = 0;
5795 intel_clock_t clock, reduced_clock;
5796 u32 dpll = 0, fp = 0, fp2 = 0;
5797 bool ok, has_reduced_clock = false;
5798 bool is_lvds = false;
5799 struct intel_encoder *encoder;
5800 struct intel_shared_dpll *pll;
5801 int ret;
5802
5803 for_each_encoder_on_crtc(dev, crtc, encoder) {
5804 switch (encoder->type) {
5805 case INTEL_OUTPUT_LVDS:
5806 is_lvds = true;
5807 break;
5808 }
5809
5810 num_connectors++;
5811 }
5812
5813 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5814 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5815
5816 ok = ironlake_compute_clocks(crtc, &clock,
5817 &has_reduced_clock, &reduced_clock);
5818 if (!ok && !intel_crtc->config.clock_set) {
5819 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5820 return -EINVAL;
5821 }
5822 /* Compat-code for transition, will disappear. */
5823 if (!intel_crtc->config.clock_set) {
5824 intel_crtc->config.dpll.n = clock.n;
5825 intel_crtc->config.dpll.m1 = clock.m1;
5826 intel_crtc->config.dpll.m2 = clock.m2;
5827 intel_crtc->config.dpll.p1 = clock.p1;
5828 intel_crtc->config.dpll.p2 = clock.p2;
5829 }
5830
5831 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5832 if (intel_crtc->config.has_pch_encoder) {
5833 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5834 if (has_reduced_clock)
5835 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5836
5837 dpll = ironlake_compute_dpll(intel_crtc,
5838 &fp, &reduced_clock,
5839 has_reduced_clock ? &fp2 : NULL);
5840
5841 intel_crtc->config.dpll_hw_state.dpll = dpll;
5842 intel_crtc->config.dpll_hw_state.fp0 = fp;
5843 if (has_reduced_clock)
5844 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5845 else
5846 intel_crtc->config.dpll_hw_state.fp1 = fp;
5847
5848 pll = intel_get_shared_dpll(intel_crtc);
5849 if (pll == NULL) {
5850 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5851 pipe_name(pipe));
5852 return -EINVAL;
5853 }
5854 } else
5855 intel_put_shared_dpll(intel_crtc);
5856
5857 if (intel_crtc->config.has_dp_encoder)
5858 intel_dp_set_m_n(intel_crtc);
5859
5860 if (is_lvds && has_reduced_clock && i915_powersave)
5861 intel_crtc->lowfreq_avail = true;
5862 else
5863 intel_crtc->lowfreq_avail = false;
5864
5865 if (intel_crtc->config.has_pch_encoder) {
5866 pll = intel_crtc_to_shared_dpll(intel_crtc);
5867
5868 }
5869
5870 intel_set_pipe_timings(intel_crtc);
5871
5872 if (intel_crtc->config.has_pch_encoder) {
5873 intel_cpu_transcoder_set_m_n(intel_crtc,
5874 &intel_crtc->config.fdi_m_n);
5875 }
5876
5877 ironlake_set_pipeconf(crtc);
5878
5879 /* Set up the display plane register */
5880 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5881 POSTING_READ(DSPCNTR(plane));
5882
5883 ret = intel_pipe_set_base(crtc, x, y, fb);
5884
5885 intel_update_watermarks(dev);
5886
5887 return ret;
5888 }
5889
5890 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5891 struct intel_crtc_config *pipe_config)
5892 {
5893 struct drm_device *dev = crtc->base.dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 enum transcoder transcoder = pipe_config->cpu_transcoder;
5896
5897 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5898 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5899 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5900 & ~TU_SIZE_MASK;
5901 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5902 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5903 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5904 }
5905
5906 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5907 struct intel_crtc_config *pipe_config)
5908 {
5909 struct drm_device *dev = crtc->base.dev;
5910 struct drm_i915_private *dev_priv = dev->dev_private;
5911 uint32_t tmp;
5912
5913 tmp = I915_READ(PF_CTL(crtc->pipe));
5914
5915 if (tmp & PF_ENABLE) {
5916 pipe_config->pch_pfit.enabled = true;
5917 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5918 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5919
5920 /* We currently do not free assignements of panel fitters on
5921 * ivb/hsw (since we don't use the higher upscaling modes which
5922 * differentiates them) so just WARN about this case for now. */
5923 if (IS_GEN7(dev)) {
5924 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5925 PF_PIPE_SEL_IVB(crtc->pipe));
5926 }
5927 }
5928 }
5929
5930 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5931 struct intel_crtc_config *pipe_config)
5932 {
5933 struct drm_device *dev = crtc->base.dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 uint32_t tmp;
5936
5937 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5938 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5939
5940 tmp = I915_READ(PIPECONF(crtc->pipe));
5941 if (!(tmp & PIPECONF_ENABLE))
5942 return false;
5943
5944 switch (tmp & PIPECONF_BPC_MASK) {
5945 case PIPECONF_6BPC:
5946 pipe_config->pipe_bpp = 18;
5947 break;
5948 case PIPECONF_8BPC:
5949 pipe_config->pipe_bpp = 24;
5950 break;
5951 case PIPECONF_10BPC:
5952 pipe_config->pipe_bpp = 30;
5953 break;
5954 case PIPECONF_12BPC:
5955 pipe_config->pipe_bpp = 36;
5956 break;
5957 default:
5958 break;
5959 }
5960
5961 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5962 struct intel_shared_dpll *pll;
5963
5964 pipe_config->has_pch_encoder = true;
5965
5966 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5967 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5968 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5969
5970 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5971
5972 if (HAS_PCH_IBX(dev_priv->dev)) {
5973 pipe_config->shared_dpll =
5974 (enum intel_dpll_id) crtc->pipe;
5975 } else {
5976 tmp = I915_READ(PCH_DPLL_SEL);
5977 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5978 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5979 else
5980 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5981 }
5982
5983 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5984
5985 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5986 &pipe_config->dpll_hw_state));
5987
5988 tmp = pipe_config->dpll_hw_state.dpll;
5989 pipe_config->pixel_multiplier =
5990 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5991 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5992 } else {
5993 pipe_config->pixel_multiplier = 1;
5994 }
5995
5996 intel_get_pipe_timings(crtc, pipe_config);
5997
5998 ironlake_get_pfit_config(crtc, pipe_config);
5999
6000 return true;
6001 }
6002
6003 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6004 {
6005 struct drm_device *dev = dev_priv->dev;
6006 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6007 struct intel_crtc *crtc;
6008 unsigned long irqflags;
6009 uint32_t val;
6010
6011 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6012 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6013 pipe_name(crtc->pipe));
6014
6015 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6016 WARN(plls->spll_refcount, "SPLL enabled\n");
6017 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6018 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6019 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6020 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6021 "CPU PWM1 enabled\n");
6022 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6023 "CPU PWM2 enabled\n");
6024 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6025 "PCH PWM1 enabled\n");
6026 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6027 "Utility pin enabled\n");
6028 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6029
6030 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6031 val = I915_READ(DEIMR);
6032 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6033 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6034 val = I915_READ(SDEIMR);
6035 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6036 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6037 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6038 }
6039
6040 /*
6041 * This function implements pieces of two sequences from BSpec:
6042 * - Sequence for display software to disable LCPLL
6043 * - Sequence for display software to allow package C8+
6044 * The steps implemented here are just the steps that actually touch the LCPLL
6045 * register. Callers should take care of disabling all the display engine
6046 * functions, doing the mode unset, fixing interrupts, etc.
6047 */
6048 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6049 bool switch_to_fclk, bool allow_power_down)
6050 {
6051 uint32_t val;
6052
6053 assert_can_disable_lcpll(dev_priv);
6054
6055 val = I915_READ(LCPLL_CTL);
6056
6057 if (switch_to_fclk) {
6058 val |= LCPLL_CD_SOURCE_FCLK;
6059 I915_WRITE(LCPLL_CTL, val);
6060
6061 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6062 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6063 DRM_ERROR("Switching to FCLK failed\n");
6064
6065 val = I915_READ(LCPLL_CTL);
6066 }
6067
6068 val |= LCPLL_PLL_DISABLE;
6069 I915_WRITE(LCPLL_CTL, val);
6070 POSTING_READ(LCPLL_CTL);
6071
6072 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6073 DRM_ERROR("LCPLL still locked\n");
6074
6075 val = I915_READ(D_COMP);
6076 val |= D_COMP_COMP_DISABLE;
6077 I915_WRITE(D_COMP, val);
6078 POSTING_READ(D_COMP);
6079 ndelay(100);
6080
6081 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6082 DRM_ERROR("D_COMP RCOMP still in progress\n");
6083
6084 if (allow_power_down) {
6085 val = I915_READ(LCPLL_CTL);
6086 val |= LCPLL_POWER_DOWN_ALLOW;
6087 I915_WRITE(LCPLL_CTL, val);
6088 POSTING_READ(LCPLL_CTL);
6089 }
6090 }
6091
6092 /*
6093 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6094 * source.
6095 */
6096 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6097 {
6098 uint32_t val;
6099
6100 val = I915_READ(LCPLL_CTL);
6101
6102 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6103 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6104 return;
6105
6106 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6107 * we'll hang the machine! */
6108 gen6_gt_force_wake_get(dev_priv);
6109
6110 if (val & LCPLL_POWER_DOWN_ALLOW) {
6111 val &= ~LCPLL_POWER_DOWN_ALLOW;
6112 I915_WRITE(LCPLL_CTL, val);
6113 POSTING_READ(LCPLL_CTL);
6114 }
6115
6116 val = I915_READ(D_COMP);
6117 val |= D_COMP_COMP_FORCE;
6118 val &= ~D_COMP_COMP_DISABLE;
6119 I915_WRITE(D_COMP, val);
6120 POSTING_READ(D_COMP);
6121
6122 val = I915_READ(LCPLL_CTL);
6123 val &= ~LCPLL_PLL_DISABLE;
6124 I915_WRITE(LCPLL_CTL, val);
6125
6126 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6127 DRM_ERROR("LCPLL not locked yet\n");
6128
6129 if (val & LCPLL_CD_SOURCE_FCLK) {
6130 val = I915_READ(LCPLL_CTL);
6131 val &= ~LCPLL_CD_SOURCE_FCLK;
6132 I915_WRITE(LCPLL_CTL, val);
6133
6134 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6135 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6136 DRM_ERROR("Switching back to LCPLL failed\n");
6137 }
6138
6139 gen6_gt_force_wake_put(dev_priv);
6140 }
6141
6142 void hsw_enable_pc8_work(struct work_struct *__work)
6143 {
6144 struct drm_i915_private *dev_priv =
6145 container_of(to_delayed_work(__work), struct drm_i915_private,
6146 pc8.enable_work);
6147 struct drm_device *dev = dev_priv->dev;
6148 uint32_t val;
6149
6150 if (dev_priv->pc8.enabled)
6151 return;
6152
6153 DRM_DEBUG_KMS("Enabling package C8+\n");
6154
6155 dev_priv->pc8.enabled = true;
6156
6157 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6158 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6159 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6160 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6161 }
6162
6163 lpt_disable_clkout_dp(dev);
6164 hsw_pc8_disable_interrupts(dev);
6165 hsw_disable_lcpll(dev_priv, true, true);
6166 }
6167
6168 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6169 {
6170 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6171 WARN(dev_priv->pc8.disable_count < 1,
6172 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6173
6174 dev_priv->pc8.disable_count--;
6175 if (dev_priv->pc8.disable_count != 0)
6176 return;
6177
6178 schedule_delayed_work(&dev_priv->pc8.enable_work,
6179 msecs_to_jiffies(i915_pc8_timeout));
6180 }
6181
6182 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6183 {
6184 struct drm_device *dev = dev_priv->dev;
6185 uint32_t val;
6186
6187 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6188 WARN(dev_priv->pc8.disable_count < 0,
6189 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6190
6191 dev_priv->pc8.disable_count++;
6192 if (dev_priv->pc8.disable_count != 1)
6193 return;
6194
6195 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6196 if (!dev_priv->pc8.enabled)
6197 return;
6198
6199 DRM_DEBUG_KMS("Disabling package C8+\n");
6200
6201 hsw_restore_lcpll(dev_priv);
6202 hsw_pc8_restore_interrupts(dev);
6203 lpt_init_pch_refclk(dev);
6204
6205 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6206 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6207 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6208 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6209 }
6210
6211 intel_prepare_ddi(dev);
6212 i915_gem_init_swizzling(dev);
6213 mutex_lock(&dev_priv->rps.hw_lock);
6214 gen6_update_ring_freq(dev);
6215 mutex_unlock(&dev_priv->rps.hw_lock);
6216 dev_priv->pc8.enabled = false;
6217 }
6218
6219 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6220 {
6221 mutex_lock(&dev_priv->pc8.lock);
6222 __hsw_enable_package_c8(dev_priv);
6223 mutex_unlock(&dev_priv->pc8.lock);
6224 }
6225
6226 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6227 {
6228 mutex_lock(&dev_priv->pc8.lock);
6229 __hsw_disable_package_c8(dev_priv);
6230 mutex_unlock(&dev_priv->pc8.lock);
6231 }
6232
6233 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6234 {
6235 struct drm_device *dev = dev_priv->dev;
6236 struct intel_crtc *crtc;
6237 uint32_t val;
6238
6239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6240 if (crtc->base.enabled)
6241 return false;
6242
6243 /* This case is still possible since we have the i915.disable_power_well
6244 * parameter and also the KVMr or something else might be requesting the
6245 * power well. */
6246 val = I915_READ(HSW_PWR_WELL_DRIVER);
6247 if (val != 0) {
6248 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6249 return false;
6250 }
6251
6252 return true;
6253 }
6254
6255 /* Since we're called from modeset_global_resources there's no way to
6256 * symmetrically increase and decrease the refcount, so we use
6257 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6258 * or not.
6259 */
6260 static void hsw_update_package_c8(struct drm_device *dev)
6261 {
6262 struct drm_i915_private *dev_priv = dev->dev_private;
6263 bool allow;
6264
6265 if (!i915_enable_pc8)
6266 return;
6267
6268 mutex_lock(&dev_priv->pc8.lock);
6269
6270 allow = hsw_can_enable_package_c8(dev_priv);
6271
6272 if (allow == dev_priv->pc8.requirements_met)
6273 goto done;
6274
6275 dev_priv->pc8.requirements_met = allow;
6276
6277 if (allow)
6278 __hsw_enable_package_c8(dev_priv);
6279 else
6280 __hsw_disable_package_c8(dev_priv);
6281
6282 done:
6283 mutex_unlock(&dev_priv->pc8.lock);
6284 }
6285
6286 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6287 {
6288 if (!dev_priv->pc8.gpu_idle) {
6289 dev_priv->pc8.gpu_idle = true;
6290 hsw_enable_package_c8(dev_priv);
6291 }
6292 }
6293
6294 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6295 {
6296 if (dev_priv->pc8.gpu_idle) {
6297 dev_priv->pc8.gpu_idle = false;
6298 hsw_disable_package_c8(dev_priv);
6299 }
6300 }
6301
6302 static void haswell_modeset_global_resources(struct drm_device *dev)
6303 {
6304 bool enable = false;
6305 struct intel_crtc *crtc;
6306
6307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6308 if (!crtc->base.enabled)
6309 continue;
6310
6311 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6312 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6313 enable = true;
6314 }
6315
6316 intel_set_power_well(dev, enable);
6317
6318 hsw_update_package_c8(dev);
6319 }
6320
6321 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6322 int x, int y,
6323 struct drm_framebuffer *fb)
6324 {
6325 struct drm_device *dev = crtc->dev;
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328 int plane = intel_crtc->plane;
6329 int ret;
6330
6331 if (!intel_ddi_pll_mode_set(crtc))
6332 return -EINVAL;
6333
6334 if (intel_crtc->config.has_dp_encoder)
6335 intel_dp_set_m_n(intel_crtc);
6336
6337 intel_crtc->lowfreq_avail = false;
6338
6339 intel_set_pipe_timings(intel_crtc);
6340
6341 if (intel_crtc->config.has_pch_encoder) {
6342 intel_cpu_transcoder_set_m_n(intel_crtc,
6343 &intel_crtc->config.fdi_m_n);
6344 }
6345
6346 haswell_set_pipeconf(crtc);
6347
6348 intel_set_pipe_csc(crtc);
6349
6350 /* Set up the display plane register */
6351 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6352 POSTING_READ(DSPCNTR(plane));
6353
6354 ret = intel_pipe_set_base(crtc, x, y, fb);
6355
6356 intel_update_watermarks(dev);
6357
6358 return ret;
6359 }
6360
6361 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6362 struct intel_crtc_config *pipe_config)
6363 {
6364 struct drm_device *dev = crtc->base.dev;
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 enum intel_display_power_domain pfit_domain;
6367 uint32_t tmp;
6368
6369 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6370 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6371
6372 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6373 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6374 enum pipe trans_edp_pipe;
6375 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6376 default:
6377 WARN(1, "unknown pipe linked to edp transcoder\n");
6378 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6379 case TRANS_DDI_EDP_INPUT_A_ON:
6380 trans_edp_pipe = PIPE_A;
6381 break;
6382 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6383 trans_edp_pipe = PIPE_B;
6384 break;
6385 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6386 trans_edp_pipe = PIPE_C;
6387 break;
6388 }
6389
6390 if (trans_edp_pipe == crtc->pipe)
6391 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6392 }
6393
6394 if (!intel_display_power_enabled(dev,
6395 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6396 return false;
6397
6398 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6399 if (!(tmp & PIPECONF_ENABLE))
6400 return false;
6401
6402 /*
6403 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6404 * DDI E. So just check whether this pipe is wired to DDI E and whether
6405 * the PCH transcoder is on.
6406 */
6407 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6408 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6409 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6410 pipe_config->has_pch_encoder = true;
6411
6412 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6413 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6414 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6415
6416 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6417 }
6418
6419 intel_get_pipe_timings(crtc, pipe_config);
6420
6421 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6422 if (intel_display_power_enabled(dev, pfit_domain))
6423 ironlake_get_pfit_config(crtc, pipe_config);
6424
6425 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6426 (I915_READ(IPS_CTL) & IPS_ENABLE);
6427
6428 pipe_config->pixel_multiplier = 1;
6429
6430 return true;
6431 }
6432
6433 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6434 int x, int y,
6435 struct drm_framebuffer *fb)
6436 {
6437 struct drm_device *dev = crtc->dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 struct intel_encoder *encoder;
6440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6441 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6442 int pipe = intel_crtc->pipe;
6443 int ret;
6444
6445 drm_vblank_pre_modeset(dev, pipe);
6446
6447 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6448
6449 drm_vblank_post_modeset(dev, pipe);
6450
6451 if (ret != 0)
6452 return ret;
6453
6454 for_each_encoder_on_crtc(dev, crtc, encoder) {
6455 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6456 encoder->base.base.id,
6457 drm_get_encoder_name(&encoder->base),
6458 mode->base.id, mode->name);
6459 encoder->mode_set(encoder);
6460 }
6461
6462 return 0;
6463 }
6464
6465 static bool intel_eld_uptodate(struct drm_connector *connector,
6466 int reg_eldv, uint32_t bits_eldv,
6467 int reg_elda, uint32_t bits_elda,
6468 int reg_edid)
6469 {
6470 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6471 uint8_t *eld = connector->eld;
6472 uint32_t i;
6473
6474 i = I915_READ(reg_eldv);
6475 i &= bits_eldv;
6476
6477 if (!eld[0])
6478 return !i;
6479
6480 if (!i)
6481 return false;
6482
6483 i = I915_READ(reg_elda);
6484 i &= ~bits_elda;
6485 I915_WRITE(reg_elda, i);
6486
6487 for (i = 0; i < eld[2]; i++)
6488 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6489 return false;
6490
6491 return true;
6492 }
6493
6494 static void g4x_write_eld(struct drm_connector *connector,
6495 struct drm_crtc *crtc)
6496 {
6497 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6498 uint8_t *eld = connector->eld;
6499 uint32_t eldv;
6500 uint32_t len;
6501 uint32_t i;
6502
6503 i = I915_READ(G4X_AUD_VID_DID);
6504
6505 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6506 eldv = G4X_ELDV_DEVCL_DEVBLC;
6507 else
6508 eldv = G4X_ELDV_DEVCTG;
6509
6510 if (intel_eld_uptodate(connector,
6511 G4X_AUD_CNTL_ST, eldv,
6512 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6513 G4X_HDMIW_HDMIEDID))
6514 return;
6515
6516 i = I915_READ(G4X_AUD_CNTL_ST);
6517 i &= ~(eldv | G4X_ELD_ADDR);
6518 len = (i >> 9) & 0x1f; /* ELD buffer size */
6519 I915_WRITE(G4X_AUD_CNTL_ST, i);
6520
6521 if (!eld[0])
6522 return;
6523
6524 len = min_t(uint8_t, eld[2], len);
6525 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6526 for (i = 0; i < len; i++)
6527 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6528
6529 i = I915_READ(G4X_AUD_CNTL_ST);
6530 i |= eldv;
6531 I915_WRITE(G4X_AUD_CNTL_ST, i);
6532 }
6533
6534 static void haswell_write_eld(struct drm_connector *connector,
6535 struct drm_crtc *crtc)
6536 {
6537 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6538 uint8_t *eld = connector->eld;
6539 struct drm_device *dev = crtc->dev;
6540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6541 uint32_t eldv;
6542 uint32_t i;
6543 int len;
6544 int pipe = to_intel_crtc(crtc)->pipe;
6545 int tmp;
6546
6547 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6548 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6549 int aud_config = HSW_AUD_CFG(pipe);
6550 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6551
6552
6553 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6554
6555 /* Audio output enable */
6556 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6557 tmp = I915_READ(aud_cntrl_st2);
6558 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6559 I915_WRITE(aud_cntrl_st2, tmp);
6560
6561 /* Wait for 1 vertical blank */
6562 intel_wait_for_vblank(dev, pipe);
6563
6564 /* Set ELD valid state */
6565 tmp = I915_READ(aud_cntrl_st2);
6566 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6567 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6568 I915_WRITE(aud_cntrl_st2, tmp);
6569 tmp = I915_READ(aud_cntrl_st2);
6570 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6571
6572 /* Enable HDMI mode */
6573 tmp = I915_READ(aud_config);
6574 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6575 /* clear N_programing_enable and N_value_index */
6576 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6577 I915_WRITE(aud_config, tmp);
6578
6579 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6580
6581 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6582 intel_crtc->eld_vld = true;
6583
6584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6585 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6586 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6587 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6588 } else
6589 I915_WRITE(aud_config, 0);
6590
6591 if (intel_eld_uptodate(connector,
6592 aud_cntrl_st2, eldv,
6593 aud_cntl_st, IBX_ELD_ADDRESS,
6594 hdmiw_hdmiedid))
6595 return;
6596
6597 i = I915_READ(aud_cntrl_st2);
6598 i &= ~eldv;
6599 I915_WRITE(aud_cntrl_st2, i);
6600
6601 if (!eld[0])
6602 return;
6603
6604 i = I915_READ(aud_cntl_st);
6605 i &= ~IBX_ELD_ADDRESS;
6606 I915_WRITE(aud_cntl_st, i);
6607 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6608 DRM_DEBUG_DRIVER("port num:%d\n", i);
6609
6610 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6611 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6612 for (i = 0; i < len; i++)
6613 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6614
6615 i = I915_READ(aud_cntrl_st2);
6616 i |= eldv;
6617 I915_WRITE(aud_cntrl_st2, i);
6618
6619 }
6620
6621 static void ironlake_write_eld(struct drm_connector *connector,
6622 struct drm_crtc *crtc)
6623 {
6624 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6625 uint8_t *eld = connector->eld;
6626 uint32_t eldv;
6627 uint32_t i;
6628 int len;
6629 int hdmiw_hdmiedid;
6630 int aud_config;
6631 int aud_cntl_st;
6632 int aud_cntrl_st2;
6633 int pipe = to_intel_crtc(crtc)->pipe;
6634
6635 if (HAS_PCH_IBX(connector->dev)) {
6636 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6637 aud_config = IBX_AUD_CFG(pipe);
6638 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6639 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6640 } else {
6641 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6642 aud_config = CPT_AUD_CFG(pipe);
6643 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6644 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6645 }
6646
6647 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6648
6649 i = I915_READ(aud_cntl_st);
6650 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6651 if (!i) {
6652 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6653 /* operate blindly on all ports */
6654 eldv = IBX_ELD_VALIDB;
6655 eldv |= IBX_ELD_VALIDB << 4;
6656 eldv |= IBX_ELD_VALIDB << 8;
6657 } else {
6658 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6659 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6660 }
6661
6662 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6663 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6664 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6665 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6666 } else
6667 I915_WRITE(aud_config, 0);
6668
6669 if (intel_eld_uptodate(connector,
6670 aud_cntrl_st2, eldv,
6671 aud_cntl_st, IBX_ELD_ADDRESS,
6672 hdmiw_hdmiedid))
6673 return;
6674
6675 i = I915_READ(aud_cntrl_st2);
6676 i &= ~eldv;
6677 I915_WRITE(aud_cntrl_st2, i);
6678
6679 if (!eld[0])
6680 return;
6681
6682 i = I915_READ(aud_cntl_st);
6683 i &= ~IBX_ELD_ADDRESS;
6684 I915_WRITE(aud_cntl_st, i);
6685
6686 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6687 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6688 for (i = 0; i < len; i++)
6689 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6690
6691 i = I915_READ(aud_cntrl_st2);
6692 i |= eldv;
6693 I915_WRITE(aud_cntrl_st2, i);
6694 }
6695
6696 void intel_write_eld(struct drm_encoder *encoder,
6697 struct drm_display_mode *mode)
6698 {
6699 struct drm_crtc *crtc = encoder->crtc;
6700 struct drm_connector *connector;
6701 struct drm_device *dev = encoder->dev;
6702 struct drm_i915_private *dev_priv = dev->dev_private;
6703
6704 connector = drm_select_eld(encoder, mode);
6705 if (!connector)
6706 return;
6707
6708 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6709 connector->base.id,
6710 drm_get_connector_name(connector),
6711 connector->encoder->base.id,
6712 drm_get_encoder_name(connector->encoder));
6713
6714 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6715
6716 if (dev_priv->display.write_eld)
6717 dev_priv->display.write_eld(connector, crtc);
6718 }
6719
6720 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6721 void intel_crtc_load_lut(struct drm_crtc *crtc)
6722 {
6723 struct drm_device *dev = crtc->dev;
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6726 enum pipe pipe = intel_crtc->pipe;
6727 int palreg = PALETTE(pipe);
6728 int i;
6729 bool reenable_ips = false;
6730
6731 /* The clocks have to be on to load the palette. */
6732 if (!crtc->enabled || !intel_crtc->active)
6733 return;
6734
6735 if (!HAS_PCH_SPLIT(dev_priv->dev))
6736 assert_pll_enabled(dev_priv, pipe);
6737
6738 /* use legacy palette for Ironlake */
6739 if (HAS_PCH_SPLIT(dev))
6740 palreg = LGC_PALETTE(pipe);
6741
6742 /* Workaround : Do not read or write the pipe palette/gamma data while
6743 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6744 */
6745 if (intel_crtc->config.ips_enabled &&
6746 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6747 GAMMA_MODE_MODE_SPLIT)) {
6748 hsw_disable_ips(intel_crtc);
6749 reenable_ips = true;
6750 }
6751
6752 for (i = 0; i < 256; i++) {
6753 I915_WRITE(palreg + 4 * i,
6754 (intel_crtc->lut_r[i] << 16) |
6755 (intel_crtc->lut_g[i] << 8) |
6756 intel_crtc->lut_b[i]);
6757 }
6758
6759 if (reenable_ips)
6760 hsw_enable_ips(intel_crtc);
6761 }
6762
6763 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6764 {
6765 struct drm_device *dev = crtc->dev;
6766 struct drm_i915_private *dev_priv = dev->dev_private;
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6768 bool visible = base != 0;
6769 u32 cntl;
6770
6771 if (intel_crtc->cursor_visible == visible)
6772 return;
6773
6774 cntl = I915_READ(_CURACNTR);
6775 if (visible) {
6776 /* On these chipsets we can only modify the base whilst
6777 * the cursor is disabled.
6778 */
6779 I915_WRITE(_CURABASE, base);
6780
6781 cntl &= ~(CURSOR_FORMAT_MASK);
6782 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6783 cntl |= CURSOR_ENABLE |
6784 CURSOR_GAMMA_ENABLE |
6785 CURSOR_FORMAT_ARGB;
6786 } else
6787 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6788 I915_WRITE(_CURACNTR, cntl);
6789
6790 intel_crtc->cursor_visible = visible;
6791 }
6792
6793 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6794 {
6795 struct drm_device *dev = crtc->dev;
6796 struct drm_i915_private *dev_priv = dev->dev_private;
6797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6798 int pipe = intel_crtc->pipe;
6799 bool visible = base != 0;
6800
6801 if (intel_crtc->cursor_visible != visible) {
6802 uint32_t cntl = I915_READ(CURCNTR(pipe));
6803 if (base) {
6804 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6805 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6806 cntl |= pipe << 28; /* Connect to correct pipe */
6807 } else {
6808 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6809 cntl |= CURSOR_MODE_DISABLE;
6810 }
6811 I915_WRITE(CURCNTR(pipe), cntl);
6812
6813 intel_crtc->cursor_visible = visible;
6814 }
6815 /* and commit changes on next vblank */
6816 POSTING_READ(CURCNTR(pipe));
6817 I915_WRITE(CURBASE(pipe), base);
6818 POSTING_READ(CURBASE(pipe));
6819 }
6820
6821 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6822 {
6823 struct drm_device *dev = crtc->dev;
6824 struct drm_i915_private *dev_priv = dev->dev_private;
6825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6826 int pipe = intel_crtc->pipe;
6827 bool visible = base != 0;
6828
6829 if (intel_crtc->cursor_visible != visible) {
6830 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6831 if (base) {
6832 cntl &= ~CURSOR_MODE;
6833 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6834 } else {
6835 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6836 cntl |= CURSOR_MODE_DISABLE;
6837 }
6838 if (IS_HASWELL(dev)) {
6839 cntl |= CURSOR_PIPE_CSC_ENABLE;
6840 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6841 }
6842 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6843
6844 intel_crtc->cursor_visible = visible;
6845 }
6846 /* and commit changes on next vblank */
6847 POSTING_READ(CURCNTR_IVB(pipe));
6848 I915_WRITE(CURBASE_IVB(pipe), base);
6849 POSTING_READ(CURBASE_IVB(pipe));
6850 }
6851
6852 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6853 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6854 bool on)
6855 {
6856 struct drm_device *dev = crtc->dev;
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 int pipe = intel_crtc->pipe;
6860 int x = intel_crtc->cursor_x;
6861 int y = intel_crtc->cursor_y;
6862 u32 base, pos;
6863 bool visible;
6864
6865 pos = 0;
6866
6867 if (on && crtc->enabled && crtc->fb) {
6868 base = intel_crtc->cursor_addr;
6869 if (x > (int) crtc->fb->width)
6870 base = 0;
6871
6872 if (y > (int) crtc->fb->height)
6873 base = 0;
6874 } else
6875 base = 0;
6876
6877 if (x < 0) {
6878 if (x + intel_crtc->cursor_width < 0)
6879 base = 0;
6880
6881 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6882 x = -x;
6883 }
6884 pos |= x << CURSOR_X_SHIFT;
6885
6886 if (y < 0) {
6887 if (y + intel_crtc->cursor_height < 0)
6888 base = 0;
6889
6890 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6891 y = -y;
6892 }
6893 pos |= y << CURSOR_Y_SHIFT;
6894
6895 visible = base != 0;
6896 if (!visible && !intel_crtc->cursor_visible)
6897 return;
6898
6899 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6900 I915_WRITE(CURPOS_IVB(pipe), pos);
6901 ivb_update_cursor(crtc, base);
6902 } else {
6903 I915_WRITE(CURPOS(pipe), pos);
6904 if (IS_845G(dev) || IS_I865G(dev))
6905 i845_update_cursor(crtc, base);
6906 else
6907 i9xx_update_cursor(crtc, base);
6908 }
6909 }
6910
6911 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6912 struct drm_file *file,
6913 uint32_t handle,
6914 uint32_t width, uint32_t height)
6915 {
6916 struct drm_device *dev = crtc->dev;
6917 struct drm_i915_private *dev_priv = dev->dev_private;
6918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6919 struct drm_i915_gem_object *obj;
6920 uint32_t addr;
6921 int ret;
6922
6923 /* if we want to turn off the cursor ignore width and height */
6924 if (!handle) {
6925 DRM_DEBUG_KMS("cursor off\n");
6926 addr = 0;
6927 obj = NULL;
6928 mutex_lock(&dev->struct_mutex);
6929 goto finish;
6930 }
6931
6932 /* Currently we only support 64x64 cursors */
6933 if (width != 64 || height != 64) {
6934 DRM_ERROR("we currently only support 64x64 cursors\n");
6935 return -EINVAL;
6936 }
6937
6938 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6939 if (&obj->base == NULL)
6940 return -ENOENT;
6941
6942 if (obj->base.size < width * height * 4) {
6943 DRM_ERROR("buffer is to small\n");
6944 ret = -ENOMEM;
6945 goto fail;
6946 }
6947
6948 /* we only need to pin inside GTT if cursor is non-phy */
6949 mutex_lock(&dev->struct_mutex);
6950 if (!dev_priv->info->cursor_needs_physical) {
6951 unsigned alignment;
6952
6953 if (obj->tiling_mode) {
6954 DRM_ERROR("cursor cannot be tiled\n");
6955 ret = -EINVAL;
6956 goto fail_locked;
6957 }
6958
6959 /* Note that the w/a also requires 2 PTE of padding following
6960 * the bo. We currently fill all unused PTE with the shadow
6961 * page and so we should always have valid PTE following the
6962 * cursor preventing the VT-d warning.
6963 */
6964 alignment = 0;
6965 if (need_vtd_wa(dev))
6966 alignment = 64*1024;
6967
6968 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6969 if (ret) {
6970 DRM_ERROR("failed to move cursor bo into the GTT\n");
6971 goto fail_locked;
6972 }
6973
6974 ret = i915_gem_object_put_fence(obj);
6975 if (ret) {
6976 DRM_ERROR("failed to release fence for cursor");
6977 goto fail_unpin;
6978 }
6979
6980 addr = i915_gem_obj_ggtt_offset(obj);
6981 } else {
6982 int align = IS_I830(dev) ? 16 * 1024 : 256;
6983 ret = i915_gem_attach_phys_object(dev, obj,
6984 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6985 align);
6986 if (ret) {
6987 DRM_ERROR("failed to attach phys object\n");
6988 goto fail_locked;
6989 }
6990 addr = obj->phys_obj->handle->busaddr;
6991 }
6992
6993 if (IS_GEN2(dev))
6994 I915_WRITE(CURSIZE, (height << 12) | width);
6995
6996 finish:
6997 if (intel_crtc->cursor_bo) {
6998 if (dev_priv->info->cursor_needs_physical) {
6999 if (intel_crtc->cursor_bo != obj)
7000 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7001 } else
7002 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7003 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7004 }
7005
7006 mutex_unlock(&dev->struct_mutex);
7007
7008 intel_crtc->cursor_addr = addr;
7009 intel_crtc->cursor_bo = obj;
7010 intel_crtc->cursor_width = width;
7011 intel_crtc->cursor_height = height;
7012
7013 if (intel_crtc->active)
7014 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7015
7016 return 0;
7017 fail_unpin:
7018 i915_gem_object_unpin_from_display_plane(obj);
7019 fail_locked:
7020 mutex_unlock(&dev->struct_mutex);
7021 fail:
7022 drm_gem_object_unreference_unlocked(&obj->base);
7023 return ret;
7024 }
7025
7026 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7027 {
7028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7029
7030 intel_crtc->cursor_x = x;
7031 intel_crtc->cursor_y = y;
7032
7033 if (intel_crtc->active)
7034 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7035
7036 return 0;
7037 }
7038
7039 /** Sets the color ramps on behalf of RandR */
7040 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7041 u16 blue, int regno)
7042 {
7043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7044
7045 intel_crtc->lut_r[regno] = red >> 8;
7046 intel_crtc->lut_g[regno] = green >> 8;
7047 intel_crtc->lut_b[regno] = blue >> 8;
7048 }
7049
7050 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7051 u16 *blue, int regno)
7052 {
7053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7054
7055 *red = intel_crtc->lut_r[regno] << 8;
7056 *green = intel_crtc->lut_g[regno] << 8;
7057 *blue = intel_crtc->lut_b[regno] << 8;
7058 }
7059
7060 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7061 u16 *blue, uint32_t start, uint32_t size)
7062 {
7063 int end = (start + size > 256) ? 256 : start + size, i;
7064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7065
7066 for (i = start; i < end; i++) {
7067 intel_crtc->lut_r[i] = red[i] >> 8;
7068 intel_crtc->lut_g[i] = green[i] >> 8;
7069 intel_crtc->lut_b[i] = blue[i] >> 8;
7070 }
7071
7072 intel_crtc_load_lut(crtc);
7073 }
7074
7075 /* VESA 640x480x72Hz mode to set on the pipe */
7076 static struct drm_display_mode load_detect_mode = {
7077 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7078 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7079 };
7080
7081 static struct drm_framebuffer *
7082 intel_framebuffer_create(struct drm_device *dev,
7083 struct drm_mode_fb_cmd2 *mode_cmd,
7084 struct drm_i915_gem_object *obj)
7085 {
7086 struct intel_framebuffer *intel_fb;
7087 int ret;
7088
7089 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7090 if (!intel_fb) {
7091 drm_gem_object_unreference_unlocked(&obj->base);
7092 return ERR_PTR(-ENOMEM);
7093 }
7094
7095 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7096 if (ret) {
7097 drm_gem_object_unreference_unlocked(&obj->base);
7098 kfree(intel_fb);
7099 return ERR_PTR(ret);
7100 }
7101
7102 return &intel_fb->base;
7103 }
7104
7105 static u32
7106 intel_framebuffer_pitch_for_width(int width, int bpp)
7107 {
7108 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7109 return ALIGN(pitch, 64);
7110 }
7111
7112 static u32
7113 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7114 {
7115 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7116 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7117 }
7118
7119 static struct drm_framebuffer *
7120 intel_framebuffer_create_for_mode(struct drm_device *dev,
7121 struct drm_display_mode *mode,
7122 int depth, int bpp)
7123 {
7124 struct drm_i915_gem_object *obj;
7125 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7126
7127 obj = i915_gem_alloc_object(dev,
7128 intel_framebuffer_size_for_mode(mode, bpp));
7129 if (obj == NULL)
7130 return ERR_PTR(-ENOMEM);
7131
7132 mode_cmd.width = mode->hdisplay;
7133 mode_cmd.height = mode->vdisplay;
7134 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7135 bpp);
7136 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7137
7138 return intel_framebuffer_create(dev, &mode_cmd, obj);
7139 }
7140
7141 static struct drm_framebuffer *
7142 mode_fits_in_fbdev(struct drm_device *dev,
7143 struct drm_display_mode *mode)
7144 {
7145 struct drm_i915_private *dev_priv = dev->dev_private;
7146 struct drm_i915_gem_object *obj;
7147 struct drm_framebuffer *fb;
7148
7149 if (dev_priv->fbdev == NULL)
7150 return NULL;
7151
7152 obj = dev_priv->fbdev->ifb.obj;
7153 if (obj == NULL)
7154 return NULL;
7155
7156 fb = &dev_priv->fbdev->ifb.base;
7157 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7158 fb->bits_per_pixel))
7159 return NULL;
7160
7161 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7162 return NULL;
7163
7164 return fb;
7165 }
7166
7167 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7168 struct drm_display_mode *mode,
7169 struct intel_load_detect_pipe *old)
7170 {
7171 struct intel_crtc *intel_crtc;
7172 struct intel_encoder *intel_encoder =
7173 intel_attached_encoder(connector);
7174 struct drm_crtc *possible_crtc;
7175 struct drm_encoder *encoder = &intel_encoder->base;
7176 struct drm_crtc *crtc = NULL;
7177 struct drm_device *dev = encoder->dev;
7178 struct drm_framebuffer *fb;
7179 int i = -1;
7180
7181 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7182 connector->base.id, drm_get_connector_name(connector),
7183 encoder->base.id, drm_get_encoder_name(encoder));
7184
7185 /*
7186 * Algorithm gets a little messy:
7187 *
7188 * - if the connector already has an assigned crtc, use it (but make
7189 * sure it's on first)
7190 *
7191 * - try to find the first unused crtc that can drive this connector,
7192 * and use that if we find one
7193 */
7194
7195 /* See if we already have a CRTC for this connector */
7196 if (encoder->crtc) {
7197 crtc = encoder->crtc;
7198
7199 mutex_lock(&crtc->mutex);
7200
7201 old->dpms_mode = connector->dpms;
7202 old->load_detect_temp = false;
7203
7204 /* Make sure the crtc and connector are running */
7205 if (connector->dpms != DRM_MODE_DPMS_ON)
7206 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7207
7208 return true;
7209 }
7210
7211 /* Find an unused one (if possible) */
7212 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7213 i++;
7214 if (!(encoder->possible_crtcs & (1 << i)))
7215 continue;
7216 if (!possible_crtc->enabled) {
7217 crtc = possible_crtc;
7218 break;
7219 }
7220 }
7221
7222 /*
7223 * If we didn't find an unused CRTC, don't use any.
7224 */
7225 if (!crtc) {
7226 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7227 return false;
7228 }
7229
7230 mutex_lock(&crtc->mutex);
7231 intel_encoder->new_crtc = to_intel_crtc(crtc);
7232 to_intel_connector(connector)->new_encoder = intel_encoder;
7233
7234 intel_crtc = to_intel_crtc(crtc);
7235 old->dpms_mode = connector->dpms;
7236 old->load_detect_temp = true;
7237 old->release_fb = NULL;
7238
7239 if (!mode)
7240 mode = &load_detect_mode;
7241
7242 /* We need a framebuffer large enough to accommodate all accesses
7243 * that the plane may generate whilst we perform load detection.
7244 * We can not rely on the fbcon either being present (we get called
7245 * during its initialisation to detect all boot displays, or it may
7246 * not even exist) or that it is large enough to satisfy the
7247 * requested mode.
7248 */
7249 fb = mode_fits_in_fbdev(dev, mode);
7250 if (fb == NULL) {
7251 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7252 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7253 old->release_fb = fb;
7254 } else
7255 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7256 if (IS_ERR(fb)) {
7257 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7258 mutex_unlock(&crtc->mutex);
7259 return false;
7260 }
7261
7262 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7263 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7264 if (old->release_fb)
7265 old->release_fb->funcs->destroy(old->release_fb);
7266 mutex_unlock(&crtc->mutex);
7267 return false;
7268 }
7269
7270 /* let the connector get through one full cycle before testing */
7271 intel_wait_for_vblank(dev, intel_crtc->pipe);
7272 return true;
7273 }
7274
7275 void intel_release_load_detect_pipe(struct drm_connector *connector,
7276 struct intel_load_detect_pipe *old)
7277 {
7278 struct intel_encoder *intel_encoder =
7279 intel_attached_encoder(connector);
7280 struct drm_encoder *encoder = &intel_encoder->base;
7281 struct drm_crtc *crtc = encoder->crtc;
7282
7283 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7284 connector->base.id, drm_get_connector_name(connector),
7285 encoder->base.id, drm_get_encoder_name(encoder));
7286
7287 if (old->load_detect_temp) {
7288 to_intel_connector(connector)->new_encoder = NULL;
7289 intel_encoder->new_crtc = NULL;
7290 intel_set_mode(crtc, NULL, 0, 0, NULL);
7291
7292 if (old->release_fb) {
7293 drm_framebuffer_unregister_private(old->release_fb);
7294 drm_framebuffer_unreference(old->release_fb);
7295 }
7296
7297 mutex_unlock(&crtc->mutex);
7298 return;
7299 }
7300
7301 /* Switch crtc and encoder back off if necessary */
7302 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7303 connector->funcs->dpms(connector, old->dpms_mode);
7304
7305 mutex_unlock(&crtc->mutex);
7306 }
7307
7308 /* Returns the clock of the currently programmed mode of the given pipe. */
7309 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7310 struct intel_crtc_config *pipe_config)
7311 {
7312 struct drm_device *dev = crtc->base.dev;
7313 struct drm_i915_private *dev_priv = dev->dev_private;
7314 int pipe = pipe_config->cpu_transcoder;
7315 u32 dpll = I915_READ(DPLL(pipe));
7316 u32 fp;
7317 intel_clock_t clock;
7318
7319 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7320 fp = I915_READ(FP0(pipe));
7321 else
7322 fp = I915_READ(FP1(pipe));
7323
7324 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7325 if (IS_PINEVIEW(dev)) {
7326 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7327 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7328 } else {
7329 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7330 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7331 }
7332
7333 if (!IS_GEN2(dev)) {
7334 if (IS_PINEVIEW(dev))
7335 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7336 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7337 else
7338 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7339 DPLL_FPA01_P1_POST_DIV_SHIFT);
7340
7341 switch (dpll & DPLL_MODE_MASK) {
7342 case DPLLB_MODE_DAC_SERIAL:
7343 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7344 5 : 10;
7345 break;
7346 case DPLLB_MODE_LVDS:
7347 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7348 7 : 14;
7349 break;
7350 default:
7351 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7352 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7353 pipe_config->adjusted_mode.clock = 0;
7354 return;
7355 }
7356
7357 if (IS_PINEVIEW(dev))
7358 pineview_clock(96000, &clock);
7359 else
7360 i9xx_clock(96000, &clock);
7361 } else {
7362 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7363
7364 if (is_lvds) {
7365 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7366 DPLL_FPA01_P1_POST_DIV_SHIFT);
7367 clock.p2 = 14;
7368
7369 if ((dpll & PLL_REF_INPUT_MASK) ==
7370 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7371 /* XXX: might not be 66MHz */
7372 i9xx_clock(66000, &clock);
7373 } else
7374 i9xx_clock(48000, &clock);
7375 } else {
7376 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7377 clock.p1 = 2;
7378 else {
7379 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7380 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7381 }
7382 if (dpll & PLL_P2_DIVIDE_BY_4)
7383 clock.p2 = 4;
7384 else
7385 clock.p2 = 2;
7386
7387 i9xx_clock(48000, &clock);
7388 }
7389 }
7390
7391 pipe_config->adjusted_mode.clock = clock.dot;
7392 }
7393
7394 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7395 struct intel_crtc_config *pipe_config)
7396 {
7397 struct drm_device *dev = crtc->base.dev;
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7400 int link_freq, repeat;
7401 u64 clock;
7402 u32 link_m, link_n;
7403
7404 repeat = pipe_config->pixel_multiplier;
7405
7406 /*
7407 * The calculation for the data clock is:
7408 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7409 * But we want to avoid losing precison if possible, so:
7410 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7411 *
7412 * and the link clock is simpler:
7413 * link_clock = (m * link_clock * repeat) / n
7414 */
7415
7416 /*
7417 * We need to get the FDI or DP link clock here to derive
7418 * the M/N dividers.
7419 *
7420 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7421 * For DP, it's either 1.62GHz or 2.7GHz.
7422 * We do our calculations in 10*MHz since we don't need much precison.
7423 */
7424 if (pipe_config->has_pch_encoder)
7425 link_freq = intel_fdi_link_freq(dev) * 10000;
7426 else
7427 link_freq = pipe_config->port_clock;
7428
7429 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7430 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7431
7432 if (!link_m || !link_n)
7433 return;
7434
7435 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7436 do_div(clock, link_n);
7437
7438 pipe_config->adjusted_mode.clock = clock;
7439 }
7440
7441 /** Returns the currently programmed mode of the given pipe. */
7442 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7443 struct drm_crtc *crtc)
7444 {
7445 struct drm_i915_private *dev_priv = dev->dev_private;
7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7448 struct drm_display_mode *mode;
7449 struct intel_crtc_config pipe_config;
7450 int htot = I915_READ(HTOTAL(cpu_transcoder));
7451 int hsync = I915_READ(HSYNC(cpu_transcoder));
7452 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7453 int vsync = I915_READ(VSYNC(cpu_transcoder));
7454
7455 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7456 if (!mode)
7457 return NULL;
7458
7459 /*
7460 * Construct a pipe_config sufficient for getting the clock info
7461 * back out of crtc_clock_get.
7462 *
7463 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7464 * to use a real value here instead.
7465 */
7466 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7467 pipe_config.pixel_multiplier = 1;
7468 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7469
7470 mode->clock = pipe_config.adjusted_mode.clock;
7471 mode->hdisplay = (htot & 0xffff) + 1;
7472 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7473 mode->hsync_start = (hsync & 0xffff) + 1;
7474 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7475 mode->vdisplay = (vtot & 0xffff) + 1;
7476 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7477 mode->vsync_start = (vsync & 0xffff) + 1;
7478 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7479
7480 drm_mode_set_name(mode);
7481
7482 return mode;
7483 }
7484
7485 static void intel_increase_pllclock(struct drm_crtc *crtc)
7486 {
7487 struct drm_device *dev = crtc->dev;
7488 drm_i915_private_t *dev_priv = dev->dev_private;
7489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7490 int pipe = intel_crtc->pipe;
7491 int dpll_reg = DPLL(pipe);
7492 int dpll;
7493
7494 if (HAS_PCH_SPLIT(dev))
7495 return;
7496
7497 if (!dev_priv->lvds_downclock_avail)
7498 return;
7499
7500 dpll = I915_READ(dpll_reg);
7501 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7502 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7503
7504 assert_panel_unlocked(dev_priv, pipe);
7505
7506 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7507 I915_WRITE(dpll_reg, dpll);
7508 intel_wait_for_vblank(dev, pipe);
7509
7510 dpll = I915_READ(dpll_reg);
7511 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7512 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7513 }
7514 }
7515
7516 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7517 {
7518 struct drm_device *dev = crtc->dev;
7519 drm_i915_private_t *dev_priv = dev->dev_private;
7520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7521
7522 if (HAS_PCH_SPLIT(dev))
7523 return;
7524
7525 if (!dev_priv->lvds_downclock_avail)
7526 return;
7527
7528 /*
7529 * Since this is called by a timer, we should never get here in
7530 * the manual case.
7531 */
7532 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7533 int pipe = intel_crtc->pipe;
7534 int dpll_reg = DPLL(pipe);
7535 int dpll;
7536
7537 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7538
7539 assert_panel_unlocked(dev_priv, pipe);
7540
7541 dpll = I915_READ(dpll_reg);
7542 dpll |= DISPLAY_RATE_SELECT_FPA1;
7543 I915_WRITE(dpll_reg, dpll);
7544 intel_wait_for_vblank(dev, pipe);
7545 dpll = I915_READ(dpll_reg);
7546 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7547 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7548 }
7549
7550 }
7551
7552 void intel_mark_busy(struct drm_device *dev)
7553 {
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555
7556 hsw_package_c8_gpu_busy(dev_priv);
7557 i915_update_gfx_val(dev_priv);
7558 }
7559
7560 void intel_mark_idle(struct drm_device *dev)
7561 {
7562 struct drm_i915_private *dev_priv = dev->dev_private;
7563 struct drm_crtc *crtc;
7564
7565 hsw_package_c8_gpu_idle(dev_priv);
7566
7567 if (!i915_powersave)
7568 return;
7569
7570 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7571 if (!crtc->fb)
7572 continue;
7573
7574 intel_decrease_pllclock(crtc);
7575 }
7576 }
7577
7578 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7579 struct intel_ring_buffer *ring)
7580 {
7581 struct drm_device *dev = obj->base.dev;
7582 struct drm_crtc *crtc;
7583
7584 if (!i915_powersave)
7585 return;
7586
7587 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7588 if (!crtc->fb)
7589 continue;
7590
7591 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7592 continue;
7593
7594 intel_increase_pllclock(crtc);
7595 if (ring && intel_fbc_enabled(dev))
7596 ring->fbc_dirty = true;
7597 }
7598 }
7599
7600 static void intel_crtc_destroy(struct drm_crtc *crtc)
7601 {
7602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7603 struct drm_device *dev = crtc->dev;
7604 struct intel_unpin_work *work;
7605 unsigned long flags;
7606
7607 spin_lock_irqsave(&dev->event_lock, flags);
7608 work = intel_crtc->unpin_work;
7609 intel_crtc->unpin_work = NULL;
7610 spin_unlock_irqrestore(&dev->event_lock, flags);
7611
7612 if (work) {
7613 cancel_work_sync(&work->work);
7614 kfree(work);
7615 }
7616
7617 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7618
7619 drm_crtc_cleanup(crtc);
7620
7621 kfree(intel_crtc);
7622 }
7623
7624 static void intel_unpin_work_fn(struct work_struct *__work)
7625 {
7626 struct intel_unpin_work *work =
7627 container_of(__work, struct intel_unpin_work, work);
7628 struct drm_device *dev = work->crtc->dev;
7629
7630 mutex_lock(&dev->struct_mutex);
7631 intel_unpin_fb_obj(work->old_fb_obj);
7632 drm_gem_object_unreference(&work->pending_flip_obj->base);
7633 drm_gem_object_unreference(&work->old_fb_obj->base);
7634
7635 intel_update_fbc(dev);
7636 mutex_unlock(&dev->struct_mutex);
7637
7638 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7639 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7640
7641 kfree(work);
7642 }
7643
7644 static void do_intel_finish_page_flip(struct drm_device *dev,
7645 struct drm_crtc *crtc)
7646 {
7647 drm_i915_private_t *dev_priv = dev->dev_private;
7648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7649 struct intel_unpin_work *work;
7650 unsigned long flags;
7651
7652 /* Ignore early vblank irqs */
7653 if (intel_crtc == NULL)
7654 return;
7655
7656 spin_lock_irqsave(&dev->event_lock, flags);
7657 work = intel_crtc->unpin_work;
7658
7659 /* Ensure we don't miss a work->pending update ... */
7660 smp_rmb();
7661
7662 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7663 spin_unlock_irqrestore(&dev->event_lock, flags);
7664 return;
7665 }
7666
7667 /* and that the unpin work is consistent wrt ->pending. */
7668 smp_rmb();
7669
7670 intel_crtc->unpin_work = NULL;
7671
7672 if (work->event)
7673 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7674
7675 drm_vblank_put(dev, intel_crtc->pipe);
7676
7677 spin_unlock_irqrestore(&dev->event_lock, flags);
7678
7679 wake_up_all(&dev_priv->pending_flip_queue);
7680
7681 queue_work(dev_priv->wq, &work->work);
7682
7683 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7684 }
7685
7686 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7687 {
7688 drm_i915_private_t *dev_priv = dev->dev_private;
7689 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7690
7691 do_intel_finish_page_flip(dev, crtc);
7692 }
7693
7694 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7695 {
7696 drm_i915_private_t *dev_priv = dev->dev_private;
7697 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7698
7699 do_intel_finish_page_flip(dev, crtc);
7700 }
7701
7702 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7703 {
7704 drm_i915_private_t *dev_priv = dev->dev_private;
7705 struct intel_crtc *intel_crtc =
7706 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7707 unsigned long flags;
7708
7709 /* NB: An MMIO update of the plane base pointer will also
7710 * generate a page-flip completion irq, i.e. every modeset
7711 * is also accompanied by a spurious intel_prepare_page_flip().
7712 */
7713 spin_lock_irqsave(&dev->event_lock, flags);
7714 if (intel_crtc->unpin_work)
7715 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7716 spin_unlock_irqrestore(&dev->event_lock, flags);
7717 }
7718
7719 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7720 {
7721 /* Ensure that the work item is consistent when activating it ... */
7722 smp_wmb();
7723 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7724 /* and that it is marked active as soon as the irq could fire. */
7725 smp_wmb();
7726 }
7727
7728 static int intel_gen2_queue_flip(struct drm_device *dev,
7729 struct drm_crtc *crtc,
7730 struct drm_framebuffer *fb,
7731 struct drm_i915_gem_object *obj,
7732 uint32_t flags)
7733 {
7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7736 u32 flip_mask;
7737 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7738 int ret;
7739
7740 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7741 if (ret)
7742 goto err;
7743
7744 ret = intel_ring_begin(ring, 6);
7745 if (ret)
7746 goto err_unpin;
7747
7748 /* Can't queue multiple flips, so wait for the previous
7749 * one to finish before executing the next.
7750 */
7751 if (intel_crtc->plane)
7752 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7753 else
7754 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7755 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7756 intel_ring_emit(ring, MI_NOOP);
7757 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7758 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7759 intel_ring_emit(ring, fb->pitches[0]);
7760 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7761 intel_ring_emit(ring, 0); /* aux display base address, unused */
7762
7763 intel_mark_page_flip_active(intel_crtc);
7764 intel_ring_advance(ring);
7765 return 0;
7766
7767 err_unpin:
7768 intel_unpin_fb_obj(obj);
7769 err:
7770 return ret;
7771 }
7772
7773 static int intel_gen3_queue_flip(struct drm_device *dev,
7774 struct drm_crtc *crtc,
7775 struct drm_framebuffer *fb,
7776 struct drm_i915_gem_object *obj,
7777 uint32_t flags)
7778 {
7779 struct drm_i915_private *dev_priv = dev->dev_private;
7780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7781 u32 flip_mask;
7782 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7783 int ret;
7784
7785 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7786 if (ret)
7787 goto err;
7788
7789 ret = intel_ring_begin(ring, 6);
7790 if (ret)
7791 goto err_unpin;
7792
7793 if (intel_crtc->plane)
7794 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7795 else
7796 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7797 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7798 intel_ring_emit(ring, MI_NOOP);
7799 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7800 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7801 intel_ring_emit(ring, fb->pitches[0]);
7802 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7803 intel_ring_emit(ring, MI_NOOP);
7804
7805 intel_mark_page_flip_active(intel_crtc);
7806 intel_ring_advance(ring);
7807 return 0;
7808
7809 err_unpin:
7810 intel_unpin_fb_obj(obj);
7811 err:
7812 return ret;
7813 }
7814
7815 static int intel_gen4_queue_flip(struct drm_device *dev,
7816 struct drm_crtc *crtc,
7817 struct drm_framebuffer *fb,
7818 struct drm_i915_gem_object *obj,
7819 uint32_t flags)
7820 {
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7823 uint32_t pf, pipesrc;
7824 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7825 int ret;
7826
7827 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7828 if (ret)
7829 goto err;
7830
7831 ret = intel_ring_begin(ring, 4);
7832 if (ret)
7833 goto err_unpin;
7834
7835 /* i965+ uses the linear or tiled offsets from the
7836 * Display Registers (which do not change across a page-flip)
7837 * so we need only reprogram the base address.
7838 */
7839 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7840 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7841 intel_ring_emit(ring, fb->pitches[0]);
7842 intel_ring_emit(ring,
7843 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7844 obj->tiling_mode);
7845
7846 /* XXX Enabling the panel-fitter across page-flip is so far
7847 * untested on non-native modes, so ignore it for now.
7848 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7849 */
7850 pf = 0;
7851 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7852 intel_ring_emit(ring, pf | pipesrc);
7853
7854 intel_mark_page_flip_active(intel_crtc);
7855 intel_ring_advance(ring);
7856 return 0;
7857
7858 err_unpin:
7859 intel_unpin_fb_obj(obj);
7860 err:
7861 return ret;
7862 }
7863
7864 static int intel_gen6_queue_flip(struct drm_device *dev,
7865 struct drm_crtc *crtc,
7866 struct drm_framebuffer *fb,
7867 struct drm_i915_gem_object *obj,
7868 uint32_t flags)
7869 {
7870 struct drm_i915_private *dev_priv = dev->dev_private;
7871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7872 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7873 uint32_t pf, pipesrc;
7874 int ret;
7875
7876 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7877 if (ret)
7878 goto err;
7879
7880 ret = intel_ring_begin(ring, 4);
7881 if (ret)
7882 goto err_unpin;
7883
7884 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7885 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7886 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7887 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7888
7889 /* Contrary to the suggestions in the documentation,
7890 * "Enable Panel Fitter" does not seem to be required when page
7891 * flipping with a non-native mode, and worse causes a normal
7892 * modeset to fail.
7893 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7894 */
7895 pf = 0;
7896 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7897 intel_ring_emit(ring, pf | pipesrc);
7898
7899 intel_mark_page_flip_active(intel_crtc);
7900 intel_ring_advance(ring);
7901 return 0;
7902
7903 err_unpin:
7904 intel_unpin_fb_obj(obj);
7905 err:
7906 return ret;
7907 }
7908
7909 static int intel_gen7_queue_flip(struct drm_device *dev,
7910 struct drm_crtc *crtc,
7911 struct drm_framebuffer *fb,
7912 struct drm_i915_gem_object *obj,
7913 uint32_t flags)
7914 {
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7917 struct intel_ring_buffer *ring;
7918 uint32_t plane_bit = 0;
7919 int len, ret;
7920
7921 ring = obj->ring;
7922 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
7923 ring = &dev_priv->ring[BCS];
7924
7925 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7926 if (ret)
7927 goto err;
7928
7929 switch(intel_crtc->plane) {
7930 case PLANE_A:
7931 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7932 break;
7933 case PLANE_B:
7934 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7935 break;
7936 case PLANE_C:
7937 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7938 break;
7939 default:
7940 WARN_ONCE(1, "unknown plane in flip command\n");
7941 ret = -ENODEV;
7942 goto err_unpin;
7943 }
7944
7945 len = 4;
7946 if (ring->id == RCS)
7947 len += 6;
7948
7949 /*
7950 * BSpec MI_DISPLAY_FLIP for IVB:
7951 * "The full packet must be contained within the same cache line."
7952 *
7953 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
7954 * cacheline, if we ever start emitting more commands before
7955 * the MI_DISPLAY_FLIP we may need to first emit everything else,
7956 * then do the cacheline alignment, and finally emit the
7957 * MI_DISPLAY_FLIP.
7958 */
7959 ret = intel_ring_cacheline_align(ring);
7960 if (ret)
7961 goto err_unpin;
7962
7963 ret = intel_ring_begin(ring, len);
7964 if (ret)
7965 goto err_unpin;
7966
7967 /* Unmask the flip-done completion message. Note that the bspec says that
7968 * we should do this for both the BCS and RCS, and that we must not unmask
7969 * more than one flip event at any time (or ensure that one flip message
7970 * can be sent by waiting for flip-done prior to queueing new flips).
7971 * Experimentation says that BCS works despite DERRMR masking all
7972 * flip-done completion events and that unmasking all planes at once
7973 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7974 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7975 */
7976 if (ring->id == RCS) {
7977 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7978 intel_ring_emit(ring, DERRMR);
7979 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7980 DERRMR_PIPEB_PRI_FLIP_DONE |
7981 DERRMR_PIPEC_PRI_FLIP_DONE));
7982 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7983 intel_ring_emit(ring, DERRMR);
7984 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7985 }
7986
7987 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7988 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7989 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7990 intel_ring_emit(ring, (MI_NOOP));
7991
7992 intel_mark_page_flip_active(intel_crtc);
7993 intel_ring_advance(ring);
7994 return 0;
7995
7996 err_unpin:
7997 intel_unpin_fb_obj(obj);
7998 err:
7999 return ret;
8000 }
8001
8002 static int intel_default_queue_flip(struct drm_device *dev,
8003 struct drm_crtc *crtc,
8004 struct drm_framebuffer *fb,
8005 struct drm_i915_gem_object *obj,
8006 uint32_t flags)
8007 {
8008 return -ENODEV;
8009 }
8010
8011 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8012 struct drm_framebuffer *fb,
8013 struct drm_pending_vblank_event *event,
8014 uint32_t page_flip_flags)
8015 {
8016 struct drm_device *dev = crtc->dev;
8017 struct drm_i915_private *dev_priv = dev->dev_private;
8018 struct drm_framebuffer *old_fb = crtc->fb;
8019 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8021 struct intel_unpin_work *work;
8022 unsigned long flags;
8023 int ret;
8024
8025 /* Can't change pixel format via MI display flips. */
8026 if (fb->pixel_format != crtc->fb->pixel_format)
8027 return -EINVAL;
8028
8029 /*
8030 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8031 * Note that pitch changes could also affect these register.
8032 */
8033 if (INTEL_INFO(dev)->gen > 3 &&
8034 (fb->offsets[0] != crtc->fb->offsets[0] ||
8035 fb->pitches[0] != crtc->fb->pitches[0]))
8036 return -EINVAL;
8037
8038 work = kzalloc(sizeof *work, GFP_KERNEL);
8039 if (work == NULL)
8040 return -ENOMEM;
8041
8042 work->event = event;
8043 work->crtc = crtc;
8044 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8045 INIT_WORK(&work->work, intel_unpin_work_fn);
8046
8047 ret = drm_vblank_get(dev, intel_crtc->pipe);
8048 if (ret)
8049 goto free_work;
8050
8051 /* We borrow the event spin lock for protecting unpin_work */
8052 spin_lock_irqsave(&dev->event_lock, flags);
8053 if (intel_crtc->unpin_work) {
8054 spin_unlock_irqrestore(&dev->event_lock, flags);
8055 kfree(work);
8056 drm_vblank_put(dev, intel_crtc->pipe);
8057
8058 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8059 return -EBUSY;
8060 }
8061 intel_crtc->unpin_work = work;
8062 spin_unlock_irqrestore(&dev->event_lock, flags);
8063
8064 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8065 flush_workqueue(dev_priv->wq);
8066
8067 ret = i915_mutex_lock_interruptible(dev);
8068 if (ret)
8069 goto cleanup;
8070
8071 /* Reference the objects for the scheduled work. */
8072 drm_gem_object_reference(&work->old_fb_obj->base);
8073 drm_gem_object_reference(&obj->base);
8074
8075 crtc->fb = fb;
8076
8077 work->pending_flip_obj = obj;
8078
8079 work->enable_stall_check = true;
8080
8081 atomic_inc(&intel_crtc->unpin_work_count);
8082 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8083
8084 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8085 if (ret)
8086 goto cleanup_pending;
8087
8088 intel_disable_fbc(dev);
8089 intel_mark_fb_busy(obj, NULL);
8090 mutex_unlock(&dev->struct_mutex);
8091
8092 trace_i915_flip_request(intel_crtc->plane, obj);
8093
8094 return 0;
8095
8096 cleanup_pending:
8097 atomic_dec(&intel_crtc->unpin_work_count);
8098 crtc->fb = old_fb;
8099 drm_gem_object_unreference(&work->old_fb_obj->base);
8100 drm_gem_object_unreference(&obj->base);
8101 mutex_unlock(&dev->struct_mutex);
8102
8103 cleanup:
8104 spin_lock_irqsave(&dev->event_lock, flags);
8105 intel_crtc->unpin_work = NULL;
8106 spin_unlock_irqrestore(&dev->event_lock, flags);
8107
8108 drm_vblank_put(dev, intel_crtc->pipe);
8109 free_work:
8110 kfree(work);
8111
8112 return ret;
8113 }
8114
8115 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8116 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8117 .load_lut = intel_crtc_load_lut,
8118 };
8119
8120 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8121 struct drm_crtc *crtc)
8122 {
8123 struct drm_device *dev;
8124 struct drm_crtc *tmp;
8125 int crtc_mask = 1;
8126
8127 WARN(!crtc, "checking null crtc?\n");
8128
8129 dev = crtc->dev;
8130
8131 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8132 if (tmp == crtc)
8133 break;
8134 crtc_mask <<= 1;
8135 }
8136
8137 if (encoder->possible_crtcs & crtc_mask)
8138 return true;
8139 return false;
8140 }
8141
8142 /**
8143 * intel_modeset_update_staged_output_state
8144 *
8145 * Updates the staged output configuration state, e.g. after we've read out the
8146 * current hw state.
8147 */
8148 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8149 {
8150 struct intel_encoder *encoder;
8151 struct intel_connector *connector;
8152
8153 list_for_each_entry(connector, &dev->mode_config.connector_list,
8154 base.head) {
8155 connector->new_encoder =
8156 to_intel_encoder(connector->base.encoder);
8157 }
8158
8159 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8160 base.head) {
8161 encoder->new_crtc =
8162 to_intel_crtc(encoder->base.crtc);
8163 }
8164 }
8165
8166 /**
8167 * intel_modeset_commit_output_state
8168 *
8169 * This function copies the stage display pipe configuration to the real one.
8170 */
8171 static void intel_modeset_commit_output_state(struct drm_device *dev)
8172 {
8173 struct intel_encoder *encoder;
8174 struct intel_connector *connector;
8175
8176 list_for_each_entry(connector, &dev->mode_config.connector_list,
8177 base.head) {
8178 connector->base.encoder = &connector->new_encoder->base;
8179 }
8180
8181 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8182 base.head) {
8183 encoder->base.crtc = &encoder->new_crtc->base;
8184 }
8185 }
8186
8187 static void
8188 connected_sink_compute_bpp(struct intel_connector * connector,
8189 struct intel_crtc_config *pipe_config)
8190 {
8191 int bpp = pipe_config->pipe_bpp;
8192
8193 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8194 connector->base.base.id,
8195 drm_get_connector_name(&connector->base));
8196
8197 /* Don't use an invalid EDID bpc value */
8198 if (connector->base.display_info.bpc &&
8199 connector->base.display_info.bpc * 3 < bpp) {
8200 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8201 bpp, connector->base.display_info.bpc*3);
8202 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8203 }
8204
8205 /* Clamp bpp to 8 on screens without EDID 1.4 */
8206 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8207 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8208 bpp);
8209 pipe_config->pipe_bpp = 24;
8210 }
8211 }
8212
8213 static int
8214 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8215 struct drm_framebuffer *fb,
8216 struct intel_crtc_config *pipe_config)
8217 {
8218 struct drm_device *dev = crtc->base.dev;
8219 struct intel_connector *connector;
8220 int bpp;
8221
8222 switch (fb->pixel_format) {
8223 case DRM_FORMAT_C8:
8224 bpp = 8*3; /* since we go through a colormap */
8225 break;
8226 case DRM_FORMAT_XRGB1555:
8227 case DRM_FORMAT_ARGB1555:
8228 /* checked in intel_framebuffer_init already */
8229 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8230 return -EINVAL;
8231 case DRM_FORMAT_RGB565:
8232 bpp = 6*3; /* min is 18bpp */
8233 break;
8234 case DRM_FORMAT_XBGR8888:
8235 case DRM_FORMAT_ABGR8888:
8236 /* checked in intel_framebuffer_init already */
8237 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8238 return -EINVAL;
8239 case DRM_FORMAT_XRGB8888:
8240 case DRM_FORMAT_ARGB8888:
8241 bpp = 8*3;
8242 break;
8243 case DRM_FORMAT_XRGB2101010:
8244 case DRM_FORMAT_ARGB2101010:
8245 case DRM_FORMAT_XBGR2101010:
8246 case DRM_FORMAT_ABGR2101010:
8247 /* checked in intel_framebuffer_init already */
8248 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8249 return -EINVAL;
8250 bpp = 10*3;
8251 break;
8252 /* TODO: gen4+ supports 16 bpc floating point, too. */
8253 default:
8254 DRM_DEBUG_KMS("unsupported depth\n");
8255 return -EINVAL;
8256 }
8257
8258 pipe_config->pipe_bpp = bpp;
8259
8260 /* Clamp display bpp to EDID value */
8261 list_for_each_entry(connector, &dev->mode_config.connector_list,
8262 base.head) {
8263 if (!connector->new_encoder ||
8264 connector->new_encoder->new_crtc != crtc)
8265 continue;
8266
8267 connected_sink_compute_bpp(connector, pipe_config);
8268 }
8269
8270 return bpp;
8271 }
8272
8273 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8274 struct intel_crtc_config *pipe_config,
8275 const char *context)
8276 {
8277 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8278 context, pipe_name(crtc->pipe));
8279
8280 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8281 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8282 pipe_config->pipe_bpp, pipe_config->dither);
8283 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8284 pipe_config->has_pch_encoder,
8285 pipe_config->fdi_lanes,
8286 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8287 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8288 pipe_config->fdi_m_n.tu);
8289 DRM_DEBUG_KMS("requested mode:\n");
8290 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8291 DRM_DEBUG_KMS("adjusted mode:\n");
8292 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8293 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8294 pipe_config->gmch_pfit.control,
8295 pipe_config->gmch_pfit.pgm_ratios,
8296 pipe_config->gmch_pfit.lvds_border_bits);
8297 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8298 pipe_config->pch_pfit.pos,
8299 pipe_config->pch_pfit.size,
8300 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8301 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8302 }
8303
8304 static bool check_encoder_cloning(struct drm_crtc *crtc)
8305 {
8306 int num_encoders = 0;
8307 bool uncloneable_encoders = false;
8308 struct intel_encoder *encoder;
8309
8310 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8311 base.head) {
8312 if (&encoder->new_crtc->base != crtc)
8313 continue;
8314
8315 num_encoders++;
8316 if (!encoder->cloneable)
8317 uncloneable_encoders = true;
8318 }
8319
8320 return !(num_encoders > 1 && uncloneable_encoders);
8321 }
8322
8323 static struct intel_crtc_config *
8324 intel_modeset_pipe_config(struct drm_crtc *crtc,
8325 struct drm_framebuffer *fb,
8326 struct drm_display_mode *mode)
8327 {
8328 struct drm_device *dev = crtc->dev;
8329 struct intel_encoder *encoder;
8330 struct intel_crtc_config *pipe_config;
8331 int plane_bpp, ret = -EINVAL;
8332 bool retry = true;
8333
8334 if (!check_encoder_cloning(crtc)) {
8335 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8336 return ERR_PTR(-EINVAL);
8337 }
8338
8339 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8340 if (!pipe_config)
8341 return ERR_PTR(-ENOMEM);
8342
8343 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8344 drm_mode_copy(&pipe_config->requested_mode, mode);
8345 pipe_config->cpu_transcoder =
8346 (enum transcoder) to_intel_crtc(crtc)->pipe;
8347 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8348
8349 /*
8350 * Sanitize sync polarity flags based on requested ones. If neither
8351 * positive or negative polarity is requested, treat this as meaning
8352 * negative polarity.
8353 */
8354 if (!(pipe_config->adjusted_mode.flags &
8355 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8356 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8357
8358 if (!(pipe_config->adjusted_mode.flags &
8359 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8360 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8361
8362 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8363 * plane pixel format and any sink constraints into account. Returns the
8364 * source plane bpp so that dithering can be selected on mismatches
8365 * after encoders and crtc also have had their say. */
8366 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8367 fb, pipe_config);
8368 if (plane_bpp < 0)
8369 goto fail;
8370
8371 encoder_retry:
8372 /* Ensure the port clock defaults are reset when retrying. */
8373 pipe_config->port_clock = 0;
8374 pipe_config->pixel_multiplier = 1;
8375
8376 /* Fill in default crtc timings, allow encoders to overwrite them. */
8377 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8378
8379 /* Pass our mode to the connectors and the CRTC to give them a chance to
8380 * adjust it according to limitations or connector properties, and also
8381 * a chance to reject the mode entirely.
8382 */
8383 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8384 base.head) {
8385
8386 if (&encoder->new_crtc->base != crtc)
8387 continue;
8388
8389 if (!(encoder->compute_config(encoder, pipe_config))) {
8390 DRM_DEBUG_KMS("Encoder config failure\n");
8391 goto fail;
8392 }
8393 }
8394
8395 /* Set default port clock if not overwritten by the encoder. Needs to be
8396 * done afterwards in case the encoder adjusts the mode. */
8397 if (!pipe_config->port_clock)
8398 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8399
8400 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8401 if (ret < 0) {
8402 DRM_DEBUG_KMS("CRTC fixup failed\n");
8403 goto fail;
8404 }
8405
8406 if (ret == RETRY) {
8407 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8408 ret = -EINVAL;
8409 goto fail;
8410 }
8411
8412 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8413 retry = false;
8414 goto encoder_retry;
8415 }
8416
8417 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8418 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8419 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8420
8421 return pipe_config;
8422 fail:
8423 kfree(pipe_config);
8424 return ERR_PTR(ret);
8425 }
8426
8427 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8428 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8429 static void
8430 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8431 unsigned *prepare_pipes, unsigned *disable_pipes)
8432 {
8433 struct intel_crtc *intel_crtc;
8434 struct drm_device *dev = crtc->dev;
8435 struct intel_encoder *encoder;
8436 struct intel_connector *connector;
8437 struct drm_crtc *tmp_crtc;
8438
8439 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8440
8441 /* Check which crtcs have changed outputs connected to them, these need
8442 * to be part of the prepare_pipes mask. We don't (yet) support global
8443 * modeset across multiple crtcs, so modeset_pipes will only have one
8444 * bit set at most. */
8445 list_for_each_entry(connector, &dev->mode_config.connector_list,
8446 base.head) {
8447 if (connector->base.encoder == &connector->new_encoder->base)
8448 continue;
8449
8450 if (connector->base.encoder) {
8451 tmp_crtc = connector->base.encoder->crtc;
8452
8453 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8454 }
8455
8456 if (connector->new_encoder)
8457 *prepare_pipes |=
8458 1 << connector->new_encoder->new_crtc->pipe;
8459 }
8460
8461 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8462 base.head) {
8463 if (encoder->base.crtc == &encoder->new_crtc->base)
8464 continue;
8465
8466 if (encoder->base.crtc) {
8467 tmp_crtc = encoder->base.crtc;
8468
8469 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8470 }
8471
8472 if (encoder->new_crtc)
8473 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8474 }
8475
8476 /* Check for any pipes that will be fully disabled ... */
8477 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8478 base.head) {
8479 bool used = false;
8480
8481 /* Don't try to disable disabled crtcs. */
8482 if (!intel_crtc->base.enabled)
8483 continue;
8484
8485 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8486 base.head) {
8487 if (encoder->new_crtc == intel_crtc)
8488 used = true;
8489 }
8490
8491 if (!used)
8492 *disable_pipes |= 1 << intel_crtc->pipe;
8493 }
8494
8495
8496 /* set_mode is also used to update properties on life display pipes. */
8497 intel_crtc = to_intel_crtc(crtc);
8498 if (crtc->enabled)
8499 *prepare_pipes |= 1 << intel_crtc->pipe;
8500
8501 /*
8502 * For simplicity do a full modeset on any pipe where the output routing
8503 * changed. We could be more clever, but that would require us to be
8504 * more careful with calling the relevant encoder->mode_set functions.
8505 */
8506 if (*prepare_pipes)
8507 *modeset_pipes = *prepare_pipes;
8508
8509 /* ... and mask these out. */
8510 *modeset_pipes &= ~(*disable_pipes);
8511 *prepare_pipes &= ~(*disable_pipes);
8512
8513 /*
8514 * HACK: We don't (yet) fully support global modesets. intel_set_config
8515 * obies this rule, but the modeset restore mode of
8516 * intel_modeset_setup_hw_state does not.
8517 */
8518 *modeset_pipes &= 1 << intel_crtc->pipe;
8519 *prepare_pipes &= 1 << intel_crtc->pipe;
8520
8521 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8522 *modeset_pipes, *prepare_pipes, *disable_pipes);
8523 }
8524
8525 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8526 {
8527 struct drm_encoder *encoder;
8528 struct drm_device *dev = crtc->dev;
8529
8530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8531 if (encoder->crtc == crtc)
8532 return true;
8533
8534 return false;
8535 }
8536
8537 static void
8538 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8539 {
8540 struct intel_encoder *intel_encoder;
8541 struct intel_crtc *intel_crtc;
8542 struct drm_connector *connector;
8543
8544 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8545 base.head) {
8546 if (!intel_encoder->base.crtc)
8547 continue;
8548
8549 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8550
8551 if (prepare_pipes & (1 << intel_crtc->pipe))
8552 intel_encoder->connectors_active = false;
8553 }
8554
8555 intel_modeset_commit_output_state(dev);
8556
8557 /* Update computed state. */
8558 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8559 base.head) {
8560 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8561 }
8562
8563 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8564 if (!connector->encoder || !connector->encoder->crtc)
8565 continue;
8566
8567 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8568
8569 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8570 struct drm_property *dpms_property =
8571 dev->mode_config.dpms_property;
8572
8573 connector->dpms = DRM_MODE_DPMS_ON;
8574 drm_object_property_set_value(&connector->base,
8575 dpms_property,
8576 DRM_MODE_DPMS_ON);
8577
8578 intel_encoder = to_intel_encoder(connector->encoder);
8579 intel_encoder->connectors_active = true;
8580 }
8581 }
8582
8583 }
8584
8585 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8586 struct intel_crtc_config *new)
8587 {
8588 int clock1, clock2, diff;
8589
8590 clock1 = cur->adjusted_mode.clock;
8591 clock2 = new->adjusted_mode.clock;
8592
8593 if (clock1 == clock2)
8594 return true;
8595
8596 if (!clock1 || !clock2)
8597 return false;
8598
8599 diff = abs(clock1 - clock2);
8600
8601 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8602 return true;
8603
8604 return false;
8605 }
8606
8607 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8608 list_for_each_entry((intel_crtc), \
8609 &(dev)->mode_config.crtc_list, \
8610 base.head) \
8611 if (mask & (1 <<(intel_crtc)->pipe))
8612
8613 static bool
8614 intel_pipe_config_compare(struct drm_device *dev,
8615 struct intel_crtc_config *current_config,
8616 struct intel_crtc_config *pipe_config)
8617 {
8618 #define PIPE_CONF_CHECK_X(name) \
8619 if (current_config->name != pipe_config->name) { \
8620 DRM_ERROR("mismatch in " #name " " \
8621 "(expected 0x%08x, found 0x%08x)\n", \
8622 current_config->name, \
8623 pipe_config->name); \
8624 return false; \
8625 }
8626
8627 #define PIPE_CONF_CHECK_I(name) \
8628 if (current_config->name != pipe_config->name) { \
8629 DRM_ERROR("mismatch in " #name " " \
8630 "(expected %i, found %i)\n", \
8631 current_config->name, \
8632 pipe_config->name); \
8633 return false; \
8634 }
8635
8636 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8637 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8638 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8639 "(expected %i, found %i)\n", \
8640 current_config->name & (mask), \
8641 pipe_config->name & (mask)); \
8642 return false; \
8643 }
8644
8645 #define PIPE_CONF_QUIRK(quirk) \
8646 ((current_config->quirks | pipe_config->quirks) & (quirk))
8647
8648 PIPE_CONF_CHECK_I(cpu_transcoder);
8649
8650 PIPE_CONF_CHECK_I(has_pch_encoder);
8651 PIPE_CONF_CHECK_I(fdi_lanes);
8652 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8653 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8654 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8655 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8656 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8657
8658 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8659 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8660 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8661 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8662 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8663 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8664
8665 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8666 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8667 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8668 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8669 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8670 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8671
8672 PIPE_CONF_CHECK_I(pixel_multiplier);
8673
8674 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8675 DRM_MODE_FLAG_INTERLACE);
8676
8677 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8678 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8679 DRM_MODE_FLAG_PHSYNC);
8680 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8681 DRM_MODE_FLAG_NHSYNC);
8682 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8683 DRM_MODE_FLAG_PVSYNC);
8684 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8685 DRM_MODE_FLAG_NVSYNC);
8686 }
8687
8688 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8689 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8690
8691 /*
8692 * FIXME: BIOS likes to set up a cloned config with lvds+external
8693 * screen. Since we don't yet re-compute the pipe config when moving
8694 * just the lvds port away to another pipe the sw tracking won't match.
8695 *
8696 * Proper atomic modesets with recomputed global state will fix this.
8697 * Until then just don't check gmch state for inherited modes.
8698 */
8699 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
8700 PIPE_CONF_CHECK_I(gmch_pfit.control);
8701 /* pfit ratios are autocomputed by the hw on gen4+ */
8702 if (INTEL_INFO(dev)->gen < 4)
8703 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8704 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8705 }
8706
8707 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8708 if (current_config->pch_pfit.enabled) {
8709 PIPE_CONF_CHECK_I(pch_pfit.pos);
8710 PIPE_CONF_CHECK_I(pch_pfit.size);
8711 }
8712
8713 PIPE_CONF_CHECK_I(ips_enabled);
8714
8715 PIPE_CONF_CHECK_I(shared_dpll);
8716 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8717 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8718 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8719 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8720
8721 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8722 PIPE_CONF_CHECK_I(pipe_bpp);
8723
8724 #undef PIPE_CONF_CHECK_X
8725 #undef PIPE_CONF_CHECK_I
8726 #undef PIPE_CONF_CHECK_FLAGS
8727 #undef PIPE_CONF_QUIRK
8728
8729 if (!IS_HASWELL(dev)) {
8730 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8731 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8732 current_config->adjusted_mode.clock,
8733 pipe_config->adjusted_mode.clock);
8734 return false;
8735 }
8736 }
8737
8738 return true;
8739 }
8740
8741 static void
8742 check_connector_state(struct drm_device *dev)
8743 {
8744 struct intel_connector *connector;
8745
8746 list_for_each_entry(connector, &dev->mode_config.connector_list,
8747 base.head) {
8748 /* This also checks the encoder/connector hw state with the
8749 * ->get_hw_state callbacks. */
8750 intel_connector_check_state(connector);
8751
8752 WARN(&connector->new_encoder->base != connector->base.encoder,
8753 "connector's staged encoder doesn't match current encoder\n");
8754 }
8755 }
8756
8757 static void
8758 check_encoder_state(struct drm_device *dev)
8759 {
8760 struct intel_encoder *encoder;
8761 struct intel_connector *connector;
8762
8763 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8764 base.head) {
8765 bool enabled = false;
8766 bool active = false;
8767 enum pipe pipe, tracked_pipe;
8768
8769 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8770 encoder->base.base.id,
8771 drm_get_encoder_name(&encoder->base));
8772
8773 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8774 "encoder's stage crtc doesn't match current crtc\n");
8775 WARN(encoder->connectors_active && !encoder->base.crtc,
8776 "encoder's active_connectors set, but no crtc\n");
8777
8778 list_for_each_entry(connector, &dev->mode_config.connector_list,
8779 base.head) {
8780 if (connector->base.encoder != &encoder->base)
8781 continue;
8782 enabled = true;
8783 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8784 active = true;
8785 }
8786 WARN(!!encoder->base.crtc != enabled,
8787 "encoder's enabled state mismatch "
8788 "(expected %i, found %i)\n",
8789 !!encoder->base.crtc, enabled);
8790 WARN(active && !encoder->base.crtc,
8791 "active encoder with no crtc\n");
8792
8793 WARN(encoder->connectors_active != active,
8794 "encoder's computed active state doesn't match tracked active state "
8795 "(expected %i, found %i)\n", active, encoder->connectors_active);
8796
8797 active = encoder->get_hw_state(encoder, &pipe);
8798 WARN(active != encoder->connectors_active,
8799 "encoder's hw state doesn't match sw tracking "
8800 "(expected %i, found %i)\n",
8801 encoder->connectors_active, active);
8802
8803 if (!encoder->base.crtc)
8804 continue;
8805
8806 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8807 WARN(active && pipe != tracked_pipe,
8808 "active encoder's pipe doesn't match"
8809 "(expected %i, found %i)\n",
8810 tracked_pipe, pipe);
8811
8812 }
8813 }
8814
8815 static void
8816 check_crtc_state(struct drm_device *dev)
8817 {
8818 drm_i915_private_t *dev_priv = dev->dev_private;
8819 struct intel_crtc *crtc;
8820 struct intel_encoder *encoder;
8821 struct intel_crtc_config pipe_config;
8822
8823 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8824 base.head) {
8825 bool enabled = false;
8826 bool active = false;
8827
8828 memset(&pipe_config, 0, sizeof(pipe_config));
8829
8830 DRM_DEBUG_KMS("[CRTC:%d]\n",
8831 crtc->base.base.id);
8832
8833 WARN(crtc->active && !crtc->base.enabled,
8834 "active crtc, but not enabled in sw tracking\n");
8835
8836 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8837 base.head) {
8838 if (encoder->base.crtc != &crtc->base)
8839 continue;
8840 enabled = true;
8841 if (encoder->connectors_active)
8842 active = true;
8843 }
8844
8845 WARN(active != crtc->active,
8846 "crtc's computed active state doesn't match tracked active state "
8847 "(expected %i, found %i)\n", active, crtc->active);
8848 WARN(enabled != crtc->base.enabled,
8849 "crtc's computed enabled state doesn't match tracked enabled state "
8850 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8851
8852 active = dev_priv->display.get_pipe_config(crtc,
8853 &pipe_config);
8854
8855 /* hw state is inconsistent with the pipe A quirk */
8856 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8857 active = crtc->active;
8858
8859 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8860 base.head) {
8861 enum pipe pipe;
8862 if (encoder->base.crtc != &crtc->base)
8863 continue;
8864 if (encoder->get_config &&
8865 encoder->get_hw_state(encoder, &pipe))
8866 encoder->get_config(encoder, &pipe_config);
8867 }
8868
8869 if (dev_priv->display.get_clock)
8870 dev_priv->display.get_clock(crtc, &pipe_config);
8871
8872 WARN(crtc->active != active,
8873 "crtc active state doesn't match with hw state "
8874 "(expected %i, found %i)\n", crtc->active, active);
8875
8876 if (active &&
8877 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8878 WARN(1, "pipe state doesn't match!\n");
8879 intel_dump_pipe_config(crtc, &pipe_config,
8880 "[hw state]");
8881 intel_dump_pipe_config(crtc, &crtc->config,
8882 "[sw state]");
8883 }
8884 }
8885 }
8886
8887 static void
8888 check_shared_dpll_state(struct drm_device *dev)
8889 {
8890 drm_i915_private_t *dev_priv = dev->dev_private;
8891 struct intel_crtc *crtc;
8892 struct intel_dpll_hw_state dpll_hw_state;
8893 int i;
8894
8895 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8896 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8897 int enabled_crtcs = 0, active_crtcs = 0;
8898 bool active;
8899
8900 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8901
8902 DRM_DEBUG_KMS("%s\n", pll->name);
8903
8904 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8905
8906 WARN(pll->active > pll->refcount,
8907 "more active pll users than references: %i vs %i\n",
8908 pll->active, pll->refcount);
8909 WARN(pll->active && !pll->on,
8910 "pll in active use but not on in sw tracking\n");
8911 WARN(pll->on && !pll->active,
8912 "pll in on but not on in use in sw tracking\n");
8913 WARN(pll->on != active,
8914 "pll on state mismatch (expected %i, found %i)\n",
8915 pll->on, active);
8916
8917 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8918 base.head) {
8919 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8920 enabled_crtcs++;
8921 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8922 active_crtcs++;
8923 }
8924 WARN(pll->active != active_crtcs,
8925 "pll active crtcs mismatch (expected %i, found %i)\n",
8926 pll->active, active_crtcs);
8927 WARN(pll->refcount != enabled_crtcs,
8928 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8929 pll->refcount, enabled_crtcs);
8930
8931 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8932 sizeof(dpll_hw_state)),
8933 "pll hw state mismatch\n");
8934 }
8935 }
8936
8937 void
8938 intel_modeset_check_state(struct drm_device *dev)
8939 {
8940 check_connector_state(dev);
8941 check_encoder_state(dev);
8942 check_crtc_state(dev);
8943 check_shared_dpll_state(dev);
8944 }
8945
8946 static int __intel_set_mode(struct drm_crtc *crtc,
8947 struct drm_display_mode *mode,
8948 int x, int y, struct drm_framebuffer *fb)
8949 {
8950 struct drm_device *dev = crtc->dev;
8951 drm_i915_private_t *dev_priv = dev->dev_private;
8952 struct drm_display_mode *saved_mode, *saved_hwmode;
8953 struct intel_crtc_config *pipe_config = NULL;
8954 struct intel_crtc *intel_crtc;
8955 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8956 int ret = 0;
8957
8958 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8959 if (!saved_mode)
8960 return -ENOMEM;
8961 saved_hwmode = saved_mode + 1;
8962
8963 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8964 &prepare_pipes, &disable_pipes);
8965
8966 *saved_hwmode = crtc->hwmode;
8967 *saved_mode = crtc->mode;
8968
8969 /* Hack: Because we don't (yet) support global modeset on multiple
8970 * crtcs, we don't keep track of the new mode for more than one crtc.
8971 * Hence simply check whether any bit is set in modeset_pipes in all the
8972 * pieces of code that are not yet converted to deal with mutliple crtcs
8973 * changing their mode at the same time. */
8974 if (modeset_pipes) {
8975 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8976 if (IS_ERR(pipe_config)) {
8977 ret = PTR_ERR(pipe_config);
8978 pipe_config = NULL;
8979
8980 goto out;
8981 }
8982 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8983 "[modeset]");
8984 }
8985
8986 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8987 intel_crtc_disable(&intel_crtc->base);
8988
8989 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8990 if (intel_crtc->base.enabled)
8991 dev_priv->display.crtc_disable(&intel_crtc->base);
8992 }
8993
8994 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8995 * to set it here already despite that we pass it down the callchain.
8996 */
8997 if (modeset_pipes) {
8998 crtc->mode = *mode;
8999 /* mode_set/enable/disable functions rely on a correct pipe
9000 * config. */
9001 to_intel_crtc(crtc)->config = *pipe_config;
9002 }
9003
9004 /* Only after disabling all output pipelines that will be changed can we
9005 * update the the output configuration. */
9006 intel_modeset_update_state(dev, prepare_pipes);
9007
9008 if (dev_priv->display.modeset_global_resources)
9009 dev_priv->display.modeset_global_resources(dev);
9010
9011 /* Set up the DPLL and any encoders state that needs to adjust or depend
9012 * on the DPLL.
9013 */
9014 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9015 ret = intel_crtc_mode_set(&intel_crtc->base,
9016 x, y, fb);
9017 if (ret)
9018 goto done;
9019 }
9020
9021 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9022 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9023 dev_priv->display.crtc_enable(&intel_crtc->base);
9024
9025 if (modeset_pipes) {
9026 /* Store real post-adjustment hardware mode. */
9027 crtc->hwmode = pipe_config->adjusted_mode;
9028
9029 /* Calculate and store various constants which
9030 * are later needed by vblank and swap-completion
9031 * timestamping. They are derived from true hwmode.
9032 */
9033 drm_calc_timestamping_constants(crtc);
9034 }
9035
9036 /* FIXME: add subpixel order */
9037 done:
9038 if (ret && crtc->enabled) {
9039 crtc->hwmode = *saved_hwmode;
9040 crtc->mode = *saved_mode;
9041 }
9042
9043 out:
9044 kfree(pipe_config);
9045 kfree(saved_mode);
9046 return ret;
9047 }
9048
9049 static int intel_set_mode(struct drm_crtc *crtc,
9050 struct drm_display_mode *mode,
9051 int x, int y, struct drm_framebuffer *fb)
9052 {
9053 int ret;
9054
9055 ret = __intel_set_mode(crtc, mode, x, y, fb);
9056
9057 if (ret == 0)
9058 intel_modeset_check_state(crtc->dev);
9059
9060 return ret;
9061 }
9062
9063 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9064 {
9065 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9066 }
9067
9068 #undef for_each_intel_crtc_masked
9069
9070 static void intel_set_config_free(struct intel_set_config *config)
9071 {
9072 if (!config)
9073 return;
9074
9075 kfree(config->save_connector_encoders);
9076 kfree(config->save_encoder_crtcs);
9077 kfree(config);
9078 }
9079
9080 static int intel_set_config_save_state(struct drm_device *dev,
9081 struct intel_set_config *config)
9082 {
9083 struct drm_encoder *encoder;
9084 struct drm_connector *connector;
9085 int count;
9086
9087 config->save_encoder_crtcs =
9088 kcalloc(dev->mode_config.num_encoder,
9089 sizeof(struct drm_crtc *), GFP_KERNEL);
9090 if (!config->save_encoder_crtcs)
9091 return -ENOMEM;
9092
9093 config->save_connector_encoders =
9094 kcalloc(dev->mode_config.num_connector,
9095 sizeof(struct drm_encoder *), GFP_KERNEL);
9096 if (!config->save_connector_encoders)
9097 return -ENOMEM;
9098
9099 /* Copy data. Note that driver private data is not affected.
9100 * Should anything bad happen only the expected state is
9101 * restored, not the drivers personal bookkeeping.
9102 */
9103 count = 0;
9104 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9105 config->save_encoder_crtcs[count++] = encoder->crtc;
9106 }
9107
9108 count = 0;
9109 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9110 config->save_connector_encoders[count++] = connector->encoder;
9111 }
9112
9113 return 0;
9114 }
9115
9116 static void intel_set_config_restore_state(struct drm_device *dev,
9117 struct intel_set_config *config)
9118 {
9119 struct intel_encoder *encoder;
9120 struct intel_connector *connector;
9121 int count;
9122
9123 count = 0;
9124 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9125 encoder->new_crtc =
9126 to_intel_crtc(config->save_encoder_crtcs[count++]);
9127 }
9128
9129 count = 0;
9130 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9131 connector->new_encoder =
9132 to_intel_encoder(config->save_connector_encoders[count++]);
9133 }
9134 }
9135
9136 static bool
9137 is_crtc_connector_off(struct drm_mode_set *set)
9138 {
9139 int i;
9140
9141 if (set->num_connectors == 0)
9142 return false;
9143
9144 if (WARN_ON(set->connectors == NULL))
9145 return false;
9146
9147 for (i = 0; i < set->num_connectors; i++)
9148 if (set->connectors[i]->encoder &&
9149 set->connectors[i]->encoder->crtc == set->crtc &&
9150 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9151 return true;
9152
9153 return false;
9154 }
9155
9156 static void
9157 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9158 struct intel_set_config *config)
9159 {
9160
9161 /* We should be able to check here if the fb has the same properties
9162 * and then just flip_or_move it */
9163 if (is_crtc_connector_off(set)) {
9164 config->mode_changed = true;
9165 } else if (set->crtc->fb != set->fb) {
9166 /* If we have no fb then treat it as a full mode set */
9167 if (set->crtc->fb == NULL) {
9168 struct intel_crtc *intel_crtc =
9169 to_intel_crtc(set->crtc);
9170
9171 if (intel_crtc->active && i915_fastboot) {
9172 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9173 config->fb_changed = true;
9174 } else {
9175 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9176 config->mode_changed = true;
9177 }
9178 } else if (set->fb == NULL) {
9179 config->mode_changed = true;
9180 } else if (set->fb->pixel_format !=
9181 set->crtc->fb->pixel_format) {
9182 config->mode_changed = true;
9183 } else {
9184 config->fb_changed = true;
9185 }
9186 }
9187
9188 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9189 config->fb_changed = true;
9190
9191 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9192 DRM_DEBUG_KMS("modes are different, full mode set\n");
9193 drm_mode_debug_printmodeline(&set->crtc->mode);
9194 drm_mode_debug_printmodeline(set->mode);
9195 config->mode_changed = true;
9196 }
9197
9198 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9199 set->crtc->base.id, config->mode_changed, config->fb_changed);
9200 }
9201
9202 static int
9203 intel_modeset_stage_output_state(struct drm_device *dev,
9204 struct drm_mode_set *set,
9205 struct intel_set_config *config)
9206 {
9207 struct drm_crtc *new_crtc;
9208 struct intel_connector *connector;
9209 struct intel_encoder *encoder;
9210 int ro;
9211
9212 /* The upper layers ensure that we either disable a crtc or have a list
9213 * of connectors. For paranoia, double-check this. */
9214 WARN_ON(!set->fb && (set->num_connectors != 0));
9215 WARN_ON(set->fb && (set->num_connectors == 0));
9216
9217 list_for_each_entry(connector, &dev->mode_config.connector_list,
9218 base.head) {
9219 /* Otherwise traverse passed in connector list and get encoders
9220 * for them. */
9221 for (ro = 0; ro < set->num_connectors; ro++) {
9222 if (set->connectors[ro] == &connector->base) {
9223 connector->new_encoder = connector->encoder;
9224 break;
9225 }
9226 }
9227
9228 /* If we disable the crtc, disable all its connectors. Also, if
9229 * the connector is on the changing crtc but not on the new
9230 * connector list, disable it. */
9231 if ((!set->fb || ro == set->num_connectors) &&
9232 connector->base.encoder &&
9233 connector->base.encoder->crtc == set->crtc) {
9234 connector->new_encoder = NULL;
9235
9236 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9237 connector->base.base.id,
9238 drm_get_connector_name(&connector->base));
9239 }
9240
9241
9242 if (&connector->new_encoder->base != connector->base.encoder) {
9243 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9244 config->mode_changed = true;
9245 }
9246 }
9247 /* connector->new_encoder is now updated for all connectors. */
9248
9249 /* Update crtc of enabled connectors. */
9250 list_for_each_entry(connector, &dev->mode_config.connector_list,
9251 base.head) {
9252 if (!connector->new_encoder)
9253 continue;
9254
9255 new_crtc = connector->new_encoder->base.crtc;
9256
9257 for (ro = 0; ro < set->num_connectors; ro++) {
9258 if (set->connectors[ro] == &connector->base)
9259 new_crtc = set->crtc;
9260 }
9261
9262 /* Make sure the new CRTC will work with the encoder */
9263 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9264 new_crtc)) {
9265 return -EINVAL;
9266 }
9267 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9268
9269 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9270 connector->base.base.id,
9271 drm_get_connector_name(&connector->base),
9272 new_crtc->base.id);
9273 }
9274
9275 /* Check for any encoders that needs to be disabled. */
9276 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9277 base.head) {
9278 list_for_each_entry(connector,
9279 &dev->mode_config.connector_list,
9280 base.head) {
9281 if (connector->new_encoder == encoder) {
9282 WARN_ON(!connector->new_encoder->new_crtc);
9283
9284 goto next_encoder;
9285 }
9286 }
9287 encoder->new_crtc = NULL;
9288 next_encoder:
9289 /* Only now check for crtc changes so we don't miss encoders
9290 * that will be disabled. */
9291 if (&encoder->new_crtc->base != encoder->base.crtc) {
9292 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9293 config->mode_changed = true;
9294 }
9295 }
9296 /* Now we've also updated encoder->new_crtc for all encoders. */
9297
9298 return 0;
9299 }
9300
9301 static int intel_crtc_set_config(struct drm_mode_set *set)
9302 {
9303 struct drm_device *dev;
9304 struct drm_mode_set save_set;
9305 struct intel_set_config *config;
9306 int ret;
9307
9308 BUG_ON(!set);
9309 BUG_ON(!set->crtc);
9310 BUG_ON(!set->crtc->helper_private);
9311
9312 /* Enforce sane interface api - has been abused by the fb helper. */
9313 BUG_ON(!set->mode && set->fb);
9314 BUG_ON(set->fb && set->num_connectors == 0);
9315
9316 if (set->fb) {
9317 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9318 set->crtc->base.id, set->fb->base.id,
9319 (int)set->num_connectors, set->x, set->y);
9320 } else {
9321 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9322 }
9323
9324 dev = set->crtc->dev;
9325
9326 ret = -ENOMEM;
9327 config = kzalloc(sizeof(*config), GFP_KERNEL);
9328 if (!config)
9329 goto out_config;
9330
9331 ret = intel_set_config_save_state(dev, config);
9332 if (ret)
9333 goto out_config;
9334
9335 save_set.crtc = set->crtc;
9336 save_set.mode = &set->crtc->mode;
9337 save_set.x = set->crtc->x;
9338 save_set.y = set->crtc->y;
9339 save_set.fb = set->crtc->fb;
9340
9341 /* Compute whether we need a full modeset, only an fb base update or no
9342 * change at all. In the future we might also check whether only the
9343 * mode changed, e.g. for LVDS where we only change the panel fitter in
9344 * such cases. */
9345 intel_set_config_compute_mode_changes(set, config);
9346
9347 ret = intel_modeset_stage_output_state(dev, set, config);
9348 if (ret)
9349 goto fail;
9350
9351 if (config->mode_changed) {
9352 ret = intel_set_mode(set->crtc, set->mode,
9353 set->x, set->y, set->fb);
9354 } else if (config->fb_changed) {
9355 intel_crtc_wait_for_pending_flips(set->crtc);
9356
9357 ret = intel_pipe_set_base(set->crtc,
9358 set->x, set->y, set->fb);
9359 }
9360
9361 if (ret) {
9362 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9363 set->crtc->base.id, ret);
9364 fail:
9365 intel_set_config_restore_state(dev, config);
9366
9367 /* Try to restore the config */
9368 if (config->mode_changed &&
9369 intel_set_mode(save_set.crtc, save_set.mode,
9370 save_set.x, save_set.y, save_set.fb))
9371 DRM_ERROR("failed to restore config after modeset failure\n");
9372 }
9373
9374 out_config:
9375 intel_set_config_free(config);
9376 return ret;
9377 }
9378
9379 static const struct drm_crtc_funcs intel_crtc_funcs = {
9380 .cursor_set = intel_crtc_cursor_set,
9381 .cursor_move = intel_crtc_cursor_move,
9382 .gamma_set = intel_crtc_gamma_set,
9383 .set_config = intel_crtc_set_config,
9384 .destroy = intel_crtc_destroy,
9385 .page_flip = intel_crtc_page_flip,
9386 };
9387
9388 static void intel_cpu_pll_init(struct drm_device *dev)
9389 {
9390 if (HAS_DDI(dev))
9391 intel_ddi_pll_init(dev);
9392 }
9393
9394 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9395 struct intel_shared_dpll *pll,
9396 struct intel_dpll_hw_state *hw_state)
9397 {
9398 uint32_t val;
9399
9400 val = I915_READ(PCH_DPLL(pll->id));
9401 hw_state->dpll = val;
9402 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9403 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9404
9405 return val & DPLL_VCO_ENABLE;
9406 }
9407
9408 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9409 struct intel_shared_dpll *pll)
9410 {
9411 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9412 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9413 }
9414
9415 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9416 struct intel_shared_dpll *pll)
9417 {
9418 /* PCH refclock must be enabled first */
9419 assert_pch_refclk_enabled(dev_priv);
9420
9421 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9422
9423 /* Wait for the clocks to stabilize. */
9424 POSTING_READ(PCH_DPLL(pll->id));
9425 udelay(150);
9426
9427 /* The pixel multiplier can only be updated once the
9428 * DPLL is enabled and the clocks are stable.
9429 *
9430 * So write it again.
9431 */
9432 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9433 POSTING_READ(PCH_DPLL(pll->id));
9434 udelay(200);
9435 }
9436
9437 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9438 struct intel_shared_dpll *pll)
9439 {
9440 struct drm_device *dev = dev_priv->dev;
9441 struct intel_crtc *crtc;
9442
9443 /* Make sure no transcoder isn't still depending on us. */
9444 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9445 if (intel_crtc_to_shared_dpll(crtc) == pll)
9446 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9447 }
9448
9449 I915_WRITE(PCH_DPLL(pll->id), 0);
9450 POSTING_READ(PCH_DPLL(pll->id));
9451 udelay(200);
9452 }
9453
9454 static char *ibx_pch_dpll_names[] = {
9455 "PCH DPLL A",
9456 "PCH DPLL B",
9457 };
9458
9459 static void ibx_pch_dpll_init(struct drm_device *dev)
9460 {
9461 struct drm_i915_private *dev_priv = dev->dev_private;
9462 int i;
9463
9464 dev_priv->num_shared_dpll = 2;
9465
9466 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9467 dev_priv->shared_dplls[i].id = i;
9468 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9469 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9470 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9471 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9472 dev_priv->shared_dplls[i].get_hw_state =
9473 ibx_pch_dpll_get_hw_state;
9474 }
9475 }
9476
9477 static void intel_shared_dpll_init(struct drm_device *dev)
9478 {
9479 struct drm_i915_private *dev_priv = dev->dev_private;
9480
9481 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9482 ibx_pch_dpll_init(dev);
9483 else
9484 dev_priv->num_shared_dpll = 0;
9485
9486 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9487 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9488 dev_priv->num_shared_dpll);
9489 }
9490
9491 static void intel_crtc_init(struct drm_device *dev, int pipe)
9492 {
9493 drm_i915_private_t *dev_priv = dev->dev_private;
9494 struct intel_crtc *intel_crtc;
9495 int i;
9496
9497 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9498 if (intel_crtc == NULL)
9499 return;
9500
9501 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9502
9503 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9504 for (i = 0; i < 256; i++) {
9505 intel_crtc->lut_r[i] = i;
9506 intel_crtc->lut_g[i] = i;
9507 intel_crtc->lut_b[i] = i;
9508 }
9509
9510 /* Swap pipes & planes for FBC on pre-965 */
9511 intel_crtc->pipe = pipe;
9512 intel_crtc->plane = pipe;
9513 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9514 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9515 intel_crtc->plane = !pipe;
9516 }
9517
9518 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9519 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9520 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9521 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9522
9523 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9524 }
9525
9526 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9527 struct drm_file *file)
9528 {
9529 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9530 struct drm_mode_object *drmmode_obj;
9531 struct intel_crtc *crtc;
9532
9533 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9534 return -ENODEV;
9535
9536 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9537 DRM_MODE_OBJECT_CRTC);
9538
9539 if (!drmmode_obj) {
9540 DRM_ERROR("no such CRTC id\n");
9541 return -EINVAL;
9542 }
9543
9544 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9545 pipe_from_crtc_id->pipe = crtc->pipe;
9546
9547 return 0;
9548 }
9549
9550 static int intel_encoder_clones(struct intel_encoder *encoder)
9551 {
9552 struct drm_device *dev = encoder->base.dev;
9553 struct intel_encoder *source_encoder;
9554 int index_mask = 0;
9555 int entry = 0;
9556
9557 list_for_each_entry(source_encoder,
9558 &dev->mode_config.encoder_list, base.head) {
9559
9560 if (encoder == source_encoder)
9561 index_mask |= (1 << entry);
9562
9563 /* Intel hw has only one MUX where enocoders could be cloned. */
9564 if (encoder->cloneable && source_encoder->cloneable)
9565 index_mask |= (1 << entry);
9566
9567 entry++;
9568 }
9569
9570 return index_mask;
9571 }
9572
9573 static bool has_edp_a(struct drm_device *dev)
9574 {
9575 struct drm_i915_private *dev_priv = dev->dev_private;
9576
9577 if (!IS_MOBILE(dev))
9578 return false;
9579
9580 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9581 return false;
9582
9583 if (IS_GEN5(dev) &&
9584 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9585 return false;
9586
9587 return true;
9588 }
9589
9590 static void intel_setup_outputs(struct drm_device *dev)
9591 {
9592 struct drm_i915_private *dev_priv = dev->dev_private;
9593 struct intel_encoder *encoder;
9594 bool dpd_is_edp = false;
9595
9596 intel_lvds_init(dev);
9597
9598 if (!IS_ULT(dev))
9599 intel_crt_init(dev);
9600
9601 if (HAS_DDI(dev)) {
9602 int found;
9603
9604 /* Haswell uses DDI functions to detect digital outputs */
9605 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9606 /* DDI A only supports eDP */
9607 if (found)
9608 intel_ddi_init(dev, PORT_A);
9609
9610 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9611 * register */
9612 found = I915_READ(SFUSE_STRAP);
9613
9614 if (found & SFUSE_STRAP_DDIB_DETECTED)
9615 intel_ddi_init(dev, PORT_B);
9616 if (found & SFUSE_STRAP_DDIC_DETECTED)
9617 intel_ddi_init(dev, PORT_C);
9618 if (found & SFUSE_STRAP_DDID_DETECTED)
9619 intel_ddi_init(dev, PORT_D);
9620 } else if (HAS_PCH_SPLIT(dev)) {
9621 int found;
9622 dpd_is_edp = intel_dpd_is_edp(dev);
9623
9624 if (has_edp_a(dev))
9625 intel_dp_init(dev, DP_A, PORT_A);
9626
9627 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9628 /* PCH SDVOB multiplex with HDMIB */
9629 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9630 if (!found)
9631 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9632 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9633 intel_dp_init(dev, PCH_DP_B, PORT_B);
9634 }
9635
9636 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9637 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9638
9639 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9640 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9641
9642 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9643 intel_dp_init(dev, PCH_DP_C, PORT_C);
9644
9645 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9646 intel_dp_init(dev, PCH_DP_D, PORT_D);
9647 } else if (IS_VALLEYVIEW(dev)) {
9648 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9649 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9650 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9651 PORT_C);
9652 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9653 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9654 PORT_C);
9655 }
9656
9657 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9658 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9659 PORT_B);
9660 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9661 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9662 }
9663 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9664 bool found = false;
9665
9666 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9667 DRM_DEBUG_KMS("probing SDVOB\n");
9668 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9669 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9670 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9671 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9672 }
9673
9674 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9675 intel_dp_init(dev, DP_B, PORT_B);
9676 }
9677
9678 /* Before G4X SDVOC doesn't have its own detect register */
9679
9680 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9681 DRM_DEBUG_KMS("probing SDVOC\n");
9682 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9683 }
9684
9685 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9686
9687 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9688 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9689 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9690 }
9691 if (SUPPORTS_INTEGRATED_DP(dev))
9692 intel_dp_init(dev, DP_C, PORT_C);
9693 }
9694
9695 if (SUPPORTS_INTEGRATED_DP(dev) &&
9696 (I915_READ(DP_D) & DP_DETECTED))
9697 intel_dp_init(dev, DP_D, PORT_D);
9698 } else if (IS_GEN2(dev))
9699 intel_dvo_init(dev);
9700
9701 if (SUPPORTS_TV(dev))
9702 intel_tv_init(dev);
9703
9704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9705 encoder->base.possible_crtcs = encoder->crtc_mask;
9706 encoder->base.possible_clones =
9707 intel_encoder_clones(encoder);
9708 }
9709
9710 intel_init_pch_refclk(dev);
9711
9712 drm_helper_move_panel_connectors_to_head(dev);
9713 }
9714
9715 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9716 {
9717 drm_framebuffer_cleanup(&fb->base);
9718 drm_gem_object_unreference_unlocked(&fb->obj->base);
9719 }
9720
9721 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9722 {
9723 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9724
9725 intel_framebuffer_fini(intel_fb);
9726 kfree(intel_fb);
9727 }
9728
9729 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9730 struct drm_file *file,
9731 unsigned int *handle)
9732 {
9733 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9734 struct drm_i915_gem_object *obj = intel_fb->obj;
9735
9736 return drm_gem_handle_create(file, &obj->base, handle);
9737 }
9738
9739 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9740 .destroy = intel_user_framebuffer_destroy,
9741 .create_handle = intel_user_framebuffer_create_handle,
9742 };
9743
9744 int intel_framebuffer_init(struct drm_device *dev,
9745 struct intel_framebuffer *intel_fb,
9746 struct drm_mode_fb_cmd2 *mode_cmd,
9747 struct drm_i915_gem_object *obj)
9748 {
9749 int pitch_limit;
9750 int ret;
9751
9752 if (obj->tiling_mode == I915_TILING_Y) {
9753 DRM_DEBUG("hardware does not support tiling Y\n");
9754 return -EINVAL;
9755 }
9756
9757 if (mode_cmd->pitches[0] & 63) {
9758 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9759 mode_cmd->pitches[0]);
9760 return -EINVAL;
9761 }
9762
9763 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9764 pitch_limit = 32*1024;
9765 } else if (INTEL_INFO(dev)->gen >= 4) {
9766 if (obj->tiling_mode)
9767 pitch_limit = 16*1024;
9768 else
9769 pitch_limit = 32*1024;
9770 } else if (INTEL_INFO(dev)->gen >= 3) {
9771 if (obj->tiling_mode)
9772 pitch_limit = 8*1024;
9773 else
9774 pitch_limit = 16*1024;
9775 } else
9776 /* XXX DSPC is limited to 4k tiled */
9777 pitch_limit = 8*1024;
9778
9779 if (mode_cmd->pitches[0] > pitch_limit) {
9780 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9781 obj->tiling_mode ? "tiled" : "linear",
9782 mode_cmd->pitches[0], pitch_limit);
9783 return -EINVAL;
9784 }
9785
9786 if (obj->tiling_mode != I915_TILING_NONE &&
9787 mode_cmd->pitches[0] != obj->stride) {
9788 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9789 mode_cmd->pitches[0], obj->stride);
9790 return -EINVAL;
9791 }
9792
9793 /* Reject formats not supported by any plane early. */
9794 switch (mode_cmd->pixel_format) {
9795 case DRM_FORMAT_C8:
9796 case DRM_FORMAT_RGB565:
9797 case DRM_FORMAT_XRGB8888:
9798 case DRM_FORMAT_ARGB8888:
9799 break;
9800 case DRM_FORMAT_XRGB1555:
9801 case DRM_FORMAT_ARGB1555:
9802 if (INTEL_INFO(dev)->gen > 3) {
9803 DRM_DEBUG("unsupported pixel format: %s\n",
9804 drm_get_format_name(mode_cmd->pixel_format));
9805 return -EINVAL;
9806 }
9807 break;
9808 case DRM_FORMAT_XBGR8888:
9809 case DRM_FORMAT_ABGR8888:
9810 case DRM_FORMAT_XRGB2101010:
9811 case DRM_FORMAT_ARGB2101010:
9812 case DRM_FORMAT_XBGR2101010:
9813 case DRM_FORMAT_ABGR2101010:
9814 if (INTEL_INFO(dev)->gen < 4) {
9815 DRM_DEBUG("unsupported pixel format: %s\n",
9816 drm_get_format_name(mode_cmd->pixel_format));
9817 return -EINVAL;
9818 }
9819 break;
9820 case DRM_FORMAT_YUYV:
9821 case DRM_FORMAT_UYVY:
9822 case DRM_FORMAT_YVYU:
9823 case DRM_FORMAT_VYUY:
9824 if (INTEL_INFO(dev)->gen < 5) {
9825 DRM_DEBUG("unsupported pixel format: %s\n",
9826 drm_get_format_name(mode_cmd->pixel_format));
9827 return -EINVAL;
9828 }
9829 break;
9830 default:
9831 DRM_DEBUG("unsupported pixel format: %s\n",
9832 drm_get_format_name(mode_cmd->pixel_format));
9833 return -EINVAL;
9834 }
9835
9836 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9837 if (mode_cmd->offsets[0] != 0)
9838 return -EINVAL;
9839
9840 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9841 intel_fb->obj = obj;
9842
9843 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9844 if (ret) {
9845 DRM_ERROR("framebuffer init failed %d\n", ret);
9846 return ret;
9847 }
9848
9849 return 0;
9850 }
9851
9852 static struct drm_framebuffer *
9853 intel_user_framebuffer_create(struct drm_device *dev,
9854 struct drm_file *filp,
9855 struct drm_mode_fb_cmd2 *mode_cmd)
9856 {
9857 struct drm_i915_gem_object *obj;
9858
9859 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9860 mode_cmd->handles[0]));
9861 if (&obj->base == NULL)
9862 return ERR_PTR(-ENOENT);
9863
9864 return intel_framebuffer_create(dev, mode_cmd, obj);
9865 }
9866
9867 static const struct drm_mode_config_funcs intel_mode_funcs = {
9868 .fb_create = intel_user_framebuffer_create,
9869 .output_poll_changed = intel_fb_output_poll_changed,
9870 };
9871
9872 /* Set up chip specific display functions */
9873 static void intel_init_display(struct drm_device *dev)
9874 {
9875 struct drm_i915_private *dev_priv = dev->dev_private;
9876
9877 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9878 dev_priv->display.find_dpll = g4x_find_best_dpll;
9879 else if (IS_VALLEYVIEW(dev))
9880 dev_priv->display.find_dpll = vlv_find_best_dpll;
9881 else if (IS_PINEVIEW(dev))
9882 dev_priv->display.find_dpll = pnv_find_best_dpll;
9883 else
9884 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9885
9886 if (HAS_DDI(dev)) {
9887 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9888 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9889 dev_priv->display.crtc_enable = haswell_crtc_enable;
9890 dev_priv->display.crtc_disable = haswell_crtc_disable;
9891 dev_priv->display.off = haswell_crtc_off;
9892 dev_priv->display.update_plane = ironlake_update_plane;
9893 } else if (HAS_PCH_SPLIT(dev)) {
9894 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9895 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9896 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9897 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9898 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9899 dev_priv->display.off = ironlake_crtc_off;
9900 dev_priv->display.update_plane = ironlake_update_plane;
9901 } else if (IS_VALLEYVIEW(dev)) {
9902 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9903 dev_priv->display.get_clock = vlv_crtc_clock_get;
9904 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9905 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9906 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9907 dev_priv->display.off = i9xx_crtc_off;
9908 dev_priv->display.update_plane = i9xx_update_plane;
9909 } else {
9910 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9911 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9912 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9913 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9914 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9915 dev_priv->display.off = i9xx_crtc_off;
9916 dev_priv->display.update_plane = i9xx_update_plane;
9917 }
9918
9919 /* Returns the core display clock speed */
9920 if (IS_VALLEYVIEW(dev))
9921 dev_priv->display.get_display_clock_speed =
9922 valleyview_get_display_clock_speed;
9923 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9924 dev_priv->display.get_display_clock_speed =
9925 i945_get_display_clock_speed;
9926 else if (IS_I915G(dev))
9927 dev_priv->display.get_display_clock_speed =
9928 i915_get_display_clock_speed;
9929 else if (IS_I945GM(dev) || IS_845G(dev))
9930 dev_priv->display.get_display_clock_speed =
9931 i9xx_misc_get_display_clock_speed;
9932 else if (IS_PINEVIEW(dev))
9933 dev_priv->display.get_display_clock_speed =
9934 pnv_get_display_clock_speed;
9935 else if (IS_I915GM(dev))
9936 dev_priv->display.get_display_clock_speed =
9937 i915gm_get_display_clock_speed;
9938 else if (IS_I865G(dev))
9939 dev_priv->display.get_display_clock_speed =
9940 i865_get_display_clock_speed;
9941 else if (IS_I85X(dev))
9942 dev_priv->display.get_display_clock_speed =
9943 i855_get_display_clock_speed;
9944 else /* 852, 830 */
9945 dev_priv->display.get_display_clock_speed =
9946 i830_get_display_clock_speed;
9947
9948 if (HAS_PCH_SPLIT(dev)) {
9949 if (IS_GEN5(dev)) {
9950 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9951 dev_priv->display.write_eld = ironlake_write_eld;
9952 } else if (IS_GEN6(dev)) {
9953 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9954 dev_priv->display.write_eld = ironlake_write_eld;
9955 } else if (IS_IVYBRIDGE(dev)) {
9956 /* FIXME: detect B0+ stepping and use auto training */
9957 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9958 dev_priv->display.write_eld = ironlake_write_eld;
9959 dev_priv->display.modeset_global_resources =
9960 ivb_modeset_global_resources;
9961 } else if (IS_HASWELL(dev)) {
9962 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9963 dev_priv->display.write_eld = haswell_write_eld;
9964 dev_priv->display.modeset_global_resources =
9965 haswell_modeset_global_resources;
9966 }
9967 } else if (IS_G4X(dev)) {
9968 dev_priv->display.write_eld = g4x_write_eld;
9969 }
9970
9971 /* Default just returns -ENODEV to indicate unsupported */
9972 dev_priv->display.queue_flip = intel_default_queue_flip;
9973
9974 switch (INTEL_INFO(dev)->gen) {
9975 case 2:
9976 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9977 break;
9978
9979 case 3:
9980 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9981 break;
9982
9983 case 4:
9984 case 5:
9985 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9986 break;
9987
9988 case 6:
9989 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9990 break;
9991 case 7:
9992 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9993 break;
9994 }
9995 }
9996
9997 /*
9998 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9999 * resume, or other times. This quirk makes sure that's the case for
10000 * affected systems.
10001 */
10002 static void quirk_pipea_force(struct drm_device *dev)
10003 {
10004 struct drm_i915_private *dev_priv = dev->dev_private;
10005
10006 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10007 DRM_INFO("applying pipe a force quirk\n");
10008 }
10009
10010 /*
10011 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10012 */
10013 static void quirk_ssc_force_disable(struct drm_device *dev)
10014 {
10015 struct drm_i915_private *dev_priv = dev->dev_private;
10016 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10017 DRM_INFO("applying lvds SSC disable quirk\n");
10018 }
10019
10020 /*
10021 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10022 * brightness value
10023 */
10024 static void quirk_invert_brightness(struct drm_device *dev)
10025 {
10026 struct drm_i915_private *dev_priv = dev->dev_private;
10027 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10028 DRM_INFO("applying inverted panel brightness quirk\n");
10029 }
10030
10031 /*
10032 * Some machines (Dell XPS13) suffer broken backlight controls if
10033 * BLM_PCH_PWM_ENABLE is set.
10034 */
10035 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10036 {
10037 struct drm_i915_private *dev_priv = dev->dev_private;
10038 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10039 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10040 }
10041
10042 struct intel_quirk {
10043 int device;
10044 int subsystem_vendor;
10045 int subsystem_device;
10046 void (*hook)(struct drm_device *dev);
10047 };
10048
10049 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10050 struct intel_dmi_quirk {
10051 void (*hook)(struct drm_device *dev);
10052 const struct dmi_system_id (*dmi_id_list)[];
10053 };
10054
10055 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10056 {
10057 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10058 return 1;
10059 }
10060
10061 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10062 {
10063 .dmi_id_list = &(const struct dmi_system_id[]) {
10064 {
10065 .callback = intel_dmi_reverse_brightness,
10066 .ident = "NCR Corporation",
10067 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10068 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10069 },
10070 },
10071 { } /* terminating entry */
10072 },
10073 .hook = quirk_invert_brightness,
10074 },
10075 };
10076
10077 static struct intel_quirk intel_quirks[] = {
10078 /* HP Mini needs pipe A force quirk (LP: #322104) */
10079 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10080
10081 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10082 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10083
10084 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10085 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10086
10087 /* 830 needs to leave pipe A & dpll A up */
10088 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10089
10090 /* Lenovo U160 cannot use SSC on LVDS */
10091 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10092
10093 /* Sony Vaio Y cannot use SSC on LVDS */
10094 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10095
10096 /* Acer Aspire 5734Z must invert backlight brightness */
10097 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10098
10099 /* Acer/eMachines G725 */
10100 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10101
10102 /* Acer/eMachines e725 */
10103 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10104
10105 /* Acer/Packard Bell NCL20 */
10106 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10107
10108 /* Acer Aspire 4736Z */
10109 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10110
10111 /* Acer Aspire 5336 */
10112 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
10113
10114 /* Dell XPS13 HD Sandy Bridge */
10115 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10116 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10117 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10118 };
10119
10120 static void intel_init_quirks(struct drm_device *dev)
10121 {
10122 struct pci_dev *d = dev->pdev;
10123 int i;
10124
10125 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10126 struct intel_quirk *q = &intel_quirks[i];
10127
10128 if (d->device == q->device &&
10129 (d->subsystem_vendor == q->subsystem_vendor ||
10130 q->subsystem_vendor == PCI_ANY_ID) &&
10131 (d->subsystem_device == q->subsystem_device ||
10132 q->subsystem_device == PCI_ANY_ID))
10133 q->hook(dev);
10134 }
10135 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10136 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10137 intel_dmi_quirks[i].hook(dev);
10138 }
10139 }
10140
10141 /* Disable the VGA plane that we never use */
10142 static void i915_disable_vga(struct drm_device *dev)
10143 {
10144 struct drm_i915_private *dev_priv = dev->dev_private;
10145 u8 sr1;
10146 u32 vga_reg = i915_vgacntrl_reg(dev);
10147
10148 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10149 outb(SR01, VGA_SR_INDEX);
10150 sr1 = inb(VGA_SR_DATA);
10151 outb(sr1 | 1<<5, VGA_SR_DATA);
10152 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10153 udelay(300);
10154
10155 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10156 POSTING_READ(vga_reg);
10157 }
10158
10159 void intel_modeset_init_hw(struct drm_device *dev)
10160 {
10161 struct drm_i915_private *dev_priv = dev->dev_private;
10162
10163 intel_init_power_well(dev);
10164
10165 intel_prepare_ddi(dev);
10166
10167 intel_init_clock_gating(dev);
10168
10169 /* Enable the CRI clock source so we can get at the display */
10170 if (IS_VALLEYVIEW(dev))
10171 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10172 DPLL_INTEGRATED_CRI_CLK_VLV);
10173
10174 mutex_lock(&dev->struct_mutex);
10175 intel_enable_gt_powersave(dev);
10176 mutex_unlock(&dev->struct_mutex);
10177 }
10178
10179 void intel_modeset_suspend_hw(struct drm_device *dev)
10180 {
10181 intel_suspend_hw(dev);
10182 }
10183
10184 void intel_modeset_init(struct drm_device *dev)
10185 {
10186 struct drm_i915_private *dev_priv = dev->dev_private;
10187 int i, j, ret;
10188
10189 drm_mode_config_init(dev);
10190
10191 dev->mode_config.min_width = 0;
10192 dev->mode_config.min_height = 0;
10193
10194 dev->mode_config.preferred_depth = 24;
10195 dev->mode_config.prefer_shadow = 1;
10196
10197 dev->mode_config.funcs = &intel_mode_funcs;
10198
10199 intel_init_quirks(dev);
10200
10201 intel_init_pm(dev);
10202
10203 if (INTEL_INFO(dev)->num_pipes == 0)
10204 return;
10205
10206 intel_init_display(dev);
10207
10208 if (IS_GEN2(dev)) {
10209 dev->mode_config.max_width = 2048;
10210 dev->mode_config.max_height = 2048;
10211 } else if (IS_GEN3(dev)) {
10212 dev->mode_config.max_width = 4096;
10213 dev->mode_config.max_height = 4096;
10214 } else {
10215 dev->mode_config.max_width = 8192;
10216 dev->mode_config.max_height = 8192;
10217 }
10218 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10219
10220 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10221 INTEL_INFO(dev)->num_pipes,
10222 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10223
10224 for_each_pipe(i) {
10225 intel_crtc_init(dev, i);
10226 for (j = 0; j < dev_priv->num_plane; j++) {
10227 ret = intel_plane_init(dev, i, j);
10228 if (ret)
10229 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10230 pipe_name(i), sprite_name(i, j), ret);
10231 }
10232 }
10233
10234 intel_cpu_pll_init(dev);
10235 intel_shared_dpll_init(dev);
10236
10237 /* Just disable it once at startup */
10238 i915_disable_vga(dev);
10239 intel_setup_outputs(dev);
10240
10241 /* Just in case the BIOS is doing something questionable. */
10242 intel_disable_fbc(dev);
10243 }
10244
10245 static void intel_enable_pipe_a(struct drm_device *dev)
10246 {
10247 struct intel_connector *connector;
10248 struct drm_connector *crt = NULL;
10249 struct intel_load_detect_pipe load_detect_temp;
10250
10251 /* We can't just switch on the pipe A, we need to set things up with a
10252 * proper mode and output configuration. As a gross hack, enable pipe A
10253 * by enabling the load detect pipe once. */
10254 list_for_each_entry(connector,
10255 &dev->mode_config.connector_list,
10256 base.head) {
10257 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10258 crt = &connector->base;
10259 break;
10260 }
10261 }
10262
10263 if (!crt)
10264 return;
10265
10266 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10267 intel_release_load_detect_pipe(crt, &load_detect_temp);
10268
10269
10270 }
10271
10272 static bool
10273 intel_check_plane_mapping(struct intel_crtc *crtc)
10274 {
10275 struct drm_device *dev = crtc->base.dev;
10276 struct drm_i915_private *dev_priv = dev->dev_private;
10277 u32 reg, val;
10278
10279 if (INTEL_INFO(dev)->num_pipes == 1)
10280 return true;
10281
10282 reg = DSPCNTR(!crtc->plane);
10283 val = I915_READ(reg);
10284
10285 if ((val & DISPLAY_PLANE_ENABLE) &&
10286 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10287 return false;
10288
10289 return true;
10290 }
10291
10292 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10293 {
10294 struct drm_device *dev = crtc->base.dev;
10295 struct drm_i915_private *dev_priv = dev->dev_private;
10296 u32 reg;
10297
10298 /* Clear any frame start delays used for debugging left by the BIOS */
10299 reg = PIPECONF(crtc->config.cpu_transcoder);
10300 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10301
10302 /* We need to sanitize the plane -> pipe mapping first because this will
10303 * disable the crtc (and hence change the state) if it is wrong. Note
10304 * that gen4+ has a fixed plane -> pipe mapping. */
10305 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10306 struct intel_connector *connector;
10307 bool plane;
10308
10309 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10310 crtc->base.base.id);
10311
10312 /* Pipe has the wrong plane attached and the plane is active.
10313 * Temporarily change the plane mapping and disable everything
10314 * ... */
10315 plane = crtc->plane;
10316 crtc->plane = !plane;
10317 dev_priv->display.crtc_disable(&crtc->base);
10318 crtc->plane = plane;
10319
10320 /* ... and break all links. */
10321 list_for_each_entry(connector, &dev->mode_config.connector_list,
10322 base.head) {
10323 if (connector->encoder->base.crtc != &crtc->base)
10324 continue;
10325
10326 connector->base.dpms = DRM_MODE_DPMS_OFF;
10327 connector->base.encoder = NULL;
10328 }
10329 /* multiple connectors may have the same encoder:
10330 * handle them and break crtc link separately */
10331 list_for_each_entry(connector, &dev->mode_config.connector_list,
10332 base.head)
10333 if (connector->encoder->base.crtc == &crtc->base) {
10334 connector->encoder->base.crtc = NULL;
10335 connector->encoder->connectors_active = false;
10336 }
10337
10338 WARN_ON(crtc->active);
10339 crtc->base.enabled = false;
10340 }
10341
10342 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10343 crtc->pipe == PIPE_A && !crtc->active) {
10344 /* BIOS forgot to enable pipe A, this mostly happens after
10345 * resume. Force-enable the pipe to fix this, the update_dpms
10346 * call below we restore the pipe to the right state, but leave
10347 * the required bits on. */
10348 intel_enable_pipe_a(dev);
10349 }
10350
10351 /* Adjust the state of the output pipe according to whether we
10352 * have active connectors/encoders. */
10353 intel_crtc_update_dpms(&crtc->base);
10354
10355 if (crtc->active != crtc->base.enabled) {
10356 struct intel_encoder *encoder;
10357
10358 /* This can happen either due to bugs in the get_hw_state
10359 * functions or because the pipe is force-enabled due to the
10360 * pipe A quirk. */
10361 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10362 crtc->base.base.id,
10363 crtc->base.enabled ? "enabled" : "disabled",
10364 crtc->active ? "enabled" : "disabled");
10365
10366 crtc->base.enabled = crtc->active;
10367
10368 /* Because we only establish the connector -> encoder ->
10369 * crtc links if something is active, this means the
10370 * crtc is now deactivated. Break the links. connector
10371 * -> encoder links are only establish when things are
10372 * actually up, hence no need to break them. */
10373 WARN_ON(crtc->active);
10374
10375 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10376 WARN_ON(encoder->connectors_active);
10377 encoder->base.crtc = NULL;
10378 }
10379 }
10380 }
10381
10382 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10383 {
10384 struct intel_connector *connector;
10385 struct drm_device *dev = encoder->base.dev;
10386
10387 /* We need to check both for a crtc link (meaning that the
10388 * encoder is active and trying to read from a pipe) and the
10389 * pipe itself being active. */
10390 bool has_active_crtc = encoder->base.crtc &&
10391 to_intel_crtc(encoder->base.crtc)->active;
10392
10393 if (encoder->connectors_active && !has_active_crtc) {
10394 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10395 encoder->base.base.id,
10396 drm_get_encoder_name(&encoder->base));
10397
10398 /* Connector is active, but has no active pipe. This is
10399 * fallout from our resume register restoring. Disable
10400 * the encoder manually again. */
10401 if (encoder->base.crtc) {
10402 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10403 encoder->base.base.id,
10404 drm_get_encoder_name(&encoder->base));
10405 encoder->disable(encoder);
10406 }
10407 encoder->base.crtc = NULL;
10408 encoder->connectors_active = false;
10409
10410 /* Inconsistent output/port/pipe state happens presumably due to
10411 * a bug in one of the get_hw_state functions. Or someplace else
10412 * in our code, like the register restore mess on resume. Clamp
10413 * things to off as a safer default. */
10414 list_for_each_entry(connector,
10415 &dev->mode_config.connector_list,
10416 base.head) {
10417 if (connector->encoder != encoder)
10418 continue;
10419 connector->base.dpms = DRM_MODE_DPMS_OFF;
10420 connector->base.encoder = NULL;
10421 }
10422 }
10423 /* Enabled encoders without active connectors will be fixed in
10424 * the crtc fixup. */
10425 }
10426
10427 void i915_redisable_vga(struct drm_device *dev)
10428 {
10429 struct drm_i915_private *dev_priv = dev->dev_private;
10430 u32 vga_reg = i915_vgacntrl_reg(dev);
10431
10432 /* This function can be called both from intel_modeset_setup_hw_state or
10433 * at a very early point in our resume sequence, where the power well
10434 * structures are not yet restored. Since this function is at a very
10435 * paranoid "someone might have enabled VGA while we were not looking"
10436 * level, just check if the power well is enabled instead of trying to
10437 * follow the "don't touch the power well if we don't need it" policy
10438 * the rest of the driver uses. */
10439 if (HAS_POWER_WELL(dev) &&
10440 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10441 return;
10442
10443 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10444 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10445 i915_disable_vga(dev);
10446 }
10447 }
10448
10449 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10450 {
10451 struct drm_i915_private *dev_priv = dev->dev_private;
10452 enum pipe pipe;
10453 struct intel_crtc *crtc;
10454 struct intel_encoder *encoder;
10455 struct intel_connector *connector;
10456 int i;
10457
10458 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10459 base.head) {
10460 memset(&crtc->config, 0, sizeof(crtc->config));
10461
10462 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
10463
10464 crtc->active = dev_priv->display.get_pipe_config(crtc,
10465 &crtc->config);
10466
10467 crtc->base.enabled = crtc->active;
10468
10469 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10470 crtc->base.base.id,
10471 crtc->active ? "enabled" : "disabled");
10472 }
10473
10474 /* FIXME: Smash this into the new shared dpll infrastructure. */
10475 if (HAS_DDI(dev))
10476 intel_ddi_setup_hw_pll_state(dev);
10477
10478 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10479 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10480
10481 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10482 pll->active = 0;
10483 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10484 base.head) {
10485 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10486 pll->active++;
10487 }
10488 pll->refcount = pll->active;
10489
10490 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10491 pll->name, pll->refcount, pll->on);
10492 }
10493
10494 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10495 base.head) {
10496 pipe = 0;
10497
10498 if (encoder->get_hw_state(encoder, &pipe)) {
10499 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10500 encoder->base.crtc = &crtc->base;
10501 if (encoder->get_config)
10502 encoder->get_config(encoder, &crtc->config);
10503 } else {
10504 encoder->base.crtc = NULL;
10505 }
10506
10507 encoder->connectors_active = false;
10508 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10509 encoder->base.base.id,
10510 drm_get_encoder_name(&encoder->base),
10511 encoder->base.crtc ? "enabled" : "disabled",
10512 pipe);
10513 }
10514
10515 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10516 base.head) {
10517 if (!crtc->active)
10518 continue;
10519 if (dev_priv->display.get_clock)
10520 dev_priv->display.get_clock(crtc,
10521 &crtc->config);
10522 }
10523
10524 list_for_each_entry(connector, &dev->mode_config.connector_list,
10525 base.head) {
10526 if (connector->get_hw_state(connector)) {
10527 connector->base.dpms = DRM_MODE_DPMS_ON;
10528 connector->encoder->connectors_active = true;
10529 connector->base.encoder = &connector->encoder->base;
10530 } else {
10531 connector->base.dpms = DRM_MODE_DPMS_OFF;
10532 connector->base.encoder = NULL;
10533 }
10534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10535 connector->base.base.id,
10536 drm_get_connector_name(&connector->base),
10537 connector->base.encoder ? "enabled" : "disabled");
10538 }
10539 }
10540
10541 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10542 * and i915 state tracking structures. */
10543 void intel_modeset_setup_hw_state(struct drm_device *dev,
10544 bool force_restore)
10545 {
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 enum pipe pipe;
10548 struct drm_plane *plane;
10549 struct intel_crtc *crtc;
10550 struct intel_encoder *encoder;
10551 int i;
10552
10553 intel_modeset_readout_hw_state(dev);
10554
10555 /*
10556 * Now that we have the config, copy it to each CRTC struct
10557 * Note that this could go away if we move to using crtc_config
10558 * checking everywhere.
10559 */
10560 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10561 base.head) {
10562 if (crtc->active && i915_fastboot) {
10563 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10564
10565 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10566 crtc->base.base.id);
10567 drm_mode_debug_printmodeline(&crtc->base.mode);
10568 }
10569 }
10570
10571 /* HW state is read out, now we need to sanitize this mess. */
10572 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10573 base.head) {
10574 intel_sanitize_encoder(encoder);
10575 }
10576
10577 for_each_pipe(pipe) {
10578 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10579 intel_sanitize_crtc(crtc);
10580 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10581 }
10582
10583 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10584 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10585
10586 if (!pll->on || pll->active)
10587 continue;
10588
10589 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10590
10591 pll->disable(dev_priv, pll);
10592 pll->on = false;
10593 }
10594
10595 if (force_restore) {
10596 /*
10597 * We need to use raw interfaces for restoring state to avoid
10598 * checking (bogus) intermediate states.
10599 */
10600 for_each_pipe(pipe) {
10601 struct drm_crtc *crtc =
10602 dev_priv->pipe_to_crtc_mapping[pipe];
10603
10604 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10605 crtc->fb);
10606 }
10607 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10608 intel_plane_restore(plane);
10609
10610 i915_redisable_vga(dev);
10611 } else {
10612 intel_modeset_update_staged_output_state(dev);
10613 }
10614
10615 intel_modeset_check_state(dev);
10616
10617 drm_mode_config_reset(dev);
10618 }
10619
10620 void intel_modeset_gem_init(struct drm_device *dev)
10621 {
10622 intel_modeset_init_hw(dev);
10623
10624 intel_setup_overlay(dev);
10625
10626 mutex_lock(&dev->mode_config.mutex);
10627 intel_modeset_setup_hw_state(dev, false);
10628 mutex_unlock(&dev->mode_config.mutex);
10629 }
10630
10631 void intel_modeset_cleanup(struct drm_device *dev)
10632 {
10633 struct drm_i915_private *dev_priv = dev->dev_private;
10634 struct drm_crtc *crtc;
10635
10636 /*
10637 * Interrupts and polling as the first thing to avoid creating havoc.
10638 * Too much stuff here (turning of rps, connectors, ...) would
10639 * experience fancy races otherwise.
10640 */
10641 drm_irq_uninstall(dev);
10642 cancel_work_sync(&dev_priv->hotplug_work);
10643 /*
10644 * Due to the hpd irq storm handling the hotplug work can re-arm the
10645 * poll handlers. Hence disable polling after hpd handling is shut down.
10646 */
10647 drm_kms_helper_poll_fini(dev);
10648
10649 mutex_lock(&dev->struct_mutex);
10650
10651 intel_unregister_dsm_handler();
10652
10653 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10654 /* Skip inactive CRTCs */
10655 if (!crtc->fb)
10656 continue;
10657
10658 intel_increase_pllclock(crtc);
10659 }
10660
10661 intel_disable_fbc(dev);
10662
10663 intel_disable_gt_powersave(dev);
10664
10665 ironlake_teardown_rc6(dev);
10666
10667 mutex_unlock(&dev->struct_mutex);
10668
10669 /* flush any delayed tasks or pending work */
10670 flush_scheduled_work();
10671
10672 /* destroy backlight, if any, before the connectors */
10673 intel_panel_destroy_backlight(dev);
10674
10675 drm_mode_config_cleanup(dev);
10676
10677 intel_cleanup_overlay(dev);
10678 }
10679
10680 /*
10681 * Return which encoder is currently attached for connector.
10682 */
10683 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10684 {
10685 return &intel_attached_encoder(connector)->base;
10686 }
10687
10688 void intel_connector_attach_encoder(struct intel_connector *connector,
10689 struct intel_encoder *encoder)
10690 {
10691 connector->encoder = encoder;
10692 drm_mode_connector_attach_encoder(&connector->base,
10693 &encoder->base);
10694 }
10695
10696 /*
10697 * set vga decode state - true == enable VGA decode
10698 */
10699 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10700 {
10701 struct drm_i915_private *dev_priv = dev->dev_private;
10702 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
10703 u16 gmch_ctrl;
10704
10705 pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
10706 if (state)
10707 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10708 else
10709 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10710 pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
10711 return 0;
10712 }
10713
10714 struct intel_display_error_state {
10715
10716 u32 power_well_driver;
10717
10718 int num_transcoders;
10719
10720 struct intel_cursor_error_state {
10721 u32 control;
10722 u32 position;
10723 u32 base;
10724 u32 size;
10725 } cursor[I915_MAX_PIPES];
10726
10727 struct intel_pipe_error_state {
10728 u32 source;
10729 } pipe[I915_MAX_PIPES];
10730
10731 struct intel_plane_error_state {
10732 u32 control;
10733 u32 stride;
10734 u32 size;
10735 u32 pos;
10736 u32 addr;
10737 u32 surface;
10738 u32 tile_offset;
10739 } plane[I915_MAX_PIPES];
10740
10741 struct intel_transcoder_error_state {
10742 enum transcoder cpu_transcoder;
10743
10744 u32 conf;
10745
10746 u32 htotal;
10747 u32 hblank;
10748 u32 hsync;
10749 u32 vtotal;
10750 u32 vblank;
10751 u32 vsync;
10752 } transcoder[4];
10753 };
10754
10755 struct intel_display_error_state *
10756 intel_display_capture_error_state(struct drm_device *dev)
10757 {
10758 drm_i915_private_t *dev_priv = dev->dev_private;
10759 struct intel_display_error_state *error;
10760 int transcoders[] = {
10761 TRANSCODER_A,
10762 TRANSCODER_B,
10763 TRANSCODER_C,
10764 TRANSCODER_EDP,
10765 };
10766 int i;
10767
10768 if (INTEL_INFO(dev)->num_pipes == 0)
10769 return NULL;
10770
10771 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10772 if (error == NULL)
10773 return NULL;
10774
10775 if (HAS_POWER_WELL(dev))
10776 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10777
10778 for_each_pipe(i) {
10779 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10780 error->cursor[i].control = I915_READ(CURCNTR(i));
10781 error->cursor[i].position = I915_READ(CURPOS(i));
10782 error->cursor[i].base = I915_READ(CURBASE(i));
10783 } else {
10784 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10785 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10786 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10787 }
10788
10789 error->plane[i].control = I915_READ(DSPCNTR(i));
10790 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10791 if (INTEL_INFO(dev)->gen <= 3) {
10792 error->plane[i].size = I915_READ(DSPSIZE(i));
10793 error->plane[i].pos = I915_READ(DSPPOS(i));
10794 }
10795 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10796 error->plane[i].addr = I915_READ(DSPADDR(i));
10797 if (INTEL_INFO(dev)->gen >= 4) {
10798 error->plane[i].surface = I915_READ(DSPSURF(i));
10799 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10800 }
10801
10802 error->pipe[i].source = I915_READ(PIPESRC(i));
10803 }
10804
10805 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10806 if (HAS_DDI(dev_priv->dev))
10807 error->num_transcoders++; /* Account for eDP. */
10808
10809 for (i = 0; i < error->num_transcoders; i++) {
10810 enum transcoder cpu_transcoder = transcoders[i];
10811
10812 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10813
10814 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10815 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10816 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10817 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10818 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10819 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10820 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10821 }
10822
10823 /* In the code above we read the registers without checking if the power
10824 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10825 * prevent the next I915_WRITE from detecting it and printing an error
10826 * message. */
10827 intel_uncore_clear_errors(dev);
10828
10829 return error;
10830 }
10831
10832 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10833
10834 void
10835 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10836 struct drm_device *dev,
10837 struct intel_display_error_state *error)
10838 {
10839 int i;
10840
10841 if (!error)
10842 return;
10843
10844 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10845 if (HAS_POWER_WELL(dev))
10846 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10847 error->power_well_driver);
10848 for_each_pipe(i) {
10849 err_printf(m, "Pipe [%d]:\n", i);
10850 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10851
10852 err_printf(m, "Plane [%d]:\n", i);
10853 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10854 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10855 if (INTEL_INFO(dev)->gen <= 3) {
10856 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10857 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10858 }
10859 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10860 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10861 if (INTEL_INFO(dev)->gen >= 4) {
10862 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10863 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10864 }
10865
10866 err_printf(m, "Cursor [%d]:\n", i);
10867 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10868 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10869 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10870 }
10871
10872 for (i = 0; i < error->num_transcoders; i++) {
10873 err_printf(m, " CPU transcoder: %c\n",
10874 transcoder_name(error->transcoder[i].cpu_transcoder));
10875 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10876 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10877 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10878 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10879 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10880 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10881 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10882 }
10883 }
Linux with added FPC-III support