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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_dp.c
blobb0191f25cd55d01aa0e49e9f698d2397757924af
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56 {
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60 }
61
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63 {
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
65 }
66
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
68
69 static int
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
71 {
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
81 default:
82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88 }
89
90 /*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
107 static int
108 intel_dp_link_required(int pixel_clock, int bpp)
109 {
110 return (pixel_clock * bpp + 9) / 10;
111 }
112
113 static int
114 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115 {
116 return (max_link_clock * max_lanes * 8) / 10;
117 }
118
119 static int
120 intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122 {
123 struct intel_dp *intel_dp = intel_attached_dp(connector);
124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
128
129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
131 return MODE_PANEL;
132
133 if (mode->vdisplay > fixed_mode->vdisplay)
134 return MODE_PANEL;
135
136 target_clock = fixed_mode->clock;
137 }
138
139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
146 return MODE_CLOCK_HIGH;
147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
154 return MODE_OK;
155 }
156
157 static uint32_t
158 pack_aux(uint8_t *src, int src_bytes)
159 {
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168 }
169
170 static void
171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172 {
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178 }
179
180 /* hrawclock is 1/4 the FSB frequency */
181 static int
182 intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215 {
216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 u32 pp_stat_reg;
219
220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
222 }
223
224 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225 {
226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 pp_ctrl_reg;
229
230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
232 }
233
234 static void
235 intel_dp_check_edp(struct intel_dp *intel_dp)
236 {
237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 pp_stat_reg, pp_ctrl_reg;
240
241 if (!is_edp(intel_dp))
242 return;
243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
252 }
253 }
254
255 static uint32_t
256 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257 {
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
262 uint32_t status;
263 bool done;
264
265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
266 if (has_aux_irq)
267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
268 msecs_to_jiffies_timeout(10));
269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274 #undef C
275
276 return status;
277 }
278
279 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
280 int index)
281 {
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 /* The clock divider is based off the hrawclk,
287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
289 *
290 * Note that PCH attached eDP panels should use a 125MHz input
291 * clock divider.
292 */
293 if (IS_VALLEYVIEW(dev)) {
294 return index ? 0 : 100;
295 } else if (intel_dig_port->port == PORT_A) {
296 if (index)
297 return 0;
298 if (HAS_DDI(dev))
299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
300 else if (IS_GEN6(dev) || IS_GEN7(dev))
301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
302 else
303 return 225; /* eDP input clock at 450Mhz */
304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
306 switch (index) {
307 case 0: return 63;
308 case 1: return 72;
309 default: return 0;
310 }
311 } else if (HAS_PCH_SPLIT(dev)) {
312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
313 } else {
314 return index ? 0 :intel_hrawclk(dev) / 2;
315 }
316 }
317
318 static int
319 intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
322 {
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
328 uint32_t aux_clock_divider;
329 int i, ret, recv_bytes;
330 uint32_t status;
331 int try, precharge, clock = 0;
332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
333
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
336 * deep sleep states.
337 */
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
339
340 intel_dp_check_edp(intel_dp);
341
342 if (IS_GEN6(dev))
343 precharge = 3;
344 else
345 precharge = 5;
346
347 intel_aux_display_runtime_get(dev_priv);
348
349 /* Try to wait for any previous AUX channel activity */
350 for (try = 0; try < 3; try++) {
351 status = I915_READ_NOTRACE(ch_ctl);
352 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
353 break;
354 msleep(1);
355 }
356
357 if (try == 3) {
358 WARN(1, "dp_aux_ch not started status 0x%08x\n",
359 I915_READ(ch_ctl));
360 ret = -EBUSY;
361 goto out;
362 }
363
364 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
365 /* Must try at least 3 times according to DP spec */
366 for (try = 0; try < 5; try++) {
367 /* Load the send data into the aux channel data registers */
368 for (i = 0; i < send_bytes; i += 4)
369 I915_WRITE(ch_data + i,
370 pack_aux(send + i, send_bytes - i));
371
372 /* Send the command and wait for it to complete */
373 I915_WRITE(ch_ctl,
374 DP_AUX_CH_CTL_SEND_BUSY |
375 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
376 DP_AUX_CH_CTL_TIME_OUT_400us |
377 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
378 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
379 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
380 DP_AUX_CH_CTL_DONE |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
383
384 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
385
386 /* Clear done status and any errors */
387 I915_WRITE(ch_ctl,
388 status |
389 DP_AUX_CH_CTL_DONE |
390 DP_AUX_CH_CTL_TIME_OUT_ERROR |
391 DP_AUX_CH_CTL_RECEIVE_ERROR);
392
393 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
394 DP_AUX_CH_CTL_RECEIVE_ERROR))
395 continue;
396 if (status & DP_AUX_CH_CTL_DONE)
397 break;
398 }
399 if (status & DP_AUX_CH_CTL_DONE)
400 break;
401 }
402
403 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
404 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
405 ret = -EBUSY;
406 goto out;
407 }
408
409 /* Check for timeout or receive error.
410 * Timeouts occur when the sink is not connected
411 */
412 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
413 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
414 ret = -EIO;
415 goto out;
416 }
417
418 /* Timeouts occur when the device isn't connected, so they're
419 * "normal" -- don't fill the kernel log with these */
420 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
421 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
422 ret = -ETIMEDOUT;
423 goto out;
424 }
425
426 /* Unload any bytes sent back from the other side */
427 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
428 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
429 if (recv_bytes > recv_size)
430 recv_bytes = recv_size;
431
432 for (i = 0; i < recv_bytes; i += 4)
433 unpack_aux(I915_READ(ch_data + i),
434 recv + i, recv_bytes - i);
435
436 ret = recv_bytes;
437 out:
438 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
439 intel_aux_display_runtime_put(dev_priv);
440
441 return ret;
442 }
443
444 /* Write data to the aux channel in native mode */
445 static int
446 intel_dp_aux_native_write(struct intel_dp *intel_dp,
447 uint16_t address, uint8_t *send, int send_bytes)
448 {
449 int ret;
450 uint8_t msg[20];
451 int msg_bytes;
452 uint8_t ack;
453 int retry;
454
455 intel_dp_check_edp(intel_dp);
456 if (send_bytes > 16)
457 return -1;
458 msg[0] = AUX_NATIVE_WRITE << 4;
459 msg[1] = address >> 8;
460 msg[2] = address & 0xff;
461 msg[3] = send_bytes - 1;
462 memcpy(&msg[4], send, send_bytes);
463 msg_bytes = send_bytes + 4;
464 for (retry = 0; retry < 7; retry++) {
465 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
466 if (ret < 0)
467 return ret;
468 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
469 return send_bytes;
470 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
471 usleep_range(400, 500);
472 else
473 return -EIO;
474 }
475
476 DRM_ERROR("too many retries, giving up\n");
477 return -EIO;
478 }
479
480 /* Write a single byte to the aux channel in native mode */
481 static int
482 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
483 uint16_t address, uint8_t byte)
484 {
485 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
486 }
487
488 /* read bytes from a native aux channel */
489 static int
490 intel_dp_aux_native_read(struct intel_dp *intel_dp,
491 uint16_t address, uint8_t *recv, int recv_bytes)
492 {
493 uint8_t msg[4];
494 int msg_bytes;
495 uint8_t reply[20];
496 int reply_bytes;
497 uint8_t ack;
498 int ret;
499 int retry;
500
501 intel_dp_check_edp(intel_dp);
502 msg[0] = AUX_NATIVE_READ << 4;
503 msg[1] = address >> 8;
504 msg[2] = address & 0xff;
505 msg[3] = recv_bytes - 1;
506
507 msg_bytes = 4;
508 reply_bytes = recv_bytes + 1;
509
510 for (retry = 0; retry < 7; retry++) {
511 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
512 reply, reply_bytes);
513 if (ret == 0)
514 return -EPROTO;
515 if (ret < 0)
516 return ret;
517 ack = reply[0];
518 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
519 memcpy(recv, reply + 1, ret - 1);
520 return ret - 1;
521 }
522 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
523 usleep_range(400, 500);
524 else
525 return -EIO;
526 }
527
528 DRM_ERROR("too many retries, giving up\n");
529 return -EIO;
530 }
531
532 static int
533 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
534 uint8_t write_byte, uint8_t *read_byte)
535 {
536 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
537 struct intel_dp *intel_dp = container_of(adapter,
538 struct intel_dp,
539 adapter);
540 uint16_t address = algo_data->address;
541 uint8_t msg[5];
542 uint8_t reply[2];
543 unsigned retry;
544 int msg_bytes;
545 int reply_bytes;
546 int ret;
547
548 intel_dp_check_edp(intel_dp);
549 /* Set up the command byte */
550 if (mode & MODE_I2C_READ)
551 msg[0] = AUX_I2C_READ << 4;
552 else
553 msg[0] = AUX_I2C_WRITE << 4;
554
555 if (!(mode & MODE_I2C_STOP))
556 msg[0] |= AUX_I2C_MOT << 4;
557
558 msg[1] = address >> 8;
559 msg[2] = address;
560
561 switch (mode) {
562 case MODE_I2C_WRITE:
563 msg[3] = 0;
564 msg[4] = write_byte;
565 msg_bytes = 5;
566 reply_bytes = 1;
567 break;
568 case MODE_I2C_READ:
569 msg[3] = 0;
570 msg_bytes = 4;
571 reply_bytes = 2;
572 break;
573 default:
574 msg_bytes = 3;
575 reply_bytes = 1;
576 break;
577 }
578
579 for (retry = 0; retry < 5; retry++) {
580 ret = intel_dp_aux_ch(intel_dp,
581 msg, msg_bytes,
582 reply, reply_bytes);
583 if (ret < 0) {
584 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
585 return ret;
586 }
587
588 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
589 case AUX_NATIVE_REPLY_ACK:
590 /* I2C-over-AUX Reply field is only valid
591 * when paired with AUX ACK.
592 */
593 break;
594 case AUX_NATIVE_REPLY_NACK:
595 DRM_DEBUG_KMS("aux_ch native nack\n");
596 return -EREMOTEIO;
597 case AUX_NATIVE_REPLY_DEFER:
598 /*
599 * For now, just give more slack to branch devices. We
600 * could check the DPCD for I2C bit rate capabilities,
601 * and if available, adjust the interval. We could also
602 * be more careful with DP-to-Legacy adapters where a
603 * long legacy cable may force very low I2C bit rates.
604 */
605 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
606 DP_DWN_STRM_PORT_PRESENT)
607 usleep_range(500, 600);
608 else
609 usleep_range(300, 400);
610 continue;
611 default:
612 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
613 reply[0]);
614 return -EREMOTEIO;
615 }
616
617 switch (reply[0] & AUX_I2C_REPLY_MASK) {
618 case AUX_I2C_REPLY_ACK:
619 if (mode == MODE_I2C_READ) {
620 *read_byte = reply[1];
621 }
622 return reply_bytes - 1;
623 case AUX_I2C_REPLY_NACK:
624 DRM_DEBUG_KMS("aux_i2c nack\n");
625 return -EREMOTEIO;
626 case AUX_I2C_REPLY_DEFER:
627 DRM_DEBUG_KMS("aux_i2c defer\n");
628 udelay(100);
629 break;
630 default:
631 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
632 return -EREMOTEIO;
633 }
634 }
635
636 DRM_ERROR("too many retries, giving up\n");
637 return -EREMOTEIO;
638 }
639
640 static int
641 intel_dp_i2c_init(struct intel_dp *intel_dp,
642 struct intel_connector *intel_connector, const char *name)
643 {
644 int ret;
645
646 DRM_DEBUG_KMS("i2c_init %s\n", name);
647 intel_dp->algo.running = false;
648 intel_dp->algo.address = 0;
649 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
650
651 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
652 intel_dp->adapter.owner = THIS_MODULE;
653 intel_dp->adapter.class = I2C_CLASS_DDC;
654 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
655 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
656 intel_dp->adapter.algo_data = &intel_dp->algo;
657 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
658
659 ironlake_edp_panel_vdd_on(intel_dp);
660 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
661 ironlake_edp_panel_vdd_off(intel_dp, false);
662 return ret;
663 }
664
665 static void
666 intel_dp_set_clock(struct intel_encoder *encoder,
667 struct intel_crtc_config *pipe_config, int link_bw)
668 {
669 struct drm_device *dev = encoder->base.dev;
670
671 if (IS_G4X(dev)) {
672 if (link_bw == DP_LINK_BW_1_62) {
673 pipe_config->dpll.p1 = 2;
674 pipe_config->dpll.p2 = 10;
675 pipe_config->dpll.n = 2;
676 pipe_config->dpll.m1 = 23;
677 pipe_config->dpll.m2 = 8;
678 } else {
679 pipe_config->dpll.p1 = 1;
680 pipe_config->dpll.p2 = 10;
681 pipe_config->dpll.n = 1;
682 pipe_config->dpll.m1 = 14;
683 pipe_config->dpll.m2 = 2;
684 }
685 pipe_config->clock_set = true;
686 } else if (IS_HASWELL(dev)) {
687 /* Haswell has special-purpose DP DDI clocks. */
688 } else if (HAS_PCH_SPLIT(dev)) {
689 if (link_bw == DP_LINK_BW_1_62) {
690 pipe_config->dpll.n = 1;
691 pipe_config->dpll.p1 = 2;
692 pipe_config->dpll.p2 = 10;
693 pipe_config->dpll.m1 = 12;
694 pipe_config->dpll.m2 = 9;
695 } else {
696 pipe_config->dpll.n = 2;
697 pipe_config->dpll.p1 = 1;
698 pipe_config->dpll.p2 = 10;
699 pipe_config->dpll.m1 = 14;
700 pipe_config->dpll.m2 = 8;
701 }
702 pipe_config->clock_set = true;
703 } else if (IS_VALLEYVIEW(dev)) {
704 /* FIXME: Need to figure out optimized DP clocks for vlv. */
705 }
706 }
707
708 bool
709 intel_dp_compute_config(struct intel_encoder *encoder,
710 struct intel_crtc_config *pipe_config)
711 {
712 struct drm_device *dev = encoder->base.dev;
713 struct drm_i915_private *dev_priv = dev->dev_private;
714 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
715 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
716 enum port port = dp_to_dig_port(intel_dp)->port;
717 struct intel_crtc *intel_crtc = encoder->new_crtc;
718 struct intel_connector *intel_connector = intel_dp->attached_connector;
719 int lane_count, clock;
720 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
721 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
722 int bpp, mode_rate;
723 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
724 int link_avail, link_clock;
725
726 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
727 pipe_config->has_pch_encoder = true;
728
729 pipe_config->has_dp_encoder = true;
730
731 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
732 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
733 adjusted_mode);
734 if (!HAS_PCH_SPLIT(dev))
735 intel_gmch_panel_fitting(intel_crtc, pipe_config,
736 intel_connector->panel.fitting_mode);
737 else
738 intel_pch_panel_fitting(intel_crtc, pipe_config,
739 intel_connector->panel.fitting_mode);
740 }
741
742 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
743 return false;
744
745 DRM_DEBUG_KMS("DP link computation with max lane count %i "
746 "max bw %02x pixel clock %iKHz\n",
747 max_lane_count, bws[max_clock], adjusted_mode->clock);
748
749 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
750 * bpc in between. */
751 bpp = pipe_config->pipe_bpp;
752 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
753 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
754 dev_priv->vbt.edp_bpp);
755 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
756 }
757
758 for (; bpp >= 6*3; bpp -= 2*3) {
759 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
760
761 for (clock = 0; clock <= max_clock; clock++) {
762 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
763 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
764 link_avail = intel_dp_max_data_rate(link_clock,
765 lane_count);
766
767 if (mode_rate <= link_avail) {
768 goto found;
769 }
770 }
771 }
772 }
773
774 return false;
775
776 found:
777 if (intel_dp->color_range_auto) {
778 /*
779 * See:
780 * CEA-861-E - 5.1 Default Encoding Parameters
781 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
782 */
783 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
784 intel_dp->color_range = DP_COLOR_RANGE_16_235;
785 else
786 intel_dp->color_range = 0;
787 }
788
789 if (intel_dp->color_range)
790 pipe_config->limited_color_range = true;
791
792 intel_dp->link_bw = bws[clock];
793 intel_dp->lane_count = lane_count;
794 pipe_config->pipe_bpp = bpp;
795 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
796
797 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
798 intel_dp->link_bw, intel_dp->lane_count,
799 pipe_config->port_clock, bpp);
800 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
801 mode_rate, link_avail);
802
803 intel_link_compute_m_n(bpp, lane_count,
804 adjusted_mode->clock, pipe_config->port_clock,
805 &pipe_config->dp_m_n);
806
807 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
808
809 return true;
810 }
811
812 void intel_dp_init_link_config(struct intel_dp *intel_dp)
813 {
814 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
815 intel_dp->link_configuration[0] = intel_dp->link_bw;
816 intel_dp->link_configuration[1] = intel_dp->lane_count;
817 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
818 /*
819 * Check for DPCD version > 1.1 and enhanced framing support
820 */
821 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
822 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
823 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
824 }
825 }
826
827 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
828 {
829 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
830 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 u32 dpa_ctl;
834
835 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
836 dpa_ctl = I915_READ(DP_A);
837 dpa_ctl &= ~DP_PLL_FREQ_MASK;
838
839 if (crtc->config.port_clock == 162000) {
840 /* For a long time we've carried around a ILK-DevA w/a for the
841 * 160MHz clock. If we're really unlucky, it's still required.
842 */
843 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
844 dpa_ctl |= DP_PLL_FREQ_160MHZ;
845 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
846 } else {
847 dpa_ctl |= DP_PLL_FREQ_270MHZ;
848 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
849 }
850
851 I915_WRITE(DP_A, dpa_ctl);
852
853 POSTING_READ(DP_A);
854 udelay(500);
855 }
856
857 static void intel_dp_mode_set(struct intel_encoder *encoder)
858 {
859 struct drm_device *dev = encoder->base.dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
862 enum port port = dp_to_dig_port(intel_dp)->port;
863 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
864 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
865
866 /*
867 * There are four kinds of DP registers:
868 *
869 * IBX PCH
870 * SNB CPU
871 * IVB CPU
872 * CPT PCH
873 *
874 * IBX PCH and CPU are the same for almost everything,
875 * except that the CPU DP PLL is configured in this
876 * register
877 *
878 * CPT PCH is quite different, having many bits moved
879 * to the TRANS_DP_CTL register instead. That
880 * configuration happens (oddly) in ironlake_pch_enable
881 */
882
883 /* Preserve the BIOS-computed detected bit. This is
884 * supposed to be read-only.
885 */
886 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
887
888 /* Handle DP bits in common between all three register formats */
889 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
890 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
891
892 if (intel_dp->has_audio) {
893 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
894 pipe_name(crtc->pipe));
895 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
896 intel_write_eld(&encoder->base, adjusted_mode);
897 }
898
899 intel_dp_init_link_config(intel_dp);
900
901 /* Split out the IBX/CPU vs CPT settings */
902
903 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
904 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
905 intel_dp->DP |= DP_SYNC_HS_HIGH;
906 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
907 intel_dp->DP |= DP_SYNC_VS_HIGH;
908 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
909
910 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
911 intel_dp->DP |= DP_ENHANCED_FRAMING;
912
913 intel_dp->DP |= crtc->pipe << 29;
914 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
915 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
916 intel_dp->DP |= intel_dp->color_range;
917
918 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
919 intel_dp->DP |= DP_SYNC_HS_HIGH;
920 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
921 intel_dp->DP |= DP_SYNC_VS_HIGH;
922 intel_dp->DP |= DP_LINK_TRAIN_OFF;
923
924 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
925 intel_dp->DP |= DP_ENHANCED_FRAMING;
926
927 if (crtc->pipe == 1)
928 intel_dp->DP |= DP_PIPEB_SELECT;
929 } else {
930 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
931 }
932
933 if (port == PORT_A && !IS_VALLEYVIEW(dev))
934 ironlake_set_pll_cpu_edp(intel_dp);
935 }
936
937 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
938 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
939
940 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
941 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
942
943 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
944 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
945
946 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
947 u32 mask,
948 u32 value)
949 {
950 struct drm_device *dev = intel_dp_to_dev(intel_dp);
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 pp_stat_reg, pp_ctrl_reg;
953
954 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
955 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
956
957 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
958 mask, value,
959 I915_READ(pp_stat_reg),
960 I915_READ(pp_ctrl_reg));
961
962 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
963 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
964 I915_READ(pp_stat_reg),
965 I915_READ(pp_ctrl_reg));
966 }
967 }
968
969 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
970 {
971 DRM_DEBUG_KMS("Wait for panel power on\n");
972 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
973 }
974
975 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
976 {
977 DRM_DEBUG_KMS("Wait for panel power off time\n");
978 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
979 }
980
981 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
982 {
983 DRM_DEBUG_KMS("Wait for panel power cycle\n");
984 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
985 }
986
987
988 /* Read the current pp_control value, unlocking the register if it
989 * is locked
990 */
991
992 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
993 {
994 struct drm_device *dev = intel_dp_to_dev(intel_dp);
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 u32 control;
997 u32 pp_ctrl_reg;
998
999 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1000 control = I915_READ(pp_ctrl_reg);
1001
1002 control &= ~PANEL_UNLOCK_MASK;
1003 control |= PANEL_UNLOCK_REGS;
1004 return control;
1005 }
1006
1007 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1008 {
1009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 pp;
1012 u32 pp_stat_reg, pp_ctrl_reg;
1013
1014 if (!is_edp(intel_dp))
1015 return;
1016 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1017
1018 WARN(intel_dp->want_panel_vdd,
1019 "eDP VDD already requested on\n");
1020
1021 intel_dp->want_panel_vdd = true;
1022
1023 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1024 DRM_DEBUG_KMS("eDP VDD already on\n");
1025 return;
1026 }
1027
1028 if (!ironlake_edp_have_panel_power(intel_dp))
1029 ironlake_wait_panel_power_cycle(intel_dp);
1030
1031 pp = ironlake_get_pp_control(intel_dp);
1032 pp |= EDP_FORCE_VDD;
1033
1034 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1035 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1036
1037 I915_WRITE(pp_ctrl_reg, pp);
1038 POSTING_READ(pp_ctrl_reg);
1039 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1040 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1041 /*
1042 * If the panel wasn't on, delay before accessing aux channel
1043 */
1044 if (!ironlake_edp_have_panel_power(intel_dp)) {
1045 DRM_DEBUG_KMS("eDP was not running\n");
1046 msleep(intel_dp->panel_power_up_delay);
1047 }
1048 }
1049
1050 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1051 {
1052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 u32 pp;
1055 u32 pp_stat_reg, pp_ctrl_reg;
1056
1057 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1058
1059 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1060 pp = ironlake_get_pp_control(intel_dp);
1061 pp &= ~EDP_FORCE_VDD;
1062
1063 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1064 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1065
1066 I915_WRITE(pp_ctrl_reg, pp);
1067 POSTING_READ(pp_ctrl_reg);
1068
1069 /* Make sure sequencer is idle before allowing subsequent activity */
1070 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1071 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1072 msleep(intel_dp->panel_power_down_delay);
1073 }
1074 }
1075
1076 static void ironlake_panel_vdd_work(struct work_struct *__work)
1077 {
1078 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1079 struct intel_dp, panel_vdd_work);
1080 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1081
1082 mutex_lock(&dev->mode_config.mutex);
1083 ironlake_panel_vdd_off_sync(intel_dp);
1084 mutex_unlock(&dev->mode_config.mutex);
1085 }
1086
1087 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1088 {
1089 if (!is_edp(intel_dp))
1090 return;
1091
1092 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1093 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1094
1095 intel_dp->want_panel_vdd = false;
1096
1097 if (sync) {
1098 ironlake_panel_vdd_off_sync(intel_dp);
1099 } else {
1100 /*
1101 * Queue the timer to fire a long
1102 * time from now (relative to the power down delay)
1103 * to keep the panel power up across a sequence of operations
1104 */
1105 schedule_delayed_work(&intel_dp->panel_vdd_work,
1106 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1107 }
1108 }
1109
1110 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1111 {
1112 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 u32 pp;
1115 u32 pp_ctrl_reg;
1116
1117 if (!is_edp(intel_dp))
1118 return;
1119
1120 DRM_DEBUG_KMS("Turn eDP power on\n");
1121
1122 if (ironlake_edp_have_panel_power(intel_dp)) {
1123 DRM_DEBUG_KMS("eDP power already on\n");
1124 return;
1125 }
1126
1127 ironlake_wait_panel_power_cycle(intel_dp);
1128
1129 pp = ironlake_get_pp_control(intel_dp);
1130 if (IS_GEN5(dev)) {
1131 /* ILK workaround: disable reset around power sequence */
1132 pp &= ~PANEL_POWER_RESET;
1133 I915_WRITE(PCH_PP_CONTROL, pp);
1134 POSTING_READ(PCH_PP_CONTROL);
1135 }
1136
1137 pp |= POWER_TARGET_ON;
1138 if (!IS_GEN5(dev))
1139 pp |= PANEL_POWER_RESET;
1140
1141 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1142
1143 I915_WRITE(pp_ctrl_reg, pp);
1144 POSTING_READ(pp_ctrl_reg);
1145
1146 ironlake_wait_panel_on(intel_dp);
1147
1148 if (IS_GEN5(dev)) {
1149 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1150 I915_WRITE(PCH_PP_CONTROL, pp);
1151 POSTING_READ(PCH_PP_CONTROL);
1152 }
1153 }
1154
1155 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1156 {
1157 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1159 u32 pp;
1160 u32 pp_ctrl_reg;
1161
1162 if (!is_edp(intel_dp))
1163 return;
1164
1165 DRM_DEBUG_KMS("Turn eDP power off\n");
1166
1167 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1168
1169 pp = ironlake_get_pp_control(intel_dp);
1170 /* We need to switch off panel power _and_ force vdd, for otherwise some
1171 * panels get very unhappy and cease to work. */
1172 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1173
1174 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1175
1176 I915_WRITE(pp_ctrl_reg, pp);
1177 POSTING_READ(pp_ctrl_reg);
1178
1179 intel_dp->want_panel_vdd = false;
1180
1181 ironlake_wait_panel_off(intel_dp);
1182 }
1183
1184 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1185 {
1186 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1187 struct drm_device *dev = intel_dig_port->base.base.dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1190 u32 pp;
1191 u32 pp_ctrl_reg;
1192
1193 if (!is_edp(intel_dp))
1194 return;
1195
1196 DRM_DEBUG_KMS("\n");
1197 /*
1198 * If we enable the backlight right away following a panel power
1199 * on, we may see slight flicker as the panel syncs with the eDP
1200 * link. So delay a bit to make sure the image is solid before
1201 * allowing it to appear.
1202 */
1203 msleep(intel_dp->backlight_on_delay);
1204 pp = ironlake_get_pp_control(intel_dp);
1205 pp |= EDP_BLC_ENABLE;
1206
1207 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1208
1209 I915_WRITE(pp_ctrl_reg, pp);
1210 POSTING_READ(pp_ctrl_reg);
1211
1212 intel_panel_enable_backlight(dev, pipe);
1213 }
1214
1215 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1216 {
1217 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 u32 pp;
1220 u32 pp_ctrl_reg;
1221
1222 if (!is_edp(intel_dp))
1223 return;
1224
1225 intel_panel_disable_backlight(dev);
1226
1227 DRM_DEBUG_KMS("\n");
1228 pp = ironlake_get_pp_control(intel_dp);
1229 pp &= ~EDP_BLC_ENABLE;
1230
1231 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1232
1233 I915_WRITE(pp_ctrl_reg, pp);
1234 POSTING_READ(pp_ctrl_reg);
1235 msleep(intel_dp->backlight_off_delay);
1236 }
1237
1238 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1239 {
1240 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1241 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1242 struct drm_device *dev = crtc->dev;
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 u32 dpa_ctl;
1245
1246 assert_pipe_disabled(dev_priv,
1247 to_intel_crtc(crtc)->pipe);
1248
1249 DRM_DEBUG_KMS("\n");
1250 dpa_ctl = I915_READ(DP_A);
1251 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1252 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1253
1254 /* We don't adjust intel_dp->DP while tearing down the link, to
1255 * facilitate link retraining (e.g. after hotplug). Hence clear all
1256 * enable bits here to ensure that we don't enable too much. */
1257 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1258 intel_dp->DP |= DP_PLL_ENABLE;
1259 I915_WRITE(DP_A, intel_dp->DP);
1260 POSTING_READ(DP_A);
1261 udelay(200);
1262 }
1263
1264 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1265 {
1266 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1267 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1268 struct drm_device *dev = crtc->dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 u32 dpa_ctl;
1271
1272 assert_pipe_disabled(dev_priv,
1273 to_intel_crtc(crtc)->pipe);
1274
1275 dpa_ctl = I915_READ(DP_A);
1276 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1277 "dp pll off, should be on\n");
1278 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1279
1280 /* We can't rely on the value tracked for the DP register in
1281 * intel_dp->DP because link_down must not change that (otherwise link
1282 * re-training will fail. */
1283 dpa_ctl &= ~DP_PLL_ENABLE;
1284 I915_WRITE(DP_A, dpa_ctl);
1285 POSTING_READ(DP_A);
1286 udelay(200);
1287 }
1288
1289 /* If the sink supports it, try to set the power state appropriately */
1290 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1291 {
1292 int ret, i;
1293
1294 /* Should have a valid DPCD by this point */
1295 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1296 return;
1297
1298 if (mode != DRM_MODE_DPMS_ON) {
1299 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1300 DP_SET_POWER_D3);
1301 if (ret != 1)
1302 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1303 } else {
1304 /*
1305 * When turning on, we need to retry for 1ms to give the sink
1306 * time to wake up.
1307 */
1308 for (i = 0; i < 3; i++) {
1309 ret = intel_dp_aux_native_write_1(intel_dp,
1310 DP_SET_POWER,
1311 DP_SET_POWER_D0);
1312 if (ret == 1)
1313 break;
1314 msleep(1);
1315 }
1316 }
1317 }
1318
1319 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1320 enum pipe *pipe)
1321 {
1322 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1323 enum port port = dp_to_dig_port(intel_dp)->port;
1324 struct drm_device *dev = encoder->base.dev;
1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 u32 tmp = I915_READ(intel_dp->output_reg);
1327
1328 if (!(tmp & DP_PORT_EN))
1329 return false;
1330
1331 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1332 *pipe = PORT_TO_PIPE_CPT(tmp);
1333 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1334 *pipe = PORT_TO_PIPE(tmp);
1335 } else {
1336 u32 trans_sel;
1337 u32 trans_dp;
1338 int i;
1339
1340 switch (intel_dp->output_reg) {
1341 case PCH_DP_B:
1342 trans_sel = TRANS_DP_PORT_SEL_B;
1343 break;
1344 case PCH_DP_C:
1345 trans_sel = TRANS_DP_PORT_SEL_C;
1346 break;
1347 case PCH_DP_D:
1348 trans_sel = TRANS_DP_PORT_SEL_D;
1349 break;
1350 default:
1351 return true;
1352 }
1353
1354 for_each_pipe(i) {
1355 trans_dp = I915_READ(TRANS_DP_CTL(i));
1356 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1357 *pipe = i;
1358 return true;
1359 }
1360 }
1361
1362 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1363 intel_dp->output_reg);
1364 }
1365
1366 return true;
1367 }
1368
1369 static void intel_dp_get_config(struct intel_encoder *encoder,
1370 struct intel_crtc_config *pipe_config)
1371 {
1372 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1373 u32 tmp, flags = 0;
1374 struct drm_device *dev = encoder->base.dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 enum port port = dp_to_dig_port(intel_dp)->port;
1377 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1378
1379 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1380 tmp = I915_READ(intel_dp->output_reg);
1381 if (tmp & DP_SYNC_HS_HIGH)
1382 flags |= DRM_MODE_FLAG_PHSYNC;
1383 else
1384 flags |= DRM_MODE_FLAG_NHSYNC;
1385
1386 if (tmp & DP_SYNC_VS_HIGH)
1387 flags |= DRM_MODE_FLAG_PVSYNC;
1388 else
1389 flags |= DRM_MODE_FLAG_NVSYNC;
1390 } else {
1391 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1392 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1393 flags |= DRM_MODE_FLAG_PHSYNC;
1394 else
1395 flags |= DRM_MODE_FLAG_NHSYNC;
1396
1397 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1398 flags |= DRM_MODE_FLAG_PVSYNC;
1399 else
1400 flags |= DRM_MODE_FLAG_NVSYNC;
1401 }
1402
1403 pipe_config->adjusted_mode.flags |= flags;
1404
1405 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1406 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1407 pipe_config->port_clock = 162000;
1408 else
1409 pipe_config->port_clock = 270000;
1410 }
1411
1412 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1413 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1414 /*
1415 * This is a big fat ugly hack.
1416 *
1417 * Some machines in UEFI boot mode provide us a VBT that has 18
1418 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1419 * unknown we fail to light up. Yet the same BIOS boots up with
1420 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1421 * max, not what it tells us to use.
1422 *
1423 * Note: This will still be broken if the eDP panel is not lit
1424 * up by the BIOS, and thus we can't get the mode at module
1425 * load.
1426 */
1427 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1428 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1429 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1430 }
1431 }
1432
1433 static bool is_edp_psr(struct intel_dp *intel_dp)
1434 {
1435 return is_edp(intel_dp) &&
1436 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1437 }
1438
1439 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1440 {
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442
1443 if (!IS_HASWELL(dev))
1444 return false;
1445
1446 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1447 }
1448
1449 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1450 struct edp_vsc_psr *vsc_psr)
1451 {
1452 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1453 struct drm_device *dev = dig_port->base.base.dev;
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1456 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1457 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1458 uint32_t *data = (uint32_t *) vsc_psr;
1459 unsigned int i;
1460
1461 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1462 the video DIP being updated before program video DIP data buffer
1463 registers for DIP being updated. */
1464 I915_WRITE(ctl_reg, 0);
1465 POSTING_READ(ctl_reg);
1466
1467 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1468 if (i < sizeof(struct edp_vsc_psr))
1469 I915_WRITE(data_reg + i, *data++);
1470 else
1471 I915_WRITE(data_reg + i, 0);
1472 }
1473
1474 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1475 POSTING_READ(ctl_reg);
1476 }
1477
1478 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1479 {
1480 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct edp_vsc_psr psr_vsc;
1483
1484 if (intel_dp->psr_setup_done)
1485 return;
1486
1487 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1488 memset(&psr_vsc, 0, sizeof(psr_vsc));
1489 psr_vsc.sdp_header.HB0 = 0;
1490 psr_vsc.sdp_header.HB1 = 0x7;
1491 psr_vsc.sdp_header.HB2 = 0x2;
1492 psr_vsc.sdp_header.HB3 = 0x8;
1493 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1494
1495 /* Avoid continuous PSR exit by masking memup and hpd */
1496 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1497 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1498
1499 intel_dp->psr_setup_done = true;
1500 }
1501
1502 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1503 {
1504 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1507 int precharge = 0x3;
1508 int msg_size = 5; /* Header(4) + Message(1) */
1509
1510 /* Enable PSR in sink */
1511 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1512 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1513 DP_PSR_ENABLE &
1514 ~DP_PSR_MAIN_LINK_ACTIVE);
1515 else
1516 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1517 DP_PSR_ENABLE |
1518 DP_PSR_MAIN_LINK_ACTIVE);
1519
1520 /* Setup AUX registers */
1521 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1522 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1523 I915_WRITE(EDP_PSR_AUX_CTL,
1524 DP_AUX_CH_CTL_TIME_OUT_400us |
1525 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1526 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1527 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1528 }
1529
1530 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1531 {
1532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 uint32_t max_sleep_time = 0x1f;
1535 uint32_t idle_frames = 1;
1536 uint32_t val = 0x0;
1537
1538 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1539 val |= EDP_PSR_LINK_STANDBY;
1540 val |= EDP_PSR_TP2_TP3_TIME_0us;
1541 val |= EDP_PSR_TP1_TIME_0us;
1542 val |= EDP_PSR_SKIP_AUX_EXIT;
1543 } else
1544 val |= EDP_PSR_LINK_DISABLE;
1545
1546 I915_WRITE(EDP_PSR_CTL, val |
1547 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1548 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1549 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1550 EDP_PSR_ENABLE);
1551 }
1552
1553 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1554 {
1555 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1556 struct drm_device *dev = dig_port->base.base.dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 struct drm_crtc *crtc = dig_port->base.base.crtc;
1559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1560 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1561 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1562
1563 if (!IS_HASWELL(dev)) {
1564 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1565 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1566 return false;
1567 }
1568
1569 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1570 (dig_port->port != PORT_A)) {
1571 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1572 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1573 return false;
1574 }
1575
1576 if (!is_edp_psr(intel_dp)) {
1577 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1578 dev_priv->no_psr_reason = PSR_NO_SINK;
1579 return false;
1580 }
1581
1582 if (!i915_enable_psr) {
1583 DRM_DEBUG_KMS("PSR disable by flag\n");
1584 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1585 return false;
1586 }
1587
1588 crtc = dig_port->base.base.crtc;
1589 if (crtc == NULL) {
1590 DRM_DEBUG_KMS("crtc not active for PSR\n");
1591 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1592 return false;
1593 }
1594
1595 intel_crtc = to_intel_crtc(crtc);
1596 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1597 DRM_DEBUG_KMS("crtc not active for PSR\n");
1598 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1599 return false;
1600 }
1601
1602 obj = to_intel_framebuffer(crtc->fb)->obj;
1603 if (obj->tiling_mode != I915_TILING_X ||
1604 obj->fence_reg == I915_FENCE_REG_NONE) {
1605 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1606 dev_priv->no_psr_reason = PSR_NOT_TILED;
1607 return false;
1608 }
1609
1610 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1611 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1612 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1613 return false;
1614 }
1615
1616 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1617 S3D_ENABLE) {
1618 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1619 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1620 return false;
1621 }
1622
1623 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1624 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1625 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1626 return false;
1627 }
1628
1629 return true;
1630 }
1631
1632 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1633 {
1634 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1635
1636 if (!intel_edp_psr_match_conditions(intel_dp) ||
1637 intel_edp_is_psr_enabled(dev))
1638 return;
1639
1640 /* Setup PSR once */
1641 intel_edp_psr_setup(intel_dp);
1642
1643 /* Enable PSR on the panel */
1644 intel_edp_psr_enable_sink(intel_dp);
1645
1646 /* Enable PSR on the host */
1647 intel_edp_psr_enable_source(intel_dp);
1648 }
1649
1650 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1651 {
1652 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1653
1654 if (intel_edp_psr_match_conditions(intel_dp) &&
1655 !intel_edp_is_psr_enabled(dev))
1656 intel_edp_psr_do_enable(intel_dp);
1657 }
1658
1659 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1660 {
1661 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664 if (!intel_edp_is_psr_enabled(dev))
1665 return;
1666
1667 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1668
1669 /* Wait till PSR is idle */
1670 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1671 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1672 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1673 }
1674
1675 void intel_edp_psr_update(struct drm_device *dev)
1676 {
1677 struct intel_encoder *encoder;
1678 struct intel_dp *intel_dp = NULL;
1679
1680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1681 if (encoder->type == INTEL_OUTPUT_EDP) {
1682 intel_dp = enc_to_intel_dp(&encoder->base);
1683
1684 if (!is_edp_psr(intel_dp))
1685 return;
1686
1687 if (!intel_edp_psr_match_conditions(intel_dp))
1688 intel_edp_psr_disable(intel_dp);
1689 else
1690 if (!intel_edp_is_psr_enabled(dev))
1691 intel_edp_psr_do_enable(intel_dp);
1692 }
1693 }
1694
1695 static void intel_disable_dp(struct intel_encoder *encoder)
1696 {
1697 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1698 enum port port = dp_to_dig_port(intel_dp)->port;
1699 struct drm_device *dev = encoder->base.dev;
1700
1701 /* Make sure the panel is off before trying to change the mode. But also
1702 * ensure that we have vdd while we switch off the panel. */
1703 ironlake_edp_panel_vdd_on(intel_dp);
1704 ironlake_edp_backlight_off(intel_dp);
1705 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1706 ironlake_edp_panel_off(intel_dp);
1707
1708 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1709 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1710 intel_dp_link_down(intel_dp);
1711 }
1712
1713 static void intel_post_disable_dp(struct intel_encoder *encoder)
1714 {
1715 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1716 enum port port = dp_to_dig_port(intel_dp)->port;
1717 struct drm_device *dev = encoder->base.dev;
1718
1719 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1720 intel_dp_link_down(intel_dp);
1721 if (!IS_VALLEYVIEW(dev))
1722 ironlake_edp_pll_off(intel_dp);
1723 }
1724 }
1725
1726 static void intel_enable_dp(struct intel_encoder *encoder)
1727 {
1728 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1729 struct drm_device *dev = encoder->base.dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1732
1733 if (WARN_ON(dp_reg & DP_PORT_EN))
1734 return;
1735
1736 ironlake_edp_panel_vdd_on(intel_dp);
1737 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1738 intel_dp_start_link_train(intel_dp);
1739 ironlake_edp_panel_on(intel_dp);
1740 ironlake_edp_panel_vdd_off(intel_dp, true);
1741 intel_dp_complete_link_train(intel_dp);
1742 intel_dp_stop_link_train(intel_dp);
1743 ironlake_edp_backlight_on(intel_dp);
1744 }
1745
1746 static void vlv_enable_dp(struct intel_encoder *encoder)
1747 {
1748 }
1749
1750 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1751 {
1752 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1753 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1754
1755 if (dport->port == PORT_A)
1756 ironlake_edp_pll_on(intel_dp);
1757 }
1758
1759 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1760 {
1761 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1762 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1763 struct drm_device *dev = encoder->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1766 int port = vlv_dport_to_channel(dport);
1767 int pipe = intel_crtc->pipe;
1768 u32 val;
1769
1770 mutex_lock(&dev_priv->dpio_lock);
1771
1772 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1773 val = 0;
1774 if (pipe)
1775 val |= (1<<21);
1776 else
1777 val &= ~(1<<21);
1778 val |= 0x001000c4;
1779 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1780 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1781 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1782
1783 mutex_unlock(&dev_priv->dpio_lock);
1784
1785 intel_enable_dp(encoder);
1786
1787 vlv_wait_port_ready(dev_priv, port);
1788 }
1789
1790 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1791 {
1792 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1793 struct drm_device *dev = encoder->base.dev;
1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 int port = vlv_dport_to_channel(dport);
1796
1797 if (!IS_VALLEYVIEW(dev))
1798 return;
1799
1800 /* Program Tx lane resets to default */
1801 mutex_lock(&dev_priv->dpio_lock);
1802 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1803 DPIO_PCS_TX_LANE2_RESET |
1804 DPIO_PCS_TX_LANE1_RESET);
1805 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1806 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1807 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1808 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1809 DPIO_PCS_CLK_SOFT_RESET);
1810
1811 /* Fix up inter-pair skew failure */
1812 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1813 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1814 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1815 mutex_unlock(&dev_priv->dpio_lock);
1816 }
1817
1818 /*
1819 * Native read with retry for link status and receiver capability reads for
1820 * cases where the sink may still be asleep.
1821 */
1822 static bool
1823 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1824 uint8_t *recv, int recv_bytes)
1825 {
1826 int ret, i;
1827
1828 /*
1829 * Sinks are *supposed* to come up within 1ms from an off state,
1830 * but we're also supposed to retry 3 times per the spec.
1831 */
1832 for (i = 0; i < 3; i++) {
1833 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1834 recv_bytes);
1835 if (ret == recv_bytes)
1836 return true;
1837 msleep(1);
1838 }
1839
1840 return false;
1841 }
1842
1843 /*
1844 * Fetch AUX CH registers 0x202 - 0x207 which contain
1845 * link status information
1846 */
1847 static bool
1848 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1849 {
1850 return intel_dp_aux_native_read_retry(intel_dp,
1851 DP_LANE0_1_STATUS,
1852 link_status,
1853 DP_LINK_STATUS_SIZE);
1854 }
1855
1856 #if 0
1857 static char *voltage_names[] = {
1858 "0.4V", "0.6V", "0.8V", "1.2V"
1859 };
1860 static char *pre_emph_names[] = {
1861 "0dB", "3.5dB", "6dB", "9.5dB"
1862 };
1863 static char *link_train_names[] = {
1864 "pattern 1", "pattern 2", "idle", "off"
1865 };
1866 #endif
1867
1868 /*
1869 * These are source-specific values; current Intel hardware supports
1870 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1871 */
1872
1873 static uint8_t
1874 intel_dp_voltage_max(struct intel_dp *intel_dp)
1875 {
1876 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1877 enum port port = dp_to_dig_port(intel_dp)->port;
1878
1879 if (IS_VALLEYVIEW(dev))
1880 return DP_TRAIN_VOLTAGE_SWING_1200;
1881 else if (IS_GEN7(dev) && port == PORT_A)
1882 return DP_TRAIN_VOLTAGE_SWING_800;
1883 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1884 return DP_TRAIN_VOLTAGE_SWING_1200;
1885 else
1886 return DP_TRAIN_VOLTAGE_SWING_800;
1887 }
1888
1889 static uint8_t
1890 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1891 {
1892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1893 enum port port = dp_to_dig_port(intel_dp)->port;
1894
1895 if (HAS_DDI(dev)) {
1896 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1897 case DP_TRAIN_VOLTAGE_SWING_400:
1898 return DP_TRAIN_PRE_EMPHASIS_9_5;
1899 case DP_TRAIN_VOLTAGE_SWING_600:
1900 return DP_TRAIN_PRE_EMPHASIS_6;
1901 case DP_TRAIN_VOLTAGE_SWING_800:
1902 return DP_TRAIN_PRE_EMPHASIS_3_5;
1903 case DP_TRAIN_VOLTAGE_SWING_1200:
1904 default:
1905 return DP_TRAIN_PRE_EMPHASIS_0;
1906 }
1907 } else if (IS_VALLEYVIEW(dev)) {
1908 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1909 case DP_TRAIN_VOLTAGE_SWING_400:
1910 return DP_TRAIN_PRE_EMPHASIS_9_5;
1911 case DP_TRAIN_VOLTAGE_SWING_600:
1912 return DP_TRAIN_PRE_EMPHASIS_6;
1913 case DP_TRAIN_VOLTAGE_SWING_800:
1914 return DP_TRAIN_PRE_EMPHASIS_3_5;
1915 case DP_TRAIN_VOLTAGE_SWING_1200:
1916 default:
1917 return DP_TRAIN_PRE_EMPHASIS_0;
1918 }
1919 } else if (IS_GEN7(dev) && port == PORT_A) {
1920 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1921 case DP_TRAIN_VOLTAGE_SWING_400:
1922 return DP_TRAIN_PRE_EMPHASIS_6;
1923 case DP_TRAIN_VOLTAGE_SWING_600:
1924 case DP_TRAIN_VOLTAGE_SWING_800:
1925 return DP_TRAIN_PRE_EMPHASIS_3_5;
1926 default:
1927 return DP_TRAIN_PRE_EMPHASIS_0;
1928 }
1929 } else {
1930 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1931 case DP_TRAIN_VOLTAGE_SWING_400:
1932 return DP_TRAIN_PRE_EMPHASIS_6;
1933 case DP_TRAIN_VOLTAGE_SWING_600:
1934 return DP_TRAIN_PRE_EMPHASIS_6;
1935 case DP_TRAIN_VOLTAGE_SWING_800:
1936 return DP_TRAIN_PRE_EMPHASIS_3_5;
1937 case DP_TRAIN_VOLTAGE_SWING_1200:
1938 default:
1939 return DP_TRAIN_PRE_EMPHASIS_0;
1940 }
1941 }
1942 }
1943
1944 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1945 {
1946 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1949 unsigned long demph_reg_value, preemph_reg_value,
1950 uniqtranscale_reg_value;
1951 uint8_t train_set = intel_dp->train_set[0];
1952 int port = vlv_dport_to_channel(dport);
1953
1954 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1955 case DP_TRAIN_PRE_EMPHASIS_0:
1956 preemph_reg_value = 0x0004000;
1957 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1958 case DP_TRAIN_VOLTAGE_SWING_400:
1959 demph_reg_value = 0x2B405555;
1960 uniqtranscale_reg_value = 0x552AB83A;
1961 break;
1962 case DP_TRAIN_VOLTAGE_SWING_600:
1963 demph_reg_value = 0x2B404040;
1964 uniqtranscale_reg_value = 0x5548B83A;
1965 break;
1966 case DP_TRAIN_VOLTAGE_SWING_800:
1967 demph_reg_value = 0x2B245555;
1968 uniqtranscale_reg_value = 0x5560B83A;
1969 break;
1970 case DP_TRAIN_VOLTAGE_SWING_1200:
1971 demph_reg_value = 0x2B405555;
1972 uniqtranscale_reg_value = 0x5598DA3A;
1973 break;
1974 default:
1975 return 0;
1976 }
1977 break;
1978 case DP_TRAIN_PRE_EMPHASIS_3_5:
1979 preemph_reg_value = 0x0002000;
1980 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1981 case DP_TRAIN_VOLTAGE_SWING_400:
1982 demph_reg_value = 0x2B404040;
1983 uniqtranscale_reg_value = 0x5552B83A;
1984 break;
1985 case DP_TRAIN_VOLTAGE_SWING_600:
1986 demph_reg_value = 0x2B404848;
1987 uniqtranscale_reg_value = 0x5580B83A;
1988 break;
1989 case DP_TRAIN_VOLTAGE_SWING_800:
1990 demph_reg_value = 0x2B404040;
1991 uniqtranscale_reg_value = 0x55ADDA3A;
1992 break;
1993 default:
1994 return 0;
1995 }
1996 break;
1997 case DP_TRAIN_PRE_EMPHASIS_6:
1998 preemph_reg_value = 0x0000000;
1999 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2000 case DP_TRAIN_VOLTAGE_SWING_400:
2001 demph_reg_value = 0x2B305555;
2002 uniqtranscale_reg_value = 0x5570B83A;
2003 break;
2004 case DP_TRAIN_VOLTAGE_SWING_600:
2005 demph_reg_value = 0x2B2B4040;
2006 uniqtranscale_reg_value = 0x55ADDA3A;
2007 break;
2008 default:
2009 return 0;
2010 }
2011 break;
2012 case DP_TRAIN_PRE_EMPHASIS_9_5:
2013 preemph_reg_value = 0x0006000;
2014 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2015 case DP_TRAIN_VOLTAGE_SWING_400:
2016 demph_reg_value = 0x1B405555;
2017 uniqtranscale_reg_value = 0x55ADDA3A;
2018 break;
2019 default:
2020 return 0;
2021 }
2022 break;
2023 default:
2024 return 0;
2025 }
2026
2027 mutex_lock(&dev_priv->dpio_lock);
2028 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
2029 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2030 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
2031 uniqtranscale_reg_value);
2032 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2033 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
2034 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2035 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
2036 mutex_unlock(&dev_priv->dpio_lock);
2037
2038 return 0;
2039 }
2040
2041 static void
2042 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2043 {
2044 uint8_t v = 0;
2045 uint8_t p = 0;
2046 int lane;
2047 uint8_t voltage_max;
2048 uint8_t preemph_max;
2049
2050 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2051 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2052 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2053
2054 if (this_v > v)
2055 v = this_v;
2056 if (this_p > p)
2057 p = this_p;
2058 }
2059
2060 voltage_max = intel_dp_voltage_max(intel_dp);
2061 if (v >= voltage_max)
2062 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2063
2064 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2065 if (p >= preemph_max)
2066 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2067
2068 for (lane = 0; lane < 4; lane++)
2069 intel_dp->train_set[lane] = v | p;
2070 }
2071
2072 static uint32_t
2073 intel_gen4_signal_levels(uint8_t train_set)
2074 {
2075 uint32_t signal_levels = 0;
2076
2077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2078 case DP_TRAIN_VOLTAGE_SWING_400:
2079 default:
2080 signal_levels |= DP_VOLTAGE_0_4;
2081 break;
2082 case DP_TRAIN_VOLTAGE_SWING_600:
2083 signal_levels |= DP_VOLTAGE_0_6;
2084 break;
2085 case DP_TRAIN_VOLTAGE_SWING_800:
2086 signal_levels |= DP_VOLTAGE_0_8;
2087 break;
2088 case DP_TRAIN_VOLTAGE_SWING_1200:
2089 signal_levels |= DP_VOLTAGE_1_2;
2090 break;
2091 }
2092 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2093 case DP_TRAIN_PRE_EMPHASIS_0:
2094 default:
2095 signal_levels |= DP_PRE_EMPHASIS_0;
2096 break;
2097 case DP_TRAIN_PRE_EMPHASIS_3_5:
2098 signal_levels |= DP_PRE_EMPHASIS_3_5;
2099 break;
2100 case DP_TRAIN_PRE_EMPHASIS_6:
2101 signal_levels |= DP_PRE_EMPHASIS_6;
2102 break;
2103 case DP_TRAIN_PRE_EMPHASIS_9_5:
2104 signal_levels |= DP_PRE_EMPHASIS_9_5;
2105 break;
2106 }
2107 return signal_levels;
2108 }
2109
2110 /* Gen6's DP voltage swing and pre-emphasis control */
2111 static uint32_t
2112 intel_gen6_edp_signal_levels(uint8_t train_set)
2113 {
2114 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2115 DP_TRAIN_PRE_EMPHASIS_MASK);
2116 switch (signal_levels) {
2117 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2118 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2119 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2120 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2121 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2122 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2123 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2124 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2125 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2126 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2127 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2128 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2129 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2130 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2131 default:
2132 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2133 "0x%x\n", signal_levels);
2134 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2135 }
2136 }
2137
2138 /* Gen7's DP voltage swing and pre-emphasis control */
2139 static uint32_t
2140 intel_gen7_edp_signal_levels(uint8_t train_set)
2141 {
2142 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2143 DP_TRAIN_PRE_EMPHASIS_MASK);
2144 switch (signal_levels) {
2145 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2146 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2147 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2148 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2149 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2150 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2151
2152 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2153 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2154 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2155 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2156
2157 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2158 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2159 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2160 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2161
2162 default:
2163 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2164 "0x%x\n", signal_levels);
2165 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2166 }
2167 }
2168
2169 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2170 static uint32_t
2171 intel_hsw_signal_levels(uint8_t train_set)
2172 {
2173 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2174 DP_TRAIN_PRE_EMPHASIS_MASK);
2175 switch (signal_levels) {
2176 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2177 return DDI_BUF_EMP_400MV_0DB_HSW;
2178 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2179 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2180 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2181 return DDI_BUF_EMP_400MV_6DB_HSW;
2182 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2183 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2184
2185 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2186 return DDI_BUF_EMP_600MV_0DB_HSW;
2187 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2188 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2189 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2190 return DDI_BUF_EMP_600MV_6DB_HSW;
2191
2192 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2193 return DDI_BUF_EMP_800MV_0DB_HSW;
2194 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2195 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2196 default:
2197 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2198 "0x%x\n", signal_levels);
2199 return DDI_BUF_EMP_400MV_0DB_HSW;
2200 }
2201 }
2202
2203 /* Properly updates "DP" with the correct signal levels. */
2204 static void
2205 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2206 {
2207 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2208 enum port port = intel_dig_port->port;
2209 struct drm_device *dev = intel_dig_port->base.base.dev;
2210 uint32_t signal_levels, mask;
2211 uint8_t train_set = intel_dp->train_set[0];
2212
2213 if (HAS_DDI(dev)) {
2214 signal_levels = intel_hsw_signal_levels(train_set);
2215 mask = DDI_BUF_EMP_MASK;
2216 } else if (IS_VALLEYVIEW(dev)) {
2217 signal_levels = intel_vlv_signal_levels(intel_dp);
2218 mask = 0;
2219 } else if (IS_GEN7(dev) && port == PORT_A) {
2220 signal_levels = intel_gen7_edp_signal_levels(train_set);
2221 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2222 } else if (IS_GEN6(dev) && port == PORT_A) {
2223 signal_levels = intel_gen6_edp_signal_levels(train_set);
2224 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2225 } else {
2226 signal_levels = intel_gen4_signal_levels(train_set);
2227 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2228 }
2229
2230 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2231
2232 *DP = (*DP & ~mask) | signal_levels;
2233 }
2234
2235 static bool
2236 intel_dp_set_link_train(struct intel_dp *intel_dp,
2237 uint32_t dp_reg_value,
2238 uint8_t dp_train_pat)
2239 {
2240 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2241 struct drm_device *dev = intel_dig_port->base.base.dev;
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 enum port port = intel_dig_port->port;
2244 int ret;
2245
2246 if (HAS_DDI(dev)) {
2247 uint32_t temp = I915_READ(DP_TP_CTL(port));
2248
2249 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2250 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2251 else
2252 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2253
2254 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2255 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2256 case DP_TRAINING_PATTERN_DISABLE:
2257 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2258
2259 break;
2260 case DP_TRAINING_PATTERN_1:
2261 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2262 break;
2263 case DP_TRAINING_PATTERN_2:
2264 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2265 break;
2266 case DP_TRAINING_PATTERN_3:
2267 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2268 break;
2269 }
2270 I915_WRITE(DP_TP_CTL(port), temp);
2271
2272 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2273 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2274
2275 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2276 case DP_TRAINING_PATTERN_DISABLE:
2277 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2278 break;
2279 case DP_TRAINING_PATTERN_1:
2280 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2281 break;
2282 case DP_TRAINING_PATTERN_2:
2283 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2284 break;
2285 case DP_TRAINING_PATTERN_3:
2286 DRM_ERROR("DP training pattern 3 not supported\n");
2287 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2288 break;
2289 }
2290
2291 } else {
2292 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2293
2294 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2295 case DP_TRAINING_PATTERN_DISABLE:
2296 dp_reg_value |= DP_LINK_TRAIN_OFF;
2297 break;
2298 case DP_TRAINING_PATTERN_1:
2299 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2300 break;
2301 case DP_TRAINING_PATTERN_2:
2302 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2303 break;
2304 case DP_TRAINING_PATTERN_3:
2305 DRM_ERROR("DP training pattern 3 not supported\n");
2306 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2307 break;
2308 }
2309 }
2310
2311 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2312 POSTING_READ(intel_dp->output_reg);
2313
2314 intel_dp_aux_native_write_1(intel_dp,
2315 DP_TRAINING_PATTERN_SET,
2316 dp_train_pat);
2317
2318 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2319 DP_TRAINING_PATTERN_DISABLE) {
2320 ret = intel_dp_aux_native_write(intel_dp,
2321 DP_TRAINING_LANE0_SET,
2322 intel_dp->train_set,
2323 intel_dp->lane_count);
2324 if (ret != intel_dp->lane_count)
2325 return false;
2326 }
2327
2328 return true;
2329 }
2330
2331 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2332 {
2333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2334 struct drm_device *dev = intel_dig_port->base.base.dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 enum port port = intel_dig_port->port;
2337 uint32_t val;
2338
2339 if (!HAS_DDI(dev))
2340 return;
2341
2342 val = I915_READ(DP_TP_CTL(port));
2343 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2344 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2345 I915_WRITE(DP_TP_CTL(port), val);
2346
2347 /*
2348 * On PORT_A we can have only eDP in SST mode. There the only reason
2349 * we need to set idle transmission mode is to work around a HW issue
2350 * where we enable the pipe while not in idle link-training mode.
2351 * In this case there is requirement to wait for a minimum number of
2352 * idle patterns to be sent.
2353 */
2354 if (port == PORT_A)
2355 return;
2356
2357 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2358 1))
2359 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2360 }
2361
2362 /* Enable corresponding port and start training pattern 1 */
2363 void
2364 intel_dp_start_link_train(struct intel_dp *intel_dp)
2365 {
2366 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2367 struct drm_device *dev = encoder->dev;
2368 int i;
2369 uint8_t voltage;
2370 int voltage_tries, loop_tries;
2371 uint32_t DP = intel_dp->DP;
2372
2373 if (HAS_DDI(dev))
2374 intel_ddi_prepare_link_retrain(encoder);
2375
2376 /* Write the link configuration data */
2377 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2378 intel_dp->link_configuration,
2379 DP_LINK_CONFIGURATION_SIZE);
2380
2381 DP |= DP_PORT_EN;
2382
2383 memset(intel_dp->train_set, 0, 4);
2384 voltage = 0xff;
2385 voltage_tries = 0;
2386 loop_tries = 0;
2387 for (;;) {
2388 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2389 uint8_t link_status[DP_LINK_STATUS_SIZE];
2390
2391 intel_dp_set_signal_levels(intel_dp, &DP);
2392
2393 /* Set training pattern 1 */
2394 if (!intel_dp_set_link_train(intel_dp, DP,
2395 DP_TRAINING_PATTERN_1 |
2396 DP_LINK_SCRAMBLING_DISABLE))
2397 break;
2398
2399 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2400 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2401 DRM_ERROR("failed to get link status\n");
2402 break;
2403 }
2404
2405 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2406 DRM_DEBUG_KMS("clock recovery OK\n");
2407 break;
2408 }
2409
2410 /* Check to see if we've tried the max voltage */
2411 for (i = 0; i < intel_dp->lane_count; i++)
2412 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2413 break;
2414 if (i == intel_dp->lane_count) {
2415 ++loop_tries;
2416 if (loop_tries == 5) {
2417 DRM_DEBUG_KMS("too many full retries, give up\n");
2418 break;
2419 }
2420 memset(intel_dp->train_set, 0, 4);
2421 voltage_tries = 0;
2422 continue;
2423 }
2424
2425 /* Check to see if we've tried the same voltage 5 times */
2426 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2427 ++voltage_tries;
2428 if (voltage_tries == 5) {
2429 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2430 break;
2431 }
2432 } else
2433 voltage_tries = 0;
2434 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2435
2436 /* Compute new intel_dp->train_set as requested by target */
2437 intel_get_adjust_train(intel_dp, link_status);
2438 }
2439
2440 intel_dp->DP = DP;
2441 }
2442
2443 void
2444 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2445 {
2446 bool channel_eq = false;
2447 int tries, cr_tries;
2448 uint32_t DP = intel_dp->DP;
2449
2450 /* channel equalization */
2451 tries = 0;
2452 cr_tries = 0;
2453 channel_eq = false;
2454 for (;;) {
2455 uint8_t link_status[DP_LINK_STATUS_SIZE];
2456
2457 if (cr_tries > 5) {
2458 DRM_ERROR("failed to train DP, aborting\n");
2459 intel_dp_link_down(intel_dp);
2460 break;
2461 }
2462
2463 intel_dp_set_signal_levels(intel_dp, &DP);
2464
2465 /* channel eq pattern */
2466 if (!intel_dp_set_link_train(intel_dp, DP,
2467 DP_TRAINING_PATTERN_2 |
2468 DP_LINK_SCRAMBLING_DISABLE))
2469 break;
2470
2471 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2472 if (!intel_dp_get_link_status(intel_dp, link_status))
2473 break;
2474
2475 /* Make sure clock is still ok */
2476 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2477 intel_dp_start_link_train(intel_dp);
2478 cr_tries++;
2479 continue;
2480 }
2481
2482 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2483 channel_eq = true;
2484 break;
2485 }
2486
2487 /* Try 5 times, then try clock recovery if that fails */
2488 if (tries > 5) {
2489 intel_dp_link_down(intel_dp);
2490 intel_dp_start_link_train(intel_dp);
2491 tries = 0;
2492 cr_tries++;
2493 continue;
2494 }
2495
2496 /* Compute new intel_dp->train_set as requested by target */
2497 intel_get_adjust_train(intel_dp, link_status);
2498 ++tries;
2499 }
2500
2501 intel_dp_set_idle_link_train(intel_dp);
2502
2503 intel_dp->DP = DP;
2504
2505 if (channel_eq)
2506 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2507
2508 }
2509
2510 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2511 {
2512 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2513 DP_TRAINING_PATTERN_DISABLE);
2514 }
2515
2516 static void
2517 intel_dp_link_down(struct intel_dp *intel_dp)
2518 {
2519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520 enum port port = intel_dig_port->port;
2521 struct drm_device *dev = intel_dig_port->base.base.dev;
2522 struct drm_i915_private *dev_priv = dev->dev_private;
2523 struct intel_crtc *intel_crtc =
2524 to_intel_crtc(intel_dig_port->base.base.crtc);
2525 uint32_t DP = intel_dp->DP;
2526
2527 /*
2528 * DDI code has a strict mode set sequence and we should try to respect
2529 * it, otherwise we might hang the machine in many different ways. So we
2530 * really should be disabling the port only on a complete crtc_disable
2531 * sequence. This function is just called under two conditions on DDI
2532 * code:
2533 * - Link train failed while doing crtc_enable, and on this case we
2534 * really should respect the mode set sequence and wait for a
2535 * crtc_disable.
2536 * - Someone turned the monitor off and intel_dp_check_link_status
2537 * called us. We don't need to disable the whole port on this case, so
2538 * when someone turns the monitor on again,
2539 * intel_ddi_prepare_link_retrain will take care of redoing the link
2540 * train.
2541 */
2542 if (HAS_DDI(dev))
2543 return;
2544
2545 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2546 return;
2547
2548 DRM_DEBUG_KMS("\n");
2549
2550 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2551 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2552 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2553 } else {
2554 DP &= ~DP_LINK_TRAIN_MASK;
2555 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2556 }
2557 POSTING_READ(intel_dp->output_reg);
2558
2559 /* We don't really know why we're doing this */
2560 intel_wait_for_vblank(dev, intel_crtc->pipe);
2561
2562 if (HAS_PCH_IBX(dev) &&
2563 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2564 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2565
2566 /* Hardware workaround: leaving our transcoder select
2567 * set to transcoder B while it's off will prevent the
2568 * corresponding HDMI output on transcoder A.
2569 *
2570 * Combine this with another hardware workaround:
2571 * transcoder select bit can only be cleared while the
2572 * port is enabled.
2573 */
2574 DP &= ~DP_PIPEB_SELECT;
2575 I915_WRITE(intel_dp->output_reg, DP);
2576
2577 /* Changes to enable or select take place the vblank
2578 * after being written.
2579 */
2580 if (WARN_ON(crtc == NULL)) {
2581 /* We should never try to disable a port without a crtc
2582 * attached. For paranoia keep the code around for a
2583 * bit. */
2584 POSTING_READ(intel_dp->output_reg);
2585 msleep(50);
2586 } else
2587 intel_wait_for_vblank(dev, intel_crtc->pipe);
2588 }
2589
2590 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2591 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2592 POSTING_READ(intel_dp->output_reg);
2593 msleep(intel_dp->panel_power_down_delay);
2594 }
2595
2596 static bool
2597 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2598 {
2599 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2600
2601 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2602 sizeof(intel_dp->dpcd)) == 0)
2603 return false; /* aux transfer failed */
2604
2605 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2606 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2607 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2608
2609 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2610 return false; /* DPCD not present */
2611
2612 /* Check if the panel supports PSR */
2613 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2614 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2615 intel_dp->psr_dpcd,
2616 sizeof(intel_dp->psr_dpcd));
2617 if (is_edp_psr(intel_dp))
2618 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2619 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2620 DP_DWN_STRM_PORT_PRESENT))
2621 return true; /* native DP sink */
2622
2623 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2624 return true; /* no per-port downstream info */
2625
2626 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2627 intel_dp->downstream_ports,
2628 DP_MAX_DOWNSTREAM_PORTS) == 0)
2629 return false; /* downstream port status fetch failed */
2630
2631 return true;
2632 }
2633
2634 static void
2635 intel_dp_probe_oui(struct intel_dp *intel_dp)
2636 {
2637 u8 buf[3];
2638
2639 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2640 return;
2641
2642 ironlake_edp_panel_vdd_on(intel_dp);
2643
2644 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2645 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2646 buf[0], buf[1], buf[2]);
2647
2648 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2649 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2650 buf[0], buf[1], buf[2]);
2651
2652 ironlake_edp_panel_vdd_off(intel_dp, false);
2653 }
2654
2655 static bool
2656 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2657 {
2658 int ret;
2659
2660 ret = intel_dp_aux_native_read_retry(intel_dp,
2661 DP_DEVICE_SERVICE_IRQ_VECTOR,
2662 sink_irq_vector, 1);
2663 if (!ret)
2664 return false;
2665
2666 return true;
2667 }
2668
2669 static void
2670 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2671 {
2672 /* NAK by default */
2673 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2674 }
2675
2676 /*
2677 * According to DP spec
2678 * 5.1.2:
2679 * 1. Read DPCD
2680 * 2. Configure link according to Receiver Capabilities
2681 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2682 * 4. Check link status on receipt of hot-plug interrupt
2683 */
2684
2685 void
2686 intel_dp_check_link_status(struct intel_dp *intel_dp)
2687 {
2688 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2689 u8 sink_irq_vector;
2690 u8 link_status[DP_LINK_STATUS_SIZE];
2691
2692 if (!intel_encoder->connectors_active)
2693 return;
2694
2695 if (WARN_ON(!intel_encoder->base.crtc))
2696 return;
2697
2698 /* Try to read receiver status if the link appears to be up */
2699 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2700 intel_dp_link_down(intel_dp);
2701 return;
2702 }
2703
2704 /* Now read the DPCD to see if it's actually running */
2705 if (!intel_dp_get_dpcd(intel_dp)) {
2706 intel_dp_link_down(intel_dp);
2707 return;
2708 }
2709
2710 /* Try to read the source of the interrupt */
2711 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2712 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2713 /* Clear interrupt source */
2714 intel_dp_aux_native_write_1(intel_dp,
2715 DP_DEVICE_SERVICE_IRQ_VECTOR,
2716 sink_irq_vector);
2717
2718 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2719 intel_dp_handle_test_request(intel_dp);
2720 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2721 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2722 }
2723
2724 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2725 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2726 drm_get_encoder_name(&intel_encoder->base));
2727 intel_dp_start_link_train(intel_dp);
2728 intel_dp_complete_link_train(intel_dp);
2729 intel_dp_stop_link_train(intel_dp);
2730 }
2731 }
2732
2733 /* XXX this is probably wrong for multiple downstream ports */
2734 static enum drm_connector_status
2735 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2736 {
2737 uint8_t *dpcd = intel_dp->dpcd;
2738 bool hpd;
2739 uint8_t type;
2740
2741 if (!intel_dp_get_dpcd(intel_dp))
2742 return connector_status_disconnected;
2743
2744 /* if there's no downstream port, we're done */
2745 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2746 return connector_status_connected;
2747
2748 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2749 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2750 if (hpd) {
2751 uint8_t reg;
2752 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2753 &reg, 1))
2754 return connector_status_unknown;
2755 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2756 : connector_status_disconnected;
2757 }
2758
2759 /* If no HPD, poke DDC gently */
2760 if (drm_probe_ddc(&intel_dp->adapter))
2761 return connector_status_connected;
2762
2763 /* Well we tried, say unknown for unreliable port types */
2764 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2765 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2766 return connector_status_unknown;
2767
2768 /* Anything else is out of spec, warn and ignore */
2769 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2770 return connector_status_disconnected;
2771 }
2772
2773 static enum drm_connector_status
2774 ironlake_dp_detect(struct intel_dp *intel_dp)
2775 {
2776 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2779 enum drm_connector_status status;
2780
2781 /* Can't disconnect eDP, but you can close the lid... */
2782 if (is_edp(intel_dp)) {
2783 status = intel_panel_detect(dev);
2784 if (status == connector_status_unknown)
2785 status = connector_status_connected;
2786 return status;
2787 }
2788
2789 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2790 return connector_status_disconnected;
2791
2792 return intel_dp_detect_dpcd(intel_dp);
2793 }
2794
2795 static enum drm_connector_status
2796 g4x_dp_detect(struct intel_dp *intel_dp)
2797 {
2798 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2801 uint32_t bit;
2802
2803 /* Can't disconnect eDP, but you can close the lid... */
2804 if (is_edp(intel_dp)) {
2805 enum drm_connector_status status;
2806
2807 status = intel_panel_detect(dev);
2808 if (status == connector_status_unknown)
2809 status = connector_status_connected;
2810 return status;
2811 }
2812
2813 if (IS_VALLEYVIEW(dev)) {
2814 switch (intel_dig_port->port) {
2815 case PORT_B:
2816 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
2817 break;
2818 case PORT_C:
2819 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
2820 break;
2821 case PORT_D:
2822 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
2823 break;
2824 default:
2825 return connector_status_unknown;
2826 }
2827 } else {
2828 switch (intel_dig_port->port) {
2829 case PORT_B:
2830 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
2831 break;
2832 case PORT_C:
2833 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
2834 break;
2835 case PORT_D:
2836 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
2837 break;
2838 default:
2839 return connector_status_unknown;
2840 }
2841 }
2842
2843 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2844 return connector_status_disconnected;
2845
2846 return intel_dp_detect_dpcd(intel_dp);
2847 }
2848
2849 static struct edid *
2850 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2851 {
2852 struct intel_connector *intel_connector = to_intel_connector(connector);
2853
2854 /* use cached edid if we have one */
2855 if (intel_connector->edid) {
2856 struct edid *edid;
2857 int size;
2858
2859 /* invalid edid */
2860 if (IS_ERR(intel_connector->edid))
2861 return NULL;
2862
2863 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2864 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2865 if (!edid)
2866 return NULL;
2867
2868 return edid;
2869 }
2870
2871 return drm_get_edid(connector, adapter);
2872 }
2873
2874 static int
2875 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2876 {
2877 struct intel_connector *intel_connector = to_intel_connector(connector);
2878
2879 /* use cached edid if we have one */
2880 if (intel_connector->edid) {
2881 /* invalid edid */
2882 if (IS_ERR(intel_connector->edid))
2883 return 0;
2884
2885 return intel_connector_update_modes(connector,
2886 intel_connector->edid);
2887 }
2888
2889 return intel_ddc_get_modes(connector, adapter);
2890 }
2891
2892 static enum drm_connector_status
2893 intel_dp_detect(struct drm_connector *connector, bool force)
2894 {
2895 struct intel_dp *intel_dp = intel_attached_dp(connector);
2896 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2897 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2898 struct drm_device *dev = connector->dev;
2899 enum drm_connector_status status;
2900 struct edid *edid = NULL;
2901
2902 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2903 connector->base.id, drm_get_connector_name(connector));
2904
2905 intel_dp->has_audio = false;
2906
2907 if (HAS_PCH_SPLIT(dev))
2908 status = ironlake_dp_detect(intel_dp);
2909 else
2910 status = g4x_dp_detect(intel_dp);
2911
2912 if (status != connector_status_connected)
2913 return status;
2914
2915 intel_dp_probe_oui(intel_dp);
2916
2917 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2918 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2919 } else {
2920 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2921 if (edid) {
2922 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2923 kfree(edid);
2924 }
2925 }
2926
2927 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2928 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2929 return connector_status_connected;
2930 }
2931
2932 static int intel_dp_get_modes(struct drm_connector *connector)
2933 {
2934 struct intel_dp *intel_dp = intel_attached_dp(connector);
2935 struct intel_connector *intel_connector = to_intel_connector(connector);
2936 struct drm_device *dev = connector->dev;
2937 int ret;
2938
2939 /* We should parse the EDID data and find out if it has an audio sink
2940 */
2941
2942 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2943 if (ret)
2944 return ret;
2945
2946 /* if eDP has no EDID, fall back to fixed mode */
2947 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2948 struct drm_display_mode *mode;
2949 mode = drm_mode_duplicate(dev,
2950 intel_connector->panel.fixed_mode);
2951 if (mode) {
2952 drm_mode_probed_add(connector, mode);
2953 return 1;
2954 }
2955 }
2956 return 0;
2957 }
2958
2959 static bool
2960 intel_dp_detect_audio(struct drm_connector *connector)
2961 {
2962 struct intel_dp *intel_dp = intel_attached_dp(connector);
2963 struct edid *edid;
2964 bool has_audio = false;
2965
2966 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2967 if (edid) {
2968 has_audio = drm_detect_monitor_audio(edid);
2969 kfree(edid);
2970 }
2971
2972 return has_audio;
2973 }
2974
2975 static int
2976 intel_dp_set_property(struct drm_connector *connector,
2977 struct drm_property *property,
2978 uint64_t val)
2979 {
2980 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2981 struct intel_connector *intel_connector = to_intel_connector(connector);
2982 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2983 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2984 int ret;
2985
2986 ret = drm_object_property_set_value(&connector->base, property, val);
2987 if (ret)
2988 return ret;
2989
2990 if (property == dev_priv->force_audio_property) {
2991 int i = val;
2992 bool has_audio;
2993
2994 if (i == intel_dp->force_audio)
2995 return 0;
2996
2997 intel_dp->force_audio = i;
2998
2999 if (i == HDMI_AUDIO_AUTO)
3000 has_audio = intel_dp_detect_audio(connector);
3001 else
3002 has_audio = (i == HDMI_AUDIO_ON);
3003
3004 if (has_audio == intel_dp->has_audio)
3005 return 0;
3006
3007 intel_dp->has_audio = has_audio;
3008 goto done;
3009 }
3010
3011 if (property == dev_priv->broadcast_rgb_property) {
3012 bool old_auto = intel_dp->color_range_auto;
3013 uint32_t old_range = intel_dp->color_range;
3014
3015 switch (val) {
3016 case INTEL_BROADCAST_RGB_AUTO:
3017 intel_dp->color_range_auto = true;
3018 break;
3019 case INTEL_BROADCAST_RGB_FULL:
3020 intel_dp->color_range_auto = false;
3021 intel_dp->color_range = 0;
3022 break;
3023 case INTEL_BROADCAST_RGB_LIMITED:
3024 intel_dp->color_range_auto = false;
3025 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3026 break;
3027 default:
3028 return -EINVAL;
3029 }
3030
3031 if (old_auto == intel_dp->color_range_auto &&
3032 old_range == intel_dp->color_range)
3033 return 0;
3034
3035 goto done;
3036 }
3037
3038 if (is_edp(intel_dp) &&
3039 property == connector->dev->mode_config.scaling_mode_property) {
3040 if (val == DRM_MODE_SCALE_NONE) {
3041 DRM_DEBUG_KMS("no scaling not supported\n");
3042 return -EINVAL;
3043 }
3044
3045 if (intel_connector->panel.fitting_mode == val) {
3046 /* the eDP scaling property is not changed */
3047 return 0;
3048 }
3049 intel_connector->panel.fitting_mode = val;
3050
3051 goto done;
3052 }
3053
3054 return -EINVAL;
3055
3056 done:
3057 if (intel_encoder->base.crtc)
3058 intel_crtc_restore_mode(intel_encoder->base.crtc);
3059
3060 return 0;
3061 }
3062
3063 static void
3064 intel_dp_connector_destroy(struct drm_connector *connector)
3065 {
3066 struct intel_connector *intel_connector = to_intel_connector(connector);
3067
3068 if (!IS_ERR_OR_NULL(intel_connector->edid))
3069 kfree(intel_connector->edid);
3070
3071 /* Can't call is_edp() since the encoder may have been destroyed
3072 * already. */
3073 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3074 intel_panel_fini(&intel_connector->panel);
3075
3076 drm_sysfs_connector_remove(connector);
3077 drm_connector_cleanup(connector);
3078 kfree(connector);
3079 }
3080
3081 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3082 {
3083 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3084 struct intel_dp *intel_dp = &intel_dig_port->dp;
3085 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3086
3087 i2c_del_adapter(&intel_dp->adapter);
3088 drm_encoder_cleanup(encoder);
3089 if (is_edp(intel_dp)) {
3090 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3091 mutex_lock(&dev->mode_config.mutex);
3092 ironlake_panel_vdd_off_sync(intel_dp);
3093 mutex_unlock(&dev->mode_config.mutex);
3094 }
3095 kfree(intel_dig_port);
3096 }
3097
3098 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3099 .dpms = intel_connector_dpms,
3100 .detect = intel_dp_detect,
3101 .fill_modes = drm_helper_probe_single_connector_modes,
3102 .set_property = intel_dp_set_property,
3103 .destroy = intel_dp_connector_destroy,
3104 };
3105
3106 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3107 .get_modes = intel_dp_get_modes,
3108 .mode_valid = intel_dp_mode_valid,
3109 .best_encoder = intel_best_encoder,
3110 };
3111
3112 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3113 .destroy = intel_dp_encoder_destroy,
3114 };
3115
3116 static void
3117 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3118 {
3119 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3120
3121 intel_dp_check_link_status(intel_dp);
3122 }
3123
3124 /* Return which DP Port should be selected for Transcoder DP control */
3125 int
3126 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3127 {
3128 struct drm_device *dev = crtc->dev;
3129 struct intel_encoder *intel_encoder;
3130 struct intel_dp *intel_dp;
3131
3132 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3133 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3134
3135 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3136 intel_encoder->type == INTEL_OUTPUT_EDP)
3137 return intel_dp->output_reg;
3138 }
3139
3140 return -1;
3141 }
3142
3143 /* check the VBT to see whether the eDP is on DP-D port */
3144 bool intel_dpd_is_edp(struct drm_device *dev)
3145 {
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 struct child_device_config *p_child;
3148 int i;
3149
3150 if (!dev_priv->vbt.child_dev_num)
3151 return false;
3152
3153 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3154 p_child = dev_priv->vbt.child_dev + i;
3155
3156 if (p_child->dvo_port == PORT_IDPD &&
3157 p_child->device_type == DEVICE_TYPE_eDP)
3158 return true;
3159 }
3160 return false;
3161 }
3162
3163 static void
3164 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3165 {
3166 struct intel_connector *intel_connector = to_intel_connector(connector);
3167
3168 intel_attach_force_audio_property(connector);
3169 intel_attach_broadcast_rgb_property(connector);
3170 intel_dp->color_range_auto = true;
3171
3172 if (is_edp(intel_dp)) {
3173 drm_mode_create_scaling_mode_property(connector->dev);
3174 drm_object_attach_property(
3175 &connector->base,
3176 connector->dev->mode_config.scaling_mode_property,
3177 DRM_MODE_SCALE_ASPECT);
3178 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3179 }
3180 }
3181
3182 static void
3183 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3184 struct intel_dp *intel_dp,
3185 struct edp_power_seq *out)
3186 {
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct edp_power_seq cur, vbt, spec, final;
3189 u32 pp_on, pp_off, pp_div, pp;
3190 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3191
3192 if (HAS_PCH_SPLIT(dev)) {
3193 pp_control_reg = PCH_PP_CONTROL;
3194 pp_on_reg = PCH_PP_ON_DELAYS;
3195 pp_off_reg = PCH_PP_OFF_DELAYS;
3196 pp_div_reg = PCH_PP_DIVISOR;
3197 } else {
3198 pp_control_reg = PIPEA_PP_CONTROL;
3199 pp_on_reg = PIPEA_PP_ON_DELAYS;
3200 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3201 pp_div_reg = PIPEA_PP_DIVISOR;
3202 }
3203
3204 /* Workaround: Need to write PP_CONTROL with the unlock key as
3205 * the very first thing. */
3206 pp = ironlake_get_pp_control(intel_dp);
3207 I915_WRITE(pp_control_reg, pp);
3208
3209 pp_on = I915_READ(pp_on_reg);
3210 pp_off = I915_READ(pp_off_reg);
3211 pp_div = I915_READ(pp_div_reg);
3212
3213 /* Pull timing values out of registers */
3214 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3215 PANEL_POWER_UP_DELAY_SHIFT;
3216
3217 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3218 PANEL_LIGHT_ON_DELAY_SHIFT;
3219
3220 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3221 PANEL_LIGHT_OFF_DELAY_SHIFT;
3222
3223 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3224 PANEL_POWER_DOWN_DELAY_SHIFT;
3225
3226 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3227 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3228
3229 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3230 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3231
3232 vbt = dev_priv->vbt.edp_pps;
3233
3234 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3235 * our hw here, which are all in 100usec. */
3236 spec.t1_t3 = 210 * 10;
3237 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3238 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3239 spec.t10 = 500 * 10;
3240 /* This one is special and actually in units of 100ms, but zero
3241 * based in the hw (so we need to add 100 ms). But the sw vbt
3242 * table multiplies it with 1000 to make it in units of 100usec,
3243 * too. */
3244 spec.t11_t12 = (510 + 100) * 10;
3245
3246 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3247 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3248
3249 /* Use the max of the register settings and vbt. If both are
3250 * unset, fall back to the spec limits. */
3251 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3252 spec.field : \
3253 max(cur.field, vbt.field))
3254 assign_final(t1_t3);
3255 assign_final(t8);
3256 assign_final(t9);
3257 assign_final(t10);
3258 assign_final(t11_t12);
3259 #undef assign_final
3260
3261 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3262 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3263 intel_dp->backlight_on_delay = get_delay(t8);
3264 intel_dp->backlight_off_delay = get_delay(t9);
3265 intel_dp->panel_power_down_delay = get_delay(t10);
3266 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3267 #undef get_delay
3268
3269 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3270 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3271 intel_dp->panel_power_cycle_delay);
3272
3273 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3274 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3275
3276 if (out)
3277 *out = final;
3278 }
3279
3280 static void
3281 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3282 struct intel_dp *intel_dp,
3283 struct edp_power_seq *seq)
3284 {
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286 u32 pp_on, pp_off, pp_div, port_sel = 0;
3287 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3288 int pp_on_reg, pp_off_reg, pp_div_reg;
3289
3290 if (HAS_PCH_SPLIT(dev)) {
3291 pp_on_reg = PCH_PP_ON_DELAYS;
3292 pp_off_reg = PCH_PP_OFF_DELAYS;
3293 pp_div_reg = PCH_PP_DIVISOR;
3294 } else {
3295 pp_on_reg = PIPEA_PP_ON_DELAYS;
3296 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3297 pp_div_reg = PIPEA_PP_DIVISOR;
3298 }
3299
3300 /* And finally store the new values in the power sequencer. */
3301 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3302 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3303 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3304 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3305 /* Compute the divisor for the pp clock, simply match the Bspec
3306 * formula. */
3307 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3308 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3309 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3310
3311 /* Haswell doesn't have any port selection bits for the panel
3312 * power sequencer any more. */
3313 if (IS_VALLEYVIEW(dev)) {
3314 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3315 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3316 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3317 port_sel = PANEL_POWER_PORT_DP_A;
3318 else
3319 port_sel = PANEL_POWER_PORT_DP_D;
3320 }
3321
3322 pp_on |= port_sel;
3323
3324 I915_WRITE(pp_on_reg, pp_on);
3325 I915_WRITE(pp_off_reg, pp_off);
3326 I915_WRITE(pp_div_reg, pp_div);
3327
3328 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3329 I915_READ(pp_on_reg),
3330 I915_READ(pp_off_reg),
3331 I915_READ(pp_div_reg));
3332 }
3333
3334 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3335 struct intel_connector *intel_connector)
3336 {
3337 struct drm_connector *connector = &intel_connector->base;
3338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3339 struct drm_device *dev = intel_dig_port->base.base.dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct drm_display_mode *fixed_mode = NULL;
3342 struct edp_power_seq power_seq = { 0 };
3343 bool has_dpcd;
3344 struct drm_display_mode *scan;
3345 struct edid *edid;
3346
3347 if (!is_edp(intel_dp))
3348 return true;
3349
3350 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3351
3352 /* Cache DPCD and EDID for edp. */
3353 ironlake_edp_panel_vdd_on(intel_dp);
3354 has_dpcd = intel_dp_get_dpcd(intel_dp);
3355 ironlake_edp_panel_vdd_off(intel_dp, false);
3356
3357 if (has_dpcd) {
3358 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3359 dev_priv->no_aux_handshake =
3360 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3361 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3362 } else {
3363 /* if this fails, presume the device is a ghost */
3364 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3365 return false;
3366 }
3367
3368 /* We now know it's not a ghost, init power sequence regs. */
3369 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3370 &power_seq);
3371
3372 ironlake_edp_panel_vdd_on(intel_dp);
3373 edid = drm_get_edid(connector, &intel_dp->adapter);
3374 if (edid) {
3375 if (drm_add_edid_modes(connector, edid)) {
3376 drm_mode_connector_update_edid_property(connector,
3377 edid);
3378 drm_edid_to_eld(connector, edid);
3379 } else {
3380 kfree(edid);
3381 edid = ERR_PTR(-EINVAL);
3382 }
3383 } else {
3384 edid = ERR_PTR(-ENOENT);
3385 }
3386 intel_connector->edid = edid;
3387
3388 /* prefer fixed mode from EDID if available */
3389 list_for_each_entry(scan, &connector->probed_modes, head) {
3390 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3391 fixed_mode = drm_mode_duplicate(dev, scan);
3392 break;
3393 }
3394 }
3395
3396 /* fallback to VBT if available for eDP */
3397 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3398 fixed_mode = drm_mode_duplicate(dev,
3399 dev_priv->vbt.lfp_lvds_vbt_mode);
3400 if (fixed_mode)
3401 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3402 }
3403
3404 ironlake_edp_panel_vdd_off(intel_dp, false);
3405
3406 intel_panel_init(&intel_connector->panel, fixed_mode);
3407 intel_panel_setup_backlight(connector);
3408
3409 return true;
3410 }
3411
3412 bool
3413 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3414 struct intel_connector *intel_connector)
3415 {
3416 struct drm_connector *connector = &intel_connector->base;
3417 struct intel_dp *intel_dp = &intel_dig_port->dp;
3418 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3419 struct drm_device *dev = intel_encoder->base.dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 enum port port = intel_dig_port->port;
3422 const char *name = NULL;
3423 int type, error;
3424
3425 /* Preserve the current hw state. */
3426 intel_dp->DP = I915_READ(intel_dp->output_reg);
3427 intel_dp->attached_connector = intel_connector;
3428
3429 type = DRM_MODE_CONNECTOR_DisplayPort;
3430 /*
3431 * FIXME : We need to initialize built-in panels before external panels.
3432 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3433 */
3434 switch (port) {
3435 case PORT_A:
3436 type = DRM_MODE_CONNECTOR_eDP;
3437 break;
3438 case PORT_C:
3439 if (IS_VALLEYVIEW(dev))
3440 type = DRM_MODE_CONNECTOR_eDP;
3441 break;
3442 case PORT_D:
3443 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3444 type = DRM_MODE_CONNECTOR_eDP;
3445 break;
3446 default: /* silence GCC warning */
3447 break;
3448 }
3449
3450 /*
3451 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3452 * for DP the encoder type can be set by the caller to
3453 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3454 */
3455 if (type == DRM_MODE_CONNECTOR_eDP)
3456 intel_encoder->type = INTEL_OUTPUT_EDP;
3457
3458 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3459 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3460 port_name(port));
3461
3462 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3463 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3464
3465 connector->interlace_allowed = true;
3466 connector->doublescan_allowed = 0;
3467
3468 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3469 ironlake_panel_vdd_work);
3470
3471 intel_connector_attach_encoder(intel_connector, intel_encoder);
3472 drm_sysfs_connector_add(connector);
3473
3474 if (HAS_DDI(dev))
3475 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3476 else
3477 intel_connector->get_hw_state = intel_connector_get_hw_state;
3478
3479 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3480 if (HAS_DDI(dev)) {
3481 switch (intel_dig_port->port) {
3482 case PORT_A:
3483 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3484 break;
3485 case PORT_B:
3486 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3487 break;
3488 case PORT_C:
3489 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3490 break;
3491 case PORT_D:
3492 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3493 break;
3494 default:
3495 BUG();
3496 }
3497 }
3498
3499 /* Set up the DDC bus. */
3500 switch (port) {
3501 case PORT_A:
3502 intel_encoder->hpd_pin = HPD_PORT_A;
3503 name = "DPDDC-A";
3504 break;
3505 case PORT_B:
3506 intel_encoder->hpd_pin = HPD_PORT_B;
3507 name = "DPDDC-B";
3508 break;
3509 case PORT_C:
3510 intel_encoder->hpd_pin = HPD_PORT_C;
3511 name = "DPDDC-C";
3512 break;
3513 case PORT_D:
3514 intel_encoder->hpd_pin = HPD_PORT_D;
3515 name = "DPDDC-D";
3516 break;
3517 default:
3518 BUG();
3519 }
3520
3521 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3522 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3523 error, port_name(port));
3524
3525 intel_dp->psr_setup_done = false;
3526
3527 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3528 i2c_del_adapter(&intel_dp->adapter);
3529 if (is_edp(intel_dp)) {
3530 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3531 mutex_lock(&dev->mode_config.mutex);
3532 ironlake_panel_vdd_off_sync(intel_dp);
3533 mutex_unlock(&dev->mode_config.mutex);
3534 }
3535 drm_sysfs_connector_remove(connector);
3536 drm_connector_cleanup(connector);
3537 return false;
3538 }
3539
3540 intel_dp_add_properties(intel_dp, connector);
3541
3542 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3543 * 0xd. Failure to do so will result in spurious interrupts being
3544 * generated on the port when a cable is not attached.
3545 */
3546 if (IS_G4X(dev) && !IS_GM45(dev)) {
3547 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3548 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3549 }
3550
3551 return true;
3552 }
3553
3554 void
3555 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3556 {
3557 struct intel_digital_port *intel_dig_port;
3558 struct intel_encoder *intel_encoder;
3559 struct drm_encoder *encoder;
3560 struct intel_connector *intel_connector;
3561
3562 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3563 if (!intel_dig_port)
3564 return;
3565
3566 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3567 if (!intel_connector) {
3568 kfree(intel_dig_port);
3569 return;
3570 }
3571
3572 intel_encoder = &intel_dig_port->base;
3573 encoder = &intel_encoder->base;
3574
3575 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3576 DRM_MODE_ENCODER_TMDS);
3577
3578 intel_encoder->compute_config = intel_dp_compute_config;
3579 intel_encoder->mode_set = intel_dp_mode_set;
3580 intel_encoder->disable = intel_disable_dp;
3581 intel_encoder->post_disable = intel_post_disable_dp;
3582 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3583 intel_encoder->get_config = intel_dp_get_config;
3584 if (IS_VALLEYVIEW(dev)) {
3585 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3586 intel_encoder->pre_enable = vlv_pre_enable_dp;
3587 intel_encoder->enable = vlv_enable_dp;
3588 } else {
3589 intel_encoder->pre_enable = intel_pre_enable_dp;
3590 intel_encoder->enable = intel_enable_dp;
3591 }
3592
3593 intel_dig_port->port = port;
3594 intel_dig_port->dp.output_reg = output_reg;
3595
3596 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3597 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3598 intel_encoder->cloneable = false;
3599 intel_encoder->hot_plug = intel_dp_hot_plug;
3600
3601 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3602 drm_encoder_cleanup(encoder);
3603 kfree(intel_dig_port);
3604 kfree(intel_connector);
3605 }
3606 }
Linux with added FPC-III support