drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 struct gmbus_port {
  38         const char *name;
  39         int reg;
  40 };
  41
  42 static const struct gmbus_port gmbus_ports[] = {
  43         { "ssc", GPIOB },
  44         { "vga", GPIOA },
  45         { "panel", GPIOC },
  46         { "dpc", GPIOD },
  47         { "dpb", GPIOE },
  48         { "dpd", GPIOF },
  49 };
  50
  51 /* Intel GPIO access functions */
  52
  53 #define I2C_RISEFALL_TIME 10
  54
  55 static inline struct intel_gmbus *
  56 to_intel_gmbus(struct i2c_adapter *i2c)
  57 {
  58         return container_of(i2c, struct intel_gmbus, adapter);
  59 }
  60
  61 void
  62 intel_i2c_reset(struct drm_device *dev)
  63 {
  64         struct drm_i915_private *dev_priv = dev->dev_private;
  65         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
  66         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
  67 }
  68
  69 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  70 {
  71         u32 val;
  72
  73         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  74         if (!IS_PINEVIEW(dev_priv->dev))
  75                 return;
  76
  77         val = I915_READ(DSPCLK_GATE_D);
  78         if (enable)
  79                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  80         else
  81                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  82         I915_WRITE(DSPCLK_GATE_D, val);
  83 }
  84
  85 static u32 get_reserved(struct intel_gmbus *bus)
  86 {
  87         struct drm_i915_private *dev_priv = bus->dev_priv;
  88         struct drm_device *dev = dev_priv->dev;
  89         u32 reserved = 0;
  90
  91         /* On most chips, these bits must be preserved in software. */
  92         if (!IS_I830(dev) && !IS_845G(dev))
  93                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
  94                                              (GPIO_DATA_PULLUP_DISABLE |
  95                                               GPIO_CLOCK_PULLUP_DISABLE);
  96
  97         return reserved;
  98 }
  99
 100 static int get_clock(void *data)
 101 {
 102         struct intel_gmbus *bus = data;
 103         struct drm_i915_private *dev_priv = bus->dev_priv;
 104         u32 reserved = get_reserved(bus);
 105         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 106         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 107         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 108 }
 109
 110 static int get_data(void *data)
 111 {
 112         struct intel_gmbus *bus = data;
 113         struct drm_i915_private *dev_priv = bus->dev_priv;
 114         u32 reserved = get_reserved(bus);
 115         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 116         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 117         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 118 }
 119
 120 static void set_clock(void *data, int state_high)
 121 {
 122         struct intel_gmbus *bus = data;
 123         struct drm_i915_private *dev_priv = bus->dev_priv;
 124         u32 reserved = get_reserved(bus);
 125         u32 clock_bits;
 126
 127         if (state_high)
 128                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 129         else
 130                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 131                         GPIO_CLOCK_VAL_MASK;
 132
 133         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 134         POSTING_READ(bus->gpio_reg);
 135 }
 136
 137 static void set_data(void *data, int state_high)
 138 {
 139         struct intel_gmbus *bus = data;
 140         struct drm_i915_private *dev_priv = bus->dev_priv;
 141         u32 reserved = get_reserved(bus);
 142         u32 data_bits;
 143
 144         if (state_high)
 145                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 146         else
 147                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 148                         GPIO_DATA_VAL_MASK;
 149
 150         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 151         POSTING_READ(bus->gpio_reg);
 152 }
 153
 154 static int
 155 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 156 {
 157         struct intel_gmbus *bus = container_of(adapter,
 158                                                struct intel_gmbus,
 159                                                adapter);
 160         struct drm_i915_private *dev_priv = bus->dev_priv;
 161
 162         intel_i2c_reset(dev_priv->dev);
 163         intel_i2c_quirk_set(dev_priv, true);
 164         set_data(bus, 1);
 165         set_clock(bus, 1);
 166         udelay(I2C_RISEFALL_TIME);
 167         return 0;
 168 }
 169
 170 static void
 171 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 172 {
 173         struct intel_gmbus *bus = container_of(adapter,
 174                                                struct intel_gmbus,
 175                                                adapter);
 176         struct drm_i915_private *dev_priv = bus->dev_priv;
 177
 178         set_data(bus, 1);
 179         set_clock(bus, 1);
 180         intel_i2c_quirk_set(dev_priv, false);
 181 }
 182
 183 static void
 184 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
 185 {
 186         struct drm_i915_private *dev_priv = bus->dev_priv;
 187         struct i2c_algo_bit_data *algo;
 188
 189         algo = &bus->bit_algo;
 190
 191         /* -1 to map pin pair to gmbus index */
 192         bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
 193
 194         bus->adapter.algo_data = algo;
 195         algo->setsda = set_data;
 196         algo->setscl = set_clock;
 197         algo->getsda = get_data;
 198         algo->getscl = get_clock;
 199         algo->pre_xfer = intel_gpio_pre_xfer;
 200         algo->post_xfer = intel_gpio_post_xfer;
 201         algo->udelay = I2C_RISEFALL_TIME;
 202         algo->timeout = usecs_to_jiffies(2200);
 203         algo->data = bus;
 204 }
 205
 206 /*
 207  * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
 208  * mode. This results in spurious interrupt warnings if the legacy irq no. is
 209  * shared with another device. The kernel then disables that interrupt source
 210  * and so prevents the other device from working properly.
 211  */
 212 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
 213 static int
 214 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 215                      u32 gmbus2_status,
 216                      u32 gmbus4_irq_en)
 217 {
 218         int i;
 219         int reg_offset = dev_priv->gpio_mmio_base;
 220         u32 gmbus2 = 0;
 221         DEFINE_WAIT(wait);
 222
 223         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 224                 gmbus4_irq_en = 0;
 225
 226         /* Important: The hw handles only the first bit, so set only one! Since
 227          * we also need to check for NAKs besides the hw ready/idle signal, we
 228          * need to wake up periodically and check that ourselves. */
 229         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 230
 231         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 232                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 233                                 TASK_UNINTERRUPTIBLE);
 234
 235                 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
 236                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 237                         break;
 238
 239                 schedule_timeout(1);
 240         }
 241         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 242
 243         I915_WRITE(GMBUS4 + reg_offset, 0);
 244
 245         if (gmbus2 & GMBUS_SATOER)
 246                 return -ENXIO;
 247         if (gmbus2 & gmbus2_status)
 248                 return 0;
 249         return -ETIMEDOUT;
 250 }
 251
 252 static int
 253 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 254 {
 255         int ret;
 256         int reg_offset = dev_priv->gpio_mmio_base;
 257
 258 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
 259
 260         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 261                 return wait_for(C, 10);
 262
 263         /* Important: The hw handles only the first bit, so set only one! */
 264         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
 265
 266         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 267                                  msecs_to_jiffies_timeout(10));
 268
 269         I915_WRITE(GMBUS4 + reg_offset, 0);
 270
 271         if (ret)
 272                 return 0;
 273         else
 274                 return -ETIMEDOUT;
 275 #undef C
 276 }
 277
 278 static int
 279 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 280                 u32 gmbus1_index)
 281 {
 282         int reg_offset = dev_priv->gpio_mmio_base;
 283         u16 len = msg->len;
 284         u8 *buf = msg->buf;
 285
 286         I915_WRITE(GMBUS1 + reg_offset,
 287                    gmbus1_index |
 288                    GMBUS_CYCLE_WAIT |
 289                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 290                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 291                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 292         while (len) {
 293                 int ret;
 294                 u32 val, loop = 0;
 295
 296                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 297                                            GMBUS_HW_RDY_EN);
 298                 if (ret)
 299                         return ret;
 300
 301                 val = I915_READ(GMBUS3 + reg_offset);
 302                 do {
 303                         *buf++ = val & 0xff;
 304                         val >>= 8;
 305                 } while (--len && ++loop < 4);
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int
 312 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 313 {
 314         int reg_offset = dev_priv->gpio_mmio_base;
 315         u16 len = msg->len;
 316         u8 *buf = msg->buf;
 317         u32 val, loop;
 318
 319         val = loop = 0;
 320         while (len && loop < 4) {
 321                 val |= *buf++ << (8 * loop++);
 322                 len -= 1;
 323         }
 324
 325         I915_WRITE(GMBUS3 + reg_offset, val);
 326         I915_WRITE(GMBUS1 + reg_offset,
 327                    GMBUS_CYCLE_WAIT |
 328                    (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
 329                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 330                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 331         while (len) {
 332                 int ret;
 333
 334                 val = loop = 0;
 335                 do {
 336                         val |= *buf++ << (8 * loop);
 337                 } while (--len && ++loop < 4);
 338
 339                 I915_WRITE(GMBUS3 + reg_offset, val);
 340
 341                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 342                                            GMBUS_HW_RDY_EN);
 343                 if (ret)
 344                         return ret;
 345         }
 346         return 0;
 347 }
 348
 349 /*
 350  * The gmbus controller can combine a 1 or 2 byte write with a read that
 351  * immediately follows it by using an "INDEX" cycle.
 352  */
 353 static bool
 354 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 355 {
 356         return (i + 1 < num &&
 357                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
 358                 (msgs[i + 1].flags & I2C_M_RD));
 359 }
 360
 361 static int
 362 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 363 {
 364         int reg_offset = dev_priv->gpio_mmio_base;
 365         u32 gmbus1_index = 0;
 366         u32 gmbus5 = 0;
 367         int ret;
 368
 369         if (msgs[0].len == 2)
 370                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 371                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 372         if (msgs[0].len == 1)
 373                 gmbus1_index = GMBUS_CYCLE_INDEX |
 374                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 375
 376         /* GMBUS5 holds 16-bit index */
 377         if (gmbus5)
 378                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
 379
 380         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 381
 382         /* Clear GMBUS5 after each index transfer */
 383         if (gmbus5)
 384                 I915_WRITE(GMBUS5 + reg_offset, 0);
 385
 386         return ret;
 387 }
 388
 389 static int
 390 gmbus_xfer(struct i2c_adapter *adapter,
 391            struct i2c_msg *msgs,
 392            int num)
 393 {
 394         struct intel_gmbus *bus = container_of(adapter,
 395                                                struct intel_gmbus,
 396                                                adapter);
 397         struct drm_i915_private *dev_priv = bus->dev_priv;
 398         int i, reg_offset;
 399         int ret = 0;
 400
 401         intel_aux_display_runtime_get(dev_priv);
 402         mutex_lock(&dev_priv->gmbus_mutex);
 403
 404         if (bus->force_bit) {
 405                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 406                 goto out;
 407         }
 408
 409         reg_offset = dev_priv->gpio_mmio_base;
 410
 411         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 412
 413         for (i = 0; i < num; i++) {
 414                 if (gmbus_is_index_read(msgs, i, num)) {
 415                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 416                         i += 1;  /* set i to the index of the read xfer */
 417                 } else if (msgs[i].flags & I2C_M_RD) {
 418                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 419                 } else {
 420                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 421                 }
 422
 423                 if (ret == -ETIMEDOUT)
 424                         goto timeout;
 425                 if (ret == -ENXIO)
 426                         goto clear_err;
 427
 428                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
 429                                            GMBUS_HW_WAIT_EN);
 430                 if (ret == -ENXIO)
 431                         goto clear_err;
 432                 if (ret)
 433                         goto timeout;
 434         }
 435
 436         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 437          * a STOP on the very first cycle. To simplify the code we
 438          * unconditionally generate the STOP condition with an additional gmbus
 439          * cycle. */
 440         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 441
 442         /* Mark the GMBUS interface as disabled after waiting for idle.
 443          * We will re-enable it at the start of the next xfer,
 444          * till then let it sleep.
 445          */
 446         if (gmbus_wait_idle(dev_priv)) {
 447                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 448                          adapter->name);
 449                 ret = -ETIMEDOUT;
 450         }
 451         I915_WRITE(GMBUS0 + reg_offset, 0);
 452         ret = ret ?: i;
 453         goto out;
 454
 455 clear_err:
 456         /*
 457          * Wait for bus to IDLE before clearing NAK.
 458          * If we clear the NAK while bus is still active, then it will stay
 459          * active and the next transaction may fail.
 460          *
 461          * If no ACK is received during the address phase of a transaction, the
 462          * adapter must report -ENXIO. It is not clear what to return if no ACK
 463          * is received at other times. But we have to be careful to not return
 464          * spurious -ENXIO because that will prevent i2c and drm edid functions
 465          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 466          * timing out seems to happen when there _is_ a ddc chip present, but
 467          * it's slow responding and only answers on the 2nd retry.
 468          */
 469         ret = -ENXIO;
 470         if (gmbus_wait_idle(dev_priv)) {
 471                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 472                               adapter->name);
 473                 ret = -ETIMEDOUT;
 474         }
 475
 476         /* Toggle the Software Clear Interrupt bit. This has the effect
 477          * of resetting the GMBUS controller and so clearing the
 478          * BUS_ERROR raised by the slave's NAK.
 479          */
 480         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 481         I915_WRITE(GMBUS1 + reg_offset, 0);
 482         I915_WRITE(GMBUS0 + reg_offset, 0);
 483
 484         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 485                          adapter->name, msgs[i].addr,
 486                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 487
 488         goto out;
 489
 490 timeout:
 491         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 492                  bus->adapter.name, bus->reg0 & 0xff);
 493         I915_WRITE(GMBUS0 + reg_offset, 0);
 494
 495         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 496         bus->force_bit = 1;
 497         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 498
 499 out:
 500         mutex_unlock(&dev_priv->gmbus_mutex);
 501         intel_aux_display_runtime_put(dev_priv);
 502         return ret;
 503 }
 504
 505 static u32 gmbus_func(struct i2c_adapter *adapter)
 506 {
 507         return i2c_bit_algo.functionality(adapter) &
 508                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 509                 /* I2C_FUNC_10BIT_ADDR | */
 510                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 511                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 512 }
 513
 514 static const struct i2c_algorithm gmbus_algorithm = {
 515         .master_xfer    = gmbus_xfer,
 516         .functionality  = gmbus_func
 517 };
 518
 519 /**
 520  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 521  * @dev: DRM device
 522  */
 523 int intel_setup_gmbus(struct drm_device *dev)
 524 {
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         int ret, i;
 527
 528         if (HAS_PCH_NOP(dev))
 529                 return 0;
 530         else if (HAS_PCH_SPLIT(dev))
 531                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 532         else if (IS_VALLEYVIEW(dev))
 533                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 534         else
 535                 dev_priv->gpio_mmio_base = 0;
 536
 537         mutex_init(&dev_priv->gmbus_mutex);
 538         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 539
 540         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 541                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 542                 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
 543
 544                 bus->adapter.owner = THIS_MODULE;
 545                 bus->adapter.class = I2C_CLASS_DDC;
 546                 snprintf(bus->adapter.name,
 547                          sizeof(bus->adapter.name),
 548                          "i915 gmbus %s",
 549                          gmbus_ports[i].name);
 550
 551                 bus->adapter.dev.parent = &dev->pdev->dev;
 552                 bus->dev_priv = dev_priv;
 553
 554                 bus->adapter.algo = &gmbus_algorithm;
 555
 556                 /* By default use a conservative clock rate */
 557                 bus->reg0 = port | GMBUS_RATE_100KHZ;
 558
 559                 /* gmbus seems to be broken on i830 */
 560                 if (IS_I830(dev))
 561                         bus->force_bit = 1;
 562
 563                 intel_gpio_setup(bus, port);
 564
 565                 ret = i2c_add_adapter(&bus->adapter);
 566                 if (ret)
 567                         goto err;
 568         }
 569
 570         intel_i2c_reset(dev_priv->dev);
 571
 572         return 0;
 573
 574 err:
 575         while (--i) {
 576                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 577                 i2c_del_adapter(&bus->adapter);
 578         }
 579         return ret;
 580 }
 581
 582 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 583                                             unsigned port)
 584 {
 585         WARN_ON(!intel_gmbus_is_port_valid(port));
 586         /* -1 to map pin pair to gmbus index */
 587         return (intel_gmbus_is_port_valid(port)) ?
 588                 &dev_priv->gmbus[port - 1].adapter : NULL;
 589 }
 590
 591 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 592 {
 593         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 594
 595         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 596 }
 597
 598 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 599 {
 600         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 601
 602         bus->force_bit += force_bit ? 1 : -1;
 603         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
 604                       force_bit ? "en" : "dis", adapter->name,
 605                       bus->force_bit);
 606 }
 607
 608 void intel_teardown_gmbus(struct drm_device *dev)
 609 {
 610         struct drm_i915_private *dev_priv = dev->dev_private;
 611         int i;
 612
 613         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 614                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 615                 i2c_del_adapter(&bus->adapter);
 616         }
 617 }