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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_sdvo.c
blob49482fd5b76c6cad80298d2d2f67c0050c73a93d
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39
40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
44
45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
50 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
51 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
53
54
55 static const char *tv_format_names[] = {
56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63 };
64
65 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
67 struct intel_sdvo {
68 struct intel_encoder base;
69
70 struct i2c_adapter *i2c;
71 u8 slave_addr;
72
73 struct i2c_adapter ddc;
74
75 /* Register for the SDVO device: SDVOB or SDVOC */
76 uint32_t sdvo_reg;
77
78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
80
81 /*
82 * Capabilities of the SDVO device returned by
83 * intel_sdvo_get_capabilities()
84 */
85 struct intel_sdvo_caps caps;
86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
88 int pixel_clock_min, pixel_clock_max;
89
90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
96 /*
97 * Hotplug activation bits for this device
98 */
99 uint16_t hotplug_active;
100
101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
106 bool color_range_auto;
107
108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
120 /* This is for current tv format name */
121 int tv_format_index;
122
123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
129 bool rgb_quant_range_selectable;
130
131 /**
132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
134 */
135 bool is_lvds;
136
137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
142 /* DDC bus used by this SDVO encoder */
143 uint8_t ddc_bus;
144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
149 };
150
151 struct intel_sdvo_connector {
152 struct intel_connector base;
153
154 /* Mark the type of connector */
155 uint16_t output_flag;
156
157 enum hdmi_force_audio force_audio;
158
159 /* This contains all current supported TV format */
160 u8 tv_format_supported[TV_FORMAT_NUM];
161 int format_supported_num;
162 struct drm_property *tv_format;
163
164 /* add the property for the SDVO-TV */
165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
180 struct drm_property *dot_crawl;
181
182 /* add the property for the SDVO-TV/LVDS */
183 struct drm_property *brightness;
184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
187
188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
202 u32 cur_dot_crawl, max_dot_crawl;
203 };
204
205 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
206 {
207 return container_of(encoder, struct intel_sdvo, base);
208 }
209
210 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211 {
212 return to_sdvo(intel_attached_encoder(connector));
213 }
214
215 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216 {
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218 }
219
220 static bool
221 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
222 static bool
223 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226 static bool
227 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
229
230 /**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
235 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
236 {
237 struct drm_device *dev = intel_sdvo->base.base.dev;
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 bval = val, cval = val;
240 int i;
241
242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
243 I915_WRITE(intel_sdvo->sdvo_reg, val);
244 I915_READ(intel_sdvo->sdvo_reg);
245 return;
246 }
247
248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
249 cval = I915_READ(GEN3_SDVOC);
250 else
251 bval = I915_READ(GEN3_SDVOB);
252
253 /*
254 * Write the registers twice for luck. Sometimes,
255 * writing them only once doesn't appear to 'stick'.
256 * The BIOS does this too. Yay, magic
257 */
258 for (i = 0; i < 2; i++)
259 {
260 I915_WRITE(GEN3_SDVOB, bval);
261 I915_READ(GEN3_SDVOB);
262 I915_WRITE(GEN3_SDVOC, cval);
263 I915_READ(GEN3_SDVOC);
264 }
265 }
266
267 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
268 {
269 struct i2c_msg msgs[] = {
270 {
271 .addr = intel_sdvo->slave_addr,
272 .flags = 0,
273 .len = 1,
274 .buf = &addr,
275 },
276 {
277 .addr = intel_sdvo->slave_addr,
278 .flags = I2C_M_RD,
279 .len = 1,
280 .buf = ch,
281 }
282 };
283 int ret;
284
285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
286 return true;
287
288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
289 return false;
290 }
291
292 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293 /** Mapping of command numbers to names, for debug output */
294 static const struct _sdvo_cmd_name {
295 u8 cmd;
296 const char *name;
297 } sdvo_cmd_names[] = {
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
341
342 /* Add the op code for SDVO enhancements */
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
409 };
410
411 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
412
413 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
414 const void *args, int args_len)
415 {
416 int i;
417
418 DRM_DEBUG_KMS("%s: W: %02X ",
419 SDVO_NAME(intel_sdvo), cmd);
420 for (i = 0; i < args_len; i++)
421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
422 for (; i < 8; i++)
423 DRM_LOG_KMS(" ");
424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
425 if (cmd == sdvo_cmd_names[i].cmd) {
426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
427 break;
428 }
429 }
430 if (i == ARRAY_SIZE(sdvo_cmd_names))
431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
433 }
434
435 static const char *cmd_status_names[] = {
436 "Power on",
437 "Success",
438 "Not supported",
439 "Invalid arg",
440 "Pending",
441 "Target not specified",
442 "Scaling not supported"
443 };
444
445 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
446 const void *args, int args_len)
447 {
448 u8 *buf, status;
449 struct i2c_msg *msgs;
450 int i, ret = true;
451
452 /* Would be simpler to allocate both in one go ? */
453 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
454 if (!buf)
455 return false;
456
457 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
458 if (!msgs) {
459 kfree(buf);
460 return false;
461 }
462
463 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
464
465 for (i = 0; i < args_len; i++) {
466 msgs[i].addr = intel_sdvo->slave_addr;
467 msgs[i].flags = 0;
468 msgs[i].len = 2;
469 msgs[i].buf = buf + 2 *i;
470 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
471 buf[2*i + 1] = ((u8*)args)[i];
472 }
473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2*i;
477 buf[2*i + 0] = SDVO_I2C_OPCODE;
478 buf[2*i + 1] = cmd;
479
480 /* the following two are to read the response */
481 status = SDVO_I2C_CMD_STATUS;
482 msgs[i+1].addr = intel_sdvo->slave_addr;
483 msgs[i+1].flags = 0;
484 msgs[i+1].len = 1;
485 msgs[i+1].buf = &status;
486
487 msgs[i+2].addr = intel_sdvo->slave_addr;
488 msgs[i+2].flags = I2C_M_RD;
489 msgs[i+2].len = 1;
490 msgs[i+2].buf = &status;
491
492 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
493 if (ret < 0) {
494 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
495 ret = false;
496 goto out;
497 }
498 if (ret != i+3) {
499 /* failure in I2C transfer */
500 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
501 ret = false;
502 }
503
504 out:
505 kfree(msgs);
506 kfree(buf);
507 return ret;
508 }
509
510 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
511 void *response, int response_len)
512 {
513 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
514 u8 status;
515 int i;
516
517 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
518
519 /*
520 * The documentation states that all commands will be
521 * processed within 15µs, and that we need only poll
522 * the status byte a maximum of 3 times in order for the
523 * command to be complete.
524 *
525 * Check 5 times in case the hardware failed to read the docs.
526 *
527 * Also beware that the first response by many devices is to
528 * reply PENDING and stall for time. TVs are notorious for
529 * requiring longer than specified to complete their replies.
530 * Originally (in the DDX long ago), the delay was only ever 15ms
531 * with an additional delay of 30ms applied for TVs added later after
532 * many experiments. To accommodate both sets of delays, we do a
533 * sequence of slow checks if the device is falling behind and fails
534 * to reply within 5*15µs.
535 */
536 if (!intel_sdvo_read_byte(intel_sdvo,
537 SDVO_I2C_CMD_STATUS,
538 &status))
539 goto log_fail;
540
541 while ((status == SDVO_CMD_STATUS_PENDING ||
542 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
551 goto log_fail;
552 }
553
554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
556 else
557 DRM_LOG_KMS("(??? %d)", status);
558
559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
561
562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
569 }
570 DRM_LOG_KMS("\n");
571 return true;
572
573 log_fail:
574 DRM_LOG_KMS("... failed\n");
575 return false;
576 }
577
578 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
579 {
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586 }
587
588 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
590 {
591 /* This must be the immediately preceding write before the i2c xfer */
592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
595 }
596
597 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
598 {
599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
603 }
604
605 static bool
606 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607 {
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
610
611 return intel_sdvo_read_response(intel_sdvo, value, len);
612 }
613
614 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615 {
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
620 }
621
622 /**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
628 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
629 {
630 struct intel_sdvo_get_trained_inputs_response response;
631
632 BUILD_BUG_ON(sizeof(response) != 1);
633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640 }
641
642 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
643 u16 outputs)
644 {
645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
648 }
649
650 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652 {
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656 }
657
658 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
659 int mode)
660 {
661 u8 state = SDVO_ENCODER_STATE_ON;
662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
680 }
681
682 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
683 int *clock_min,
684 int *clock_max)
685 {
686 struct intel_sdvo_pixel_clock_range clocks;
687
688 BUILD_BUG_ON(sizeof(clocks) != 4);
689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
697 return true;
698 }
699
700 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
701 u16 outputs)
702 {
703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
706 }
707
708 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
709 struct intel_sdvo_dtd *dtd)
710 {
711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
713 }
714
715 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717 {
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720 }
721
722 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
723 struct intel_sdvo_dtd *dtd)
724 {
725 return intel_sdvo_set_timing(intel_sdvo,
726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727 }
728
729 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
730 struct intel_sdvo_dtd *dtd)
731 {
732 return intel_sdvo_set_timing(intel_sdvo,
733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734 }
735
736 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738 {
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741 }
742
743 static bool
744 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748 {
749 struct intel_sdvo_preferred_input_timing_args args;
750
751 memset(&args, 0, sizeof(args));
752 args.clock = clock;
753 args.width = width;
754 args.height = height;
755 args.interlace = 0;
756
757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
760 args.scaled = 1;
761
762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
765 }
766
767 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
768 struct intel_sdvo_dtd *dtd)
769 {
770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
776 }
777
778 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
779 {
780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
781 }
782
783 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
784 const struct drm_display_mode *mode)
785 {
786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
789 int mode_clock;
790
791 memset(dtd, 0, sizeof(*dtd));
792
793 width = mode->hdisplay;
794 height = mode->vdisplay;
795
796 /* do some mode translations */
797 h_blank_len = mode->htotal - mode->hdisplay;
798 h_sync_len = mode->hsync_end - mode->hsync_start;
799
800 v_blank_len = mode->vtotal - mode->vdisplay;
801 v_sync_len = mode->vsync_end - mode->vsync_start;
802
803 h_sync_offset = mode->hsync_start - mode->hdisplay;
804 v_sync_offset = mode->vsync_start - mode->vdisplay;
805
806 mode_clock = mode->clock;
807 mode_clock /= 10;
808 dtd->part1.clock = mode_clock;
809
810 dtd->part1.h_active = width & 0xff;
811 dtd->part1.h_blank = h_blank_len & 0xff;
812 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
813 ((h_blank_len >> 8) & 0xf);
814 dtd->part1.v_active = height & 0xff;
815 dtd->part1.v_blank = v_blank_len & 0xff;
816 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
817 ((v_blank_len >> 8) & 0xf);
818
819 dtd->part2.h_sync_off = h_sync_offset & 0xff;
820 dtd->part2.h_sync_width = h_sync_len & 0xff;
821 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
822 (v_sync_len & 0xf);
823 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
824 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
825 ((v_sync_len & 0x30) >> 4);
826
827 dtd->part2.dtd_flags = 0x18;
828 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
829 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
830 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
831 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
832 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
833 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
834
835 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
836 }
837
838 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
839 const struct intel_sdvo_dtd *dtd)
840 {
841 struct drm_display_mode mode = {};
842
843 mode.hdisplay = dtd->part1.h_active;
844 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
845 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
846 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
847 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
848 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
849 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
850 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
851
852 mode.vdisplay = dtd->part1.v_active;
853 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
854 mode.vsync_start = mode.vdisplay;
855 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
856 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
857 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
858 mode.vsync_end = mode.vsync_start +
859 (dtd->part2.v_sync_off_width & 0xf);
860 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
861 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
862 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
863
864 mode.clock = dtd->part1.clock * 10;
865
866 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
867 mode.flags |= DRM_MODE_FLAG_INTERLACE;
868 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
869 mode.flags |= DRM_MODE_FLAG_PHSYNC;
870 else
871 mode.flags |= DRM_MODE_FLAG_NHSYNC;
872 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
873 mode.flags |= DRM_MODE_FLAG_PVSYNC;
874 else
875 mode.flags |= DRM_MODE_FLAG_NVSYNC;
876
877 drm_mode_set_crtcinfo(&mode, 0);
878
879 drm_mode_copy(pmode, &mode);
880 }
881
882 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
883 {
884 struct intel_sdvo_encode encode;
885
886 BUILD_BUG_ON(sizeof(encode) != 2);
887 return intel_sdvo_get_value(intel_sdvo,
888 SDVO_CMD_GET_SUPP_ENCODE,
889 &encode, sizeof(encode));
890 }
891
892 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
893 uint8_t mode)
894 {
895 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
896 }
897
898 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
899 uint8_t mode)
900 {
901 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
902 }
903
904 #if 0
905 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
906 {
907 int i, j;
908 uint8_t set_buf_index[2];
909 uint8_t av_split;
910 uint8_t buf_size;
911 uint8_t buf[48];
912 uint8_t *pos;
913
914 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
915
916 for (i = 0; i <= av_split; i++) {
917 set_buf_index[0] = i; set_buf_index[1] = 0;
918 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
919 set_buf_index, 2);
920 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
921 intel_sdvo_read_response(encoder, &buf_size, 1);
922
923 pos = buf;
924 for (j = 0; j <= buf_size; j += 8) {
925 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
926 NULL, 0);
927 intel_sdvo_read_response(encoder, pos, 8);
928 pos += 8;
929 }
930 }
931 }
932 #endif
933
934 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
935 unsigned if_index, uint8_t tx_rate,
936 uint8_t *data, unsigned length)
937 {
938 uint8_t set_buf_index[2] = { if_index, 0 };
939 uint8_t hbuf_size, tmp[8];
940 int i;
941
942 if (!intel_sdvo_set_value(intel_sdvo,
943 SDVO_CMD_SET_HBUF_INDEX,
944 set_buf_index, 2))
945 return false;
946
947 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
948 &hbuf_size, 1))
949 return false;
950
951 /* Buffer size is 0 based, hooray! */
952 hbuf_size++;
953
954 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
955 if_index, length, hbuf_size);
956
957 for (i = 0; i < hbuf_size; i += 8) {
958 memset(tmp, 0, 8);
959 if (i < length)
960 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
961
962 if (!intel_sdvo_set_value(intel_sdvo,
963 SDVO_CMD_SET_HBUF_DATA,
964 tmp, 8))
965 return false;
966 }
967
968 return intel_sdvo_set_value(intel_sdvo,
969 SDVO_CMD_SET_HBUF_TXRATE,
970 &tx_rate, 1);
971 }
972
973 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
974 const struct drm_display_mode *adjusted_mode)
975 {
976 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
977 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
979 union hdmi_infoframe frame;
980 int ret;
981 ssize_t len;
982
983 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
984 adjusted_mode);
985 if (ret < 0) {
986 DRM_ERROR("couldn't fill AVI infoframe\n");
987 return false;
988 }
989
990 if (intel_sdvo->rgb_quant_range_selectable) {
991 if (intel_crtc->config.limited_color_range)
992 frame.avi.quantization_range =
993 HDMI_QUANTIZATION_RANGE_LIMITED;
994 else
995 frame.avi.quantization_range =
996 HDMI_QUANTIZATION_RANGE_FULL;
997 }
998
999 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1000 if (len < 0)
1001 return false;
1002
1003 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1004 SDVO_HBUF_TX_VSYNC,
1005 sdvo_data, sizeof(sdvo_data));
1006 }
1007
1008 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
1009 {
1010 struct intel_sdvo_tv_format format;
1011 uint32_t format_map;
1012
1013 format_map = 1 << intel_sdvo->tv_format_index;
1014 memset(&format, 0, sizeof(format));
1015 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1016
1017 BUILD_BUG_ON(sizeof(format) != 6);
1018 return intel_sdvo_set_value(intel_sdvo,
1019 SDVO_CMD_SET_TV_FORMAT,
1020 &format, sizeof(format));
1021 }
1022
1023 static bool
1024 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1025 const struct drm_display_mode *mode)
1026 {
1027 struct intel_sdvo_dtd output_dtd;
1028
1029 if (!intel_sdvo_set_target_output(intel_sdvo,
1030 intel_sdvo->attached_output))
1031 return false;
1032
1033 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1034 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1035 return false;
1036
1037 return true;
1038 }
1039
1040 /* Asks the sdvo controller for the preferred input mode given the output mode.
1041 * Unfortunately we have to set up the full output mode to do that. */
1042 static bool
1043 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1044 const struct drm_display_mode *mode,
1045 struct drm_display_mode *adjusted_mode)
1046 {
1047 struct intel_sdvo_dtd input_dtd;
1048
1049 /* Reset the input timing to the screen. Assume always input 0. */
1050 if (!intel_sdvo_set_target_input(intel_sdvo))
1051 return false;
1052
1053 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1054 mode->clock / 10,
1055 mode->hdisplay,
1056 mode->vdisplay))
1057 return false;
1058
1059 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1060 &input_dtd))
1061 return false;
1062
1063 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1064 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1065
1066 return true;
1067 }
1068
1069 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1070 {
1071 unsigned dotclock = pipe_config->adjusted_mode.clock;
1072 struct dpll *clock = &pipe_config->dpll;
1073
1074 /* SDVO TV has fixed PLL values depend on its clock range,
1075 this mirrors vbios setting. */
1076 if (dotclock >= 100000 && dotclock < 140500) {
1077 clock->p1 = 2;
1078 clock->p2 = 10;
1079 clock->n = 3;
1080 clock->m1 = 16;
1081 clock->m2 = 8;
1082 } else if (dotclock >= 140500 && dotclock <= 200000) {
1083 clock->p1 = 1;
1084 clock->p2 = 10;
1085 clock->n = 6;
1086 clock->m1 = 12;
1087 clock->m2 = 8;
1088 } else {
1089 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1090 }
1091
1092 pipe_config->clock_set = true;
1093 }
1094
1095 static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1096 struct intel_crtc_config *pipe_config)
1097 {
1098 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1099 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1100 struct drm_display_mode *mode = &pipe_config->requested_mode;
1101
1102 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1103 pipe_config->pipe_bpp = 8*3;
1104
1105 if (HAS_PCH_SPLIT(encoder->base.dev))
1106 pipe_config->has_pch_encoder = true;
1107
1108 /* We need to construct preferred input timings based on our
1109 * output timings. To do that, we have to set the output
1110 * timings, even though this isn't really the right place in
1111 * the sequence to do it. Oh well.
1112 */
1113 if (intel_sdvo->is_tv) {
1114 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1115 return false;
1116
1117 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1118 mode,
1119 adjusted_mode);
1120 pipe_config->sdvo_tv_clock = true;
1121 } else if (intel_sdvo->is_lvds) {
1122 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1123 intel_sdvo->sdvo_lvds_fixed_mode))
1124 return false;
1125
1126 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1127 mode,
1128 adjusted_mode);
1129 }
1130
1131 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1132 * SDVO device will factor out the multiplier during mode_set.
1133 */
1134 pipe_config->pixel_multiplier =
1135 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1136 adjusted_mode->clock *= pipe_config->pixel_multiplier;
1137
1138 if (intel_sdvo->color_range_auto) {
1139 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1140 /* FIXME: This bit is only valid when using TMDS encoding and 8
1141 * bit per color mode. */
1142 if (intel_sdvo->has_hdmi_monitor &&
1143 drm_match_cea_mode(adjusted_mode) > 1)
1144 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
1145 else
1146 intel_sdvo->color_range = 0;
1147 }
1148
1149 if (intel_sdvo->color_range)
1150 pipe_config->limited_color_range = true;
1151
1152 /* Clock computation needs to happen after pixel multiplier. */
1153 if (intel_sdvo->is_tv)
1154 i9xx_adjust_sdvo_tv_clock(pipe_config);
1155
1156 return true;
1157 }
1158
1159 static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
1160 {
1161 struct drm_device *dev = intel_encoder->base.dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
1164 struct drm_display_mode *adjusted_mode =
1165 &crtc->config.adjusted_mode;
1166 struct drm_display_mode *mode = &crtc->config.requested_mode;
1167 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1168 u32 sdvox;
1169 struct intel_sdvo_in_out_map in_out;
1170 struct intel_sdvo_dtd input_dtd, output_dtd;
1171 int rate;
1172
1173 if (!mode)
1174 return;
1175
1176 /* First, set the input mapping for the first input to our controlled
1177 * output. This is only correct if we're a single-input device, in
1178 * which case the first input is the output from the appropriate SDVO
1179 * channel on the motherboard. In a two-input device, the first input
1180 * will be SDVOB and the second SDVOC.
1181 */
1182 in_out.in0 = intel_sdvo->attached_output;
1183 in_out.in1 = 0;
1184
1185 intel_sdvo_set_value(intel_sdvo,
1186 SDVO_CMD_SET_IN_OUT_MAP,
1187 &in_out, sizeof(in_out));
1188
1189 /* Set the output timings to the screen */
1190 if (!intel_sdvo_set_target_output(intel_sdvo,
1191 intel_sdvo->attached_output))
1192 return;
1193
1194 /* lvds has a special fixed output timing. */
1195 if (intel_sdvo->is_lvds)
1196 intel_sdvo_get_dtd_from_mode(&output_dtd,
1197 intel_sdvo->sdvo_lvds_fixed_mode);
1198 else
1199 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1200 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1201 DRM_INFO("Setting output timings on %s failed\n",
1202 SDVO_NAME(intel_sdvo));
1203
1204 /* Set the input timing to the screen. Assume always input 0. */
1205 if (!intel_sdvo_set_target_input(intel_sdvo))
1206 return;
1207
1208 if (intel_sdvo->has_hdmi_monitor) {
1209 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1210 intel_sdvo_set_colorimetry(intel_sdvo,
1211 SDVO_COLORIMETRY_RGB256);
1212 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
1213 } else
1214 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1215
1216 if (intel_sdvo->is_tv &&
1217 !intel_sdvo_set_tv_format(intel_sdvo))
1218 return;
1219
1220 /* We have tried to get input timing in mode_fixup, and filled into
1221 * adjusted_mode.
1222 */
1223 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1224 input_dtd.part1.clock /= crtc->config.pixel_multiplier;
1225
1226 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1227 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1228 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1229 DRM_INFO("Setting input timings on %s failed\n",
1230 SDVO_NAME(intel_sdvo));
1231
1232 switch (crtc->config.pixel_multiplier) {
1233 default:
1234 WARN(1, "unknown pixel mutlipler specified\n");
1235 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1236 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1237 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1238 }
1239 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1240 return;
1241
1242 /* Set the SDVO control regs. */
1243 if (INTEL_INFO(dev)->gen >= 4) {
1244 /* The real mode polarity is set by the SDVO commands, using
1245 * struct intel_sdvo_dtd. */
1246 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1247 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
1248 sdvox |= intel_sdvo->color_range;
1249 if (INTEL_INFO(dev)->gen < 5)
1250 sdvox |= SDVO_BORDER_ENABLE;
1251 } else {
1252 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1253 switch (intel_sdvo->sdvo_reg) {
1254 case GEN3_SDVOB:
1255 sdvox &= SDVOB_PRESERVE_MASK;
1256 break;
1257 case GEN3_SDVOC:
1258 sdvox &= SDVOC_PRESERVE_MASK;
1259 break;
1260 }
1261 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1262 }
1263
1264 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1265 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1266 else
1267 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1268
1269 if (intel_sdvo->has_hdmi_audio)
1270 sdvox |= SDVO_AUDIO_ENABLE;
1271
1272 if (INTEL_INFO(dev)->gen >= 4) {
1273 /* done in crtc_mode_set as the dpll_md reg must be written early */
1274 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1275 /* done in crtc_mode_set as it lives inside the dpll register */
1276 } else {
1277 sdvox |= (crtc->config.pixel_multiplier - 1)
1278 << SDVO_PORT_MULTIPLY_SHIFT;
1279 }
1280
1281 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1282 INTEL_INFO(dev)->gen < 5)
1283 sdvox |= SDVO_STALL_SELECT;
1284 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1285 }
1286
1287 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1288 {
1289 struct intel_sdvo_connector *intel_sdvo_connector =
1290 to_intel_sdvo_connector(&connector->base);
1291 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1292 u16 active_outputs = 0;
1293
1294 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1295
1296 if (active_outputs & intel_sdvo_connector->output_flag)
1297 return true;
1298 else
1299 return false;
1300 }
1301
1302 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1303 enum pipe *pipe)
1304 {
1305 struct drm_device *dev = encoder->base.dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1308 u16 active_outputs = 0;
1309 u32 tmp;
1310
1311 tmp = I915_READ(intel_sdvo->sdvo_reg);
1312 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1313
1314 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
1315 return false;
1316
1317 if (HAS_PCH_CPT(dev))
1318 *pipe = PORT_TO_PIPE_CPT(tmp);
1319 else
1320 *pipe = PORT_TO_PIPE(tmp);
1321
1322 return true;
1323 }
1324
1325 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1326 struct intel_crtc_config *pipe_config)
1327 {
1328 struct drm_device *dev = encoder->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1331 struct intel_sdvo_dtd dtd;
1332 int encoder_pixel_multiplier = 0;
1333 u32 flags = 0, sdvox;
1334 u8 val;
1335 bool ret;
1336
1337 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1338 if (!ret) {
1339 /* Some sdvo encoders are not spec compliant and don't
1340 * implement the mandatory get_timings function. */
1341 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1342 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1343 } else {
1344 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1345 flags |= DRM_MODE_FLAG_PHSYNC;
1346 else
1347 flags |= DRM_MODE_FLAG_NHSYNC;
1348
1349 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1350 flags |= DRM_MODE_FLAG_PVSYNC;
1351 else
1352 flags |= DRM_MODE_FLAG_NVSYNC;
1353 }
1354
1355 pipe_config->adjusted_mode.flags |= flags;
1356
1357 /*
1358 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1359 * the sdvo port register, on all other platforms it is part of the dpll
1360 * state. Since the general pipe state readout happens before the
1361 * encoder->get_config we so already have a valid pixel multplier on all
1362 * other platfroms.
1363 */
1364 if (IS_I915G(dev) || IS_I915GM(dev)) {
1365 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1366 pipe_config->pixel_multiplier =
1367 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1368 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1369 }
1370
1371 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1372 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1373 &val, 1)) {
1374 switch (val) {
1375 case SDVO_CLOCK_RATE_MULT_1X:
1376 encoder_pixel_multiplier = 1;
1377 break;
1378 case SDVO_CLOCK_RATE_MULT_2X:
1379 encoder_pixel_multiplier = 2;
1380 break;
1381 case SDVO_CLOCK_RATE_MULT_4X:
1382 encoder_pixel_multiplier = 4;
1383 break;
1384 }
1385 }
1386
1387 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1388 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1389 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1390 }
1391
1392 static void intel_disable_sdvo(struct intel_encoder *encoder)
1393 {
1394 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1395 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1396 u32 temp;
1397
1398 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1399 if (0)
1400 intel_sdvo_set_encoder_power_state(intel_sdvo,
1401 DRM_MODE_DPMS_OFF);
1402
1403 temp = I915_READ(intel_sdvo->sdvo_reg);
1404 if ((temp & SDVO_ENABLE) != 0) {
1405 /* HW workaround for IBX, we need to move the port to
1406 * transcoder A before disabling it. */
1407 if (HAS_PCH_IBX(encoder->base.dev)) {
1408 struct drm_crtc *crtc = encoder->base.crtc;
1409 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1410
1411 if (temp & SDVO_PIPE_B_SELECT) {
1412 temp &= ~SDVO_PIPE_B_SELECT;
1413 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1414 POSTING_READ(intel_sdvo->sdvo_reg);
1415
1416 /* Again we need to write this twice. */
1417 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1418 POSTING_READ(intel_sdvo->sdvo_reg);
1419
1420 /* Transcoder selection bits only update
1421 * effectively on vblank. */
1422 if (crtc)
1423 intel_wait_for_vblank(encoder->base.dev, pipe);
1424 else
1425 msleep(50);
1426 }
1427 }
1428
1429 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1430 }
1431 }
1432
1433 static void intel_enable_sdvo(struct intel_encoder *encoder)
1434 {
1435 struct drm_device *dev = encoder->base.dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1438 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1439 u32 temp;
1440 bool input1, input2;
1441 int i;
1442 u8 status;
1443
1444 temp = I915_READ(intel_sdvo->sdvo_reg);
1445 if ((temp & SDVO_ENABLE) == 0) {
1446 /* HW workaround for IBX, we need to move the port
1447 * to transcoder A before disabling it, so restore it here. */
1448 if (HAS_PCH_IBX(dev))
1449 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
1450
1451 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1452 }
1453 for (i = 0; i < 2; i++)
1454 intel_wait_for_vblank(dev, intel_crtc->pipe);
1455
1456 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1457 /* Warn if the device reported failure to sync.
1458 * A lot of SDVO devices fail to notify of sync, but it's
1459 * a given it the status is a success, we succeeded.
1460 */
1461 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1462 DRM_DEBUG_KMS("First %s output reported failure to "
1463 "sync\n", SDVO_NAME(intel_sdvo));
1464 }
1465
1466 if (0)
1467 intel_sdvo_set_encoder_power_state(intel_sdvo,
1468 DRM_MODE_DPMS_ON);
1469 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1470 }
1471
1472 /* Special dpms function to support cloning between dvo/sdvo/crt. */
1473 static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
1474 {
1475 struct drm_crtc *crtc;
1476 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1477
1478 /* dvo supports only 2 dpms states. */
1479 if (mode != DRM_MODE_DPMS_ON)
1480 mode = DRM_MODE_DPMS_OFF;
1481
1482 if (mode == connector->dpms)
1483 return;
1484
1485 connector->dpms = mode;
1486
1487 /* Only need to change hw state when actually enabled */
1488 crtc = intel_sdvo->base.base.crtc;
1489 if (!crtc) {
1490 intel_sdvo->base.connectors_active = false;
1491 return;
1492 }
1493
1494 /* We set active outputs manually below in case pipe dpms doesn't change
1495 * due to cloning. */
1496 if (mode != DRM_MODE_DPMS_ON) {
1497 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1498 if (0)
1499 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1500
1501 intel_sdvo->base.connectors_active = false;
1502
1503 intel_crtc_update_dpms(crtc);
1504 } else {
1505 intel_sdvo->base.connectors_active = true;
1506
1507 intel_crtc_update_dpms(crtc);
1508
1509 if (0)
1510 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1511 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1512 }
1513
1514 intel_modeset_check_state(connector->dev);
1515 }
1516
1517 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1518 struct drm_display_mode *mode)
1519 {
1520 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1521
1522 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1523 return MODE_NO_DBLESCAN;
1524
1525 if (intel_sdvo->pixel_clock_min > mode->clock)
1526 return MODE_CLOCK_LOW;
1527
1528 if (intel_sdvo->pixel_clock_max < mode->clock)
1529 return MODE_CLOCK_HIGH;
1530
1531 if (intel_sdvo->is_lvds) {
1532 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1533 return MODE_PANEL;
1534
1535 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1536 return MODE_PANEL;
1537 }
1538
1539 return MODE_OK;
1540 }
1541
1542 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1543 {
1544 BUILD_BUG_ON(sizeof(*caps) != 8);
1545 if (!intel_sdvo_get_value(intel_sdvo,
1546 SDVO_CMD_GET_DEVICE_CAPS,
1547 caps, sizeof(*caps)))
1548 return false;
1549
1550 DRM_DEBUG_KMS("SDVO capabilities:\n"
1551 " vendor_id: %d\n"
1552 " device_id: %d\n"
1553 " device_rev_id: %d\n"
1554 " sdvo_version_major: %d\n"
1555 " sdvo_version_minor: %d\n"
1556 " sdvo_inputs_mask: %d\n"
1557 " smooth_scaling: %d\n"
1558 " sharp_scaling: %d\n"
1559 " up_scaling: %d\n"
1560 " down_scaling: %d\n"
1561 " stall_support: %d\n"
1562 " output_flags: %d\n",
1563 caps->vendor_id,
1564 caps->device_id,
1565 caps->device_rev_id,
1566 caps->sdvo_version_major,
1567 caps->sdvo_version_minor,
1568 caps->sdvo_inputs_mask,
1569 caps->smooth_scaling,
1570 caps->sharp_scaling,
1571 caps->up_scaling,
1572 caps->down_scaling,
1573 caps->stall_support,
1574 caps->output_flags);
1575
1576 return true;
1577 }
1578
1579 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1580 {
1581 struct drm_device *dev = intel_sdvo->base.base.dev;
1582 uint16_t hotplug;
1583
1584 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1585 * on the line. */
1586 if (IS_I945G(dev) || IS_I945GM(dev))
1587 return 0;
1588
1589 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1590 &hotplug, sizeof(hotplug)))
1591 return 0;
1592
1593 return hotplug;
1594 }
1595
1596 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1597 {
1598 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1599
1600 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1601 &intel_sdvo->hotplug_active, 2);
1602 }
1603
1604 static bool
1605 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1606 {
1607 /* Is there more than one type of output? */
1608 return hweight16(intel_sdvo->caps.output_flags) > 1;
1609 }
1610
1611 static struct edid *
1612 intel_sdvo_get_edid(struct drm_connector *connector)
1613 {
1614 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1615 return drm_get_edid(connector, &sdvo->ddc);
1616 }
1617
1618 /* Mac mini hack -- use the same DDC as the analog connector */
1619 static struct edid *
1620 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1621 {
1622 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1623
1624 return drm_get_edid(connector,
1625 intel_gmbus_get_adapter(dev_priv,
1626 dev_priv->vbt.crt_ddc_pin));
1627 }
1628
1629 static enum drm_connector_status
1630 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1631 {
1632 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1633 enum drm_connector_status status;
1634 struct edid *edid;
1635
1636 edid = intel_sdvo_get_edid(connector);
1637
1638 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1639 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1640
1641 /*
1642 * Don't use the 1 as the argument of DDC bus switch to get
1643 * the EDID. It is used for SDVO SPD ROM.
1644 */
1645 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1646 intel_sdvo->ddc_bus = ddc;
1647 edid = intel_sdvo_get_edid(connector);
1648 if (edid)
1649 break;
1650 }
1651 /*
1652 * If we found the EDID on the other bus,
1653 * assume that is the correct DDC bus.
1654 */
1655 if (edid == NULL)
1656 intel_sdvo->ddc_bus = saved_ddc;
1657 }
1658
1659 /*
1660 * When there is no edid and no monitor is connected with VGA
1661 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1662 */
1663 if (edid == NULL)
1664 edid = intel_sdvo_get_analog_edid(connector);
1665
1666 status = connector_status_unknown;
1667 if (edid != NULL) {
1668 /* DDC bus is shared, match EDID to connector type */
1669 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1670 status = connector_status_connected;
1671 if (intel_sdvo->is_hdmi) {
1672 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1673 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1674 intel_sdvo->rgb_quant_range_selectable =
1675 drm_rgb_quant_range_selectable(edid);
1676 }
1677 } else
1678 status = connector_status_disconnected;
1679 kfree(edid);
1680 }
1681
1682 if (status == connector_status_connected) {
1683 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1684 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1685 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
1686 }
1687
1688 return status;
1689 }
1690
1691 static bool
1692 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1693 struct edid *edid)
1694 {
1695 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1696 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1697
1698 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1699 connector_is_digital, monitor_is_digital);
1700 return connector_is_digital == monitor_is_digital;
1701 }
1702
1703 static enum drm_connector_status
1704 intel_sdvo_detect(struct drm_connector *connector, bool force)
1705 {
1706 uint16_t response;
1707 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1708 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1709 enum drm_connector_status ret;
1710
1711 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1712 connector->base.id, drm_get_connector_name(connector));
1713
1714 if (!intel_sdvo_get_value(intel_sdvo,
1715 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1716 &response, 2))
1717 return connector_status_unknown;
1718
1719 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1720 response & 0xff, response >> 8,
1721 intel_sdvo_connector->output_flag);
1722
1723 if (response == 0)
1724 return connector_status_disconnected;
1725
1726 intel_sdvo->attached_output = response;
1727
1728 intel_sdvo->has_hdmi_monitor = false;
1729 intel_sdvo->has_hdmi_audio = false;
1730 intel_sdvo->rgb_quant_range_selectable = false;
1731
1732 if ((intel_sdvo_connector->output_flag & response) == 0)
1733 ret = connector_status_disconnected;
1734 else if (IS_TMDS(intel_sdvo_connector))
1735 ret = intel_sdvo_tmds_sink_detect(connector);
1736 else {
1737 struct edid *edid;
1738
1739 /* if we have an edid check it matches the connection */
1740 edid = intel_sdvo_get_edid(connector);
1741 if (edid == NULL)
1742 edid = intel_sdvo_get_analog_edid(connector);
1743 if (edid != NULL) {
1744 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1745 edid))
1746 ret = connector_status_connected;
1747 else
1748 ret = connector_status_disconnected;
1749
1750 kfree(edid);
1751 } else
1752 ret = connector_status_connected;
1753 }
1754
1755 /* May update encoder flag for like clock for SDVO TV, etc.*/
1756 if (ret == connector_status_connected) {
1757 intel_sdvo->is_tv = false;
1758 intel_sdvo->is_lvds = false;
1759
1760 if (response & SDVO_TV_MASK)
1761 intel_sdvo->is_tv = true;
1762 if (response & SDVO_LVDS_MASK)
1763 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1764 }
1765
1766 return ret;
1767 }
1768
1769 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1770 {
1771 struct edid *edid;
1772
1773 /* set the bus switch and get the modes */
1774 edid = intel_sdvo_get_edid(connector);
1775
1776 /*
1777 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1778 * link between analog and digital outputs. So, if the regular SDVO
1779 * DDC fails, check to see if the analog output is disconnected, in
1780 * which case we'll look there for the digital DDC data.
1781 */
1782 if (edid == NULL)
1783 edid = intel_sdvo_get_analog_edid(connector);
1784
1785 if (edid != NULL) {
1786 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1787 edid)) {
1788 drm_mode_connector_update_edid_property(connector, edid);
1789 drm_add_edid_modes(connector, edid);
1790 }
1791
1792 kfree(edid);
1793 }
1794 }
1795
1796 /*
1797 * Set of SDVO TV modes.
1798 * Note! This is in reply order (see loop in get_tv_modes).
1799 * XXX: all 60Hz refresh?
1800 */
1801 static const struct drm_display_mode sdvo_tv_modes[] = {
1802 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1803 416, 0, 200, 201, 232, 233, 0,
1804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1805 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1806 416, 0, 240, 241, 272, 273, 0,
1807 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1808 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1809 496, 0, 300, 301, 332, 333, 0,
1810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1811 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1812 736, 0, 350, 351, 382, 383, 0,
1813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1814 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1815 736, 0, 400, 401, 432, 433, 0,
1816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1817 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1818 736, 0, 480, 481, 512, 513, 0,
1819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1820 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1821 800, 0, 480, 481, 512, 513, 0,
1822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1823 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1824 800, 0, 576, 577, 608, 609, 0,
1825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1826 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1827 816, 0, 350, 351, 382, 383, 0,
1828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1829 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1830 816, 0, 400, 401, 432, 433, 0,
1831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1832 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1833 816, 0, 480, 481, 512, 513, 0,
1834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1835 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1836 816, 0, 540, 541, 572, 573, 0,
1837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1839 816, 0, 576, 577, 608, 609, 0,
1840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1841 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1842 864, 0, 576, 577, 608, 609, 0,
1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1844 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1845 896, 0, 600, 601, 632, 633, 0,
1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1847 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1848 928, 0, 624, 625, 656, 657, 0,
1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1850 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1851 1016, 0, 766, 767, 798, 799, 0,
1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1853 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1854 1120, 0, 768, 769, 800, 801, 0,
1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1856 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1857 1376, 0, 1024, 1025, 1056, 1057, 0,
1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1859 };
1860
1861 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1862 {
1863 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1864 struct intel_sdvo_sdtv_resolution_request tv_res;
1865 uint32_t reply = 0, format_map = 0;
1866 int i;
1867
1868 /* Read the list of supported input resolutions for the selected TV
1869 * format.
1870 */
1871 format_map = 1 << intel_sdvo->tv_format_index;
1872 memcpy(&tv_res, &format_map,
1873 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1874
1875 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1876 return;
1877
1878 BUILD_BUG_ON(sizeof(tv_res) != 3);
1879 if (!intel_sdvo_write_cmd(intel_sdvo,
1880 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1881 &tv_res, sizeof(tv_res)))
1882 return;
1883 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1884 return;
1885
1886 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1887 if (reply & (1 << i)) {
1888 struct drm_display_mode *nmode;
1889 nmode = drm_mode_duplicate(connector->dev,
1890 &sdvo_tv_modes[i]);
1891 if (nmode)
1892 drm_mode_probed_add(connector, nmode);
1893 }
1894 }
1895
1896 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1897 {
1898 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1899 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1900 struct drm_display_mode *newmode;
1901
1902 /*
1903 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
1904 * SDVO->LVDS transcoders can't cope with the EDID mode.
1905 */
1906 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
1907 newmode = drm_mode_duplicate(connector->dev,
1908 dev_priv->vbt.sdvo_lvds_vbt_mode);
1909 if (newmode != NULL) {
1910 /* Guarantee the mode is preferred */
1911 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1912 DRM_MODE_TYPE_DRIVER);
1913 drm_mode_probed_add(connector, newmode);
1914 }
1915 }
1916
1917 /*
1918 * Attempt to get the mode list from DDC.
1919 * Assume that the preferred modes are
1920 * arranged in priority order.
1921 */
1922 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1923
1924 list_for_each_entry(newmode, &connector->probed_modes, head) {
1925 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1926 intel_sdvo->sdvo_lvds_fixed_mode =
1927 drm_mode_duplicate(connector->dev, newmode);
1928
1929 intel_sdvo->is_lvds = true;
1930 break;
1931 }
1932 }
1933
1934 }
1935
1936 static int intel_sdvo_get_modes(struct drm_connector *connector)
1937 {
1938 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1939
1940 if (IS_TV(intel_sdvo_connector))
1941 intel_sdvo_get_tv_modes(connector);
1942 else if (IS_LVDS(intel_sdvo_connector))
1943 intel_sdvo_get_lvds_modes(connector);
1944 else
1945 intel_sdvo_get_ddc_modes(connector);
1946
1947 return !list_empty(&connector->probed_modes);
1948 }
1949
1950 static void
1951 intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1952 {
1953 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1954 struct drm_device *dev = connector->dev;
1955
1956 if (intel_sdvo_connector->left)
1957 drm_property_destroy(dev, intel_sdvo_connector->left);
1958 if (intel_sdvo_connector->right)
1959 drm_property_destroy(dev, intel_sdvo_connector->right);
1960 if (intel_sdvo_connector->top)
1961 drm_property_destroy(dev, intel_sdvo_connector->top);
1962 if (intel_sdvo_connector->bottom)
1963 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1964 if (intel_sdvo_connector->hpos)
1965 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1966 if (intel_sdvo_connector->vpos)
1967 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1968 if (intel_sdvo_connector->saturation)
1969 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1970 if (intel_sdvo_connector->contrast)
1971 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1972 if (intel_sdvo_connector->hue)
1973 drm_property_destroy(dev, intel_sdvo_connector->hue);
1974 if (intel_sdvo_connector->sharpness)
1975 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1976 if (intel_sdvo_connector->flicker_filter)
1977 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1978 if (intel_sdvo_connector->flicker_filter_2d)
1979 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1980 if (intel_sdvo_connector->flicker_filter_adaptive)
1981 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1982 if (intel_sdvo_connector->tv_luma_filter)
1983 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1984 if (intel_sdvo_connector->tv_chroma_filter)
1985 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1986 if (intel_sdvo_connector->dot_crawl)
1987 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
1988 if (intel_sdvo_connector->brightness)
1989 drm_property_destroy(dev, intel_sdvo_connector->brightness);
1990 }
1991
1992 static void intel_sdvo_destroy(struct drm_connector *connector)
1993 {
1994 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1995
1996 if (intel_sdvo_connector->tv_format)
1997 drm_property_destroy(connector->dev,
1998 intel_sdvo_connector->tv_format);
1999
2000 intel_sdvo_destroy_enhance_property(connector);
2001 drm_sysfs_connector_remove(connector);
2002 drm_connector_cleanup(connector);
2003 kfree(intel_sdvo_connector);
2004 }
2005
2006 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
2007 {
2008 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2009 struct edid *edid;
2010 bool has_audio = false;
2011
2012 if (!intel_sdvo->is_hdmi)
2013 return false;
2014
2015 edid = intel_sdvo_get_edid(connector);
2016 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2017 has_audio = drm_detect_monitor_audio(edid);
2018 kfree(edid);
2019
2020 return has_audio;
2021 }
2022
2023 static int
2024 intel_sdvo_set_property(struct drm_connector *connector,
2025 struct drm_property *property,
2026 uint64_t val)
2027 {
2028 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2029 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2030 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2031 uint16_t temp_value;
2032 uint8_t cmd;
2033 int ret;
2034
2035 ret = drm_object_property_set_value(&connector->base, property, val);
2036 if (ret)
2037 return ret;
2038
2039 if (property == dev_priv->force_audio_property) {
2040 int i = val;
2041 bool has_audio;
2042
2043 if (i == intel_sdvo_connector->force_audio)
2044 return 0;
2045
2046 intel_sdvo_connector->force_audio = i;
2047
2048 if (i == HDMI_AUDIO_AUTO)
2049 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2050 else
2051 has_audio = (i == HDMI_AUDIO_ON);
2052
2053 if (has_audio == intel_sdvo->has_hdmi_audio)
2054 return 0;
2055
2056 intel_sdvo->has_hdmi_audio = has_audio;
2057 goto done;
2058 }
2059
2060 if (property == dev_priv->broadcast_rgb_property) {
2061 bool old_auto = intel_sdvo->color_range_auto;
2062 uint32_t old_range = intel_sdvo->color_range;
2063
2064 switch (val) {
2065 case INTEL_BROADCAST_RGB_AUTO:
2066 intel_sdvo->color_range_auto = true;
2067 break;
2068 case INTEL_BROADCAST_RGB_FULL:
2069 intel_sdvo->color_range_auto = false;
2070 intel_sdvo->color_range = 0;
2071 break;
2072 case INTEL_BROADCAST_RGB_LIMITED:
2073 intel_sdvo->color_range_auto = false;
2074 /* FIXME: this bit is only valid when using TMDS
2075 * encoding and 8 bit per color mode. */
2076 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
2077 break;
2078 default:
2079 return -EINVAL;
2080 }
2081
2082 if (old_auto == intel_sdvo->color_range_auto &&
2083 old_range == intel_sdvo->color_range)
2084 return 0;
2085
2086 goto done;
2087 }
2088
2089 #define CHECK_PROPERTY(name, NAME) \
2090 if (intel_sdvo_connector->name == property) { \
2091 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2092 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2093 cmd = SDVO_CMD_SET_##NAME; \
2094 intel_sdvo_connector->cur_##name = temp_value; \
2095 goto set_value; \
2096 }
2097
2098 if (property == intel_sdvo_connector->tv_format) {
2099 if (val >= TV_FORMAT_NUM)
2100 return -EINVAL;
2101
2102 if (intel_sdvo->tv_format_index ==
2103 intel_sdvo_connector->tv_format_supported[val])
2104 return 0;
2105
2106 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
2107 goto done;
2108 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
2109 temp_value = val;
2110 if (intel_sdvo_connector->left == property) {
2111 drm_object_property_set_value(&connector->base,
2112 intel_sdvo_connector->right, val);
2113 if (intel_sdvo_connector->left_margin == temp_value)
2114 return 0;
2115
2116 intel_sdvo_connector->left_margin = temp_value;
2117 intel_sdvo_connector->right_margin = temp_value;
2118 temp_value = intel_sdvo_connector->max_hscan -
2119 intel_sdvo_connector->left_margin;
2120 cmd = SDVO_CMD_SET_OVERSCAN_H;
2121 goto set_value;
2122 } else if (intel_sdvo_connector->right == property) {
2123 drm_object_property_set_value(&connector->base,
2124 intel_sdvo_connector->left, val);
2125 if (intel_sdvo_connector->right_margin == temp_value)
2126 return 0;
2127
2128 intel_sdvo_connector->left_margin = temp_value;
2129 intel_sdvo_connector->right_margin = temp_value;
2130 temp_value = intel_sdvo_connector->max_hscan -
2131 intel_sdvo_connector->left_margin;
2132 cmd = SDVO_CMD_SET_OVERSCAN_H;
2133 goto set_value;
2134 } else if (intel_sdvo_connector->top == property) {
2135 drm_object_property_set_value(&connector->base,
2136 intel_sdvo_connector->bottom, val);
2137 if (intel_sdvo_connector->top_margin == temp_value)
2138 return 0;
2139
2140 intel_sdvo_connector->top_margin = temp_value;
2141 intel_sdvo_connector->bottom_margin = temp_value;
2142 temp_value = intel_sdvo_connector->max_vscan -
2143 intel_sdvo_connector->top_margin;
2144 cmd = SDVO_CMD_SET_OVERSCAN_V;
2145 goto set_value;
2146 } else if (intel_sdvo_connector->bottom == property) {
2147 drm_object_property_set_value(&connector->base,
2148 intel_sdvo_connector->top, val);
2149 if (intel_sdvo_connector->bottom_margin == temp_value)
2150 return 0;
2151
2152 intel_sdvo_connector->top_margin = temp_value;
2153 intel_sdvo_connector->bottom_margin = temp_value;
2154 temp_value = intel_sdvo_connector->max_vscan -
2155 intel_sdvo_connector->top_margin;
2156 cmd = SDVO_CMD_SET_OVERSCAN_V;
2157 goto set_value;
2158 }
2159 CHECK_PROPERTY(hpos, HPOS)
2160 CHECK_PROPERTY(vpos, VPOS)
2161 CHECK_PROPERTY(saturation, SATURATION)
2162 CHECK_PROPERTY(contrast, CONTRAST)
2163 CHECK_PROPERTY(hue, HUE)
2164 CHECK_PROPERTY(brightness, BRIGHTNESS)
2165 CHECK_PROPERTY(sharpness, SHARPNESS)
2166 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2167 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2168 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2169 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2170 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
2171 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
2172 }
2173
2174 return -EINVAL; /* unknown property */
2175
2176 set_value:
2177 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2178 return -EIO;
2179
2180
2181 done:
2182 if (intel_sdvo->base.base.crtc)
2183 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2184
2185 return 0;
2186 #undef CHECK_PROPERTY
2187 }
2188
2189 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2190 .dpms = intel_sdvo_dpms,
2191 .detect = intel_sdvo_detect,
2192 .fill_modes = drm_helper_probe_single_connector_modes,
2193 .set_property = intel_sdvo_set_property,
2194 .destroy = intel_sdvo_destroy,
2195 };
2196
2197 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2198 .get_modes = intel_sdvo_get_modes,
2199 .mode_valid = intel_sdvo_mode_valid,
2200 .best_encoder = intel_best_encoder,
2201 };
2202
2203 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2204 {
2205 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2206
2207 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2208 drm_mode_destroy(encoder->dev,
2209 intel_sdvo->sdvo_lvds_fixed_mode);
2210
2211 i2c_del_adapter(&intel_sdvo->ddc);
2212 intel_encoder_destroy(encoder);
2213 }
2214
2215 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2216 .destroy = intel_sdvo_enc_destroy,
2217 };
2218
2219 static void
2220 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2221 {
2222 uint16_t mask = 0;
2223 unsigned int num_bits;
2224
2225 /* Make a mask of outputs less than or equal to our own priority in the
2226 * list.
2227 */
2228 switch (sdvo->controlled_output) {
2229 case SDVO_OUTPUT_LVDS1:
2230 mask |= SDVO_OUTPUT_LVDS1;
2231 case SDVO_OUTPUT_LVDS0:
2232 mask |= SDVO_OUTPUT_LVDS0;
2233 case SDVO_OUTPUT_TMDS1:
2234 mask |= SDVO_OUTPUT_TMDS1;
2235 case SDVO_OUTPUT_TMDS0:
2236 mask |= SDVO_OUTPUT_TMDS0;
2237 case SDVO_OUTPUT_RGB1:
2238 mask |= SDVO_OUTPUT_RGB1;
2239 case SDVO_OUTPUT_RGB0:
2240 mask |= SDVO_OUTPUT_RGB0;
2241 break;
2242 }
2243
2244 /* Count bits to find what number we are in the priority list. */
2245 mask &= sdvo->caps.output_flags;
2246 num_bits = hweight16(mask);
2247 /* If more than 3 outputs, default to DDC bus 3 for now. */
2248 if (num_bits > 3)
2249 num_bits = 3;
2250
2251 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2252 sdvo->ddc_bus = 1 << num_bits;
2253 }
2254
2255 /**
2256 * Choose the appropriate DDC bus for control bus switch command for this
2257 * SDVO output based on the controlled output.
2258 *
2259 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2260 * outputs, then LVDS outputs.
2261 */
2262 static void
2263 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2264 struct intel_sdvo *sdvo, u32 reg)
2265 {
2266 struct sdvo_device_mapping *mapping;
2267
2268 if (sdvo->is_sdvob)
2269 mapping = &(dev_priv->sdvo_mappings[0]);
2270 else
2271 mapping = &(dev_priv->sdvo_mappings[1]);
2272
2273 if (mapping->initialized)
2274 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2275 else
2276 intel_sdvo_guess_ddc_bus(sdvo);
2277 }
2278
2279 static void
2280 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2281 struct intel_sdvo *sdvo, u32 reg)
2282 {
2283 struct sdvo_device_mapping *mapping;
2284 u8 pin;
2285
2286 if (sdvo->is_sdvob)
2287 mapping = &dev_priv->sdvo_mappings[0];
2288 else
2289 mapping = &dev_priv->sdvo_mappings[1];
2290
2291 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
2292 pin = mapping->i2c_pin;
2293 else
2294 pin = GMBUS_PORT_DPB;
2295
2296 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2297
2298 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2299 * our code totally fails once we start using gmbus. Hence fall back to
2300 * bit banging for now. */
2301 intel_gmbus_force_bit(sdvo->i2c, true);
2302 }
2303
2304 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2305 static void
2306 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2307 {
2308 intel_gmbus_force_bit(sdvo->i2c, false);
2309 }
2310
2311 static bool
2312 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2313 {
2314 return intel_sdvo_check_supp_encode(intel_sdvo);
2315 }
2316
2317 static u8
2318 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
2319 {
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321 struct sdvo_device_mapping *my_mapping, *other_mapping;
2322
2323 if (sdvo->is_sdvob) {
2324 my_mapping = &dev_priv->sdvo_mappings[0];
2325 other_mapping = &dev_priv->sdvo_mappings[1];
2326 } else {
2327 my_mapping = &dev_priv->sdvo_mappings[1];
2328 other_mapping = &dev_priv->sdvo_mappings[0];
2329 }
2330
2331 /* If the BIOS described our SDVO device, take advantage of it. */
2332 if (my_mapping->slave_addr)
2333 return my_mapping->slave_addr;
2334
2335 /* If the BIOS only described a different SDVO device, use the
2336 * address that it isn't using.
2337 */
2338 if (other_mapping->slave_addr) {
2339 if (other_mapping->slave_addr == 0x70)
2340 return 0x72;
2341 else
2342 return 0x70;
2343 }
2344
2345 /* No SDVO device info is found for another DVO port,
2346 * so use mapping assumption we had before BIOS parsing.
2347 */
2348 if (sdvo->is_sdvob)
2349 return 0x70;
2350 else
2351 return 0x72;
2352 }
2353
2354 static void
2355 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2356 struct intel_sdvo *encoder)
2357 {
2358 drm_connector_init(encoder->base.base.dev,
2359 &connector->base.base,
2360 &intel_sdvo_connector_funcs,
2361 connector->base.base.connector_type);
2362
2363 drm_connector_helper_add(&connector->base.base,
2364 &intel_sdvo_connector_helper_funcs);
2365
2366 connector->base.base.interlace_allowed = 1;
2367 connector->base.base.doublescan_allowed = 0;
2368 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2369 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2370
2371 intel_connector_attach_encoder(&connector->base, &encoder->base);
2372 drm_sysfs_connector_add(&connector->base.base);
2373 }
2374
2375 static void
2376 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2377 struct intel_sdvo_connector *connector)
2378 {
2379 struct drm_device *dev = connector->base.base.dev;
2380
2381 intel_attach_force_audio_property(&connector->base.base);
2382 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2383 intel_attach_broadcast_rgb_property(&connector->base.base);
2384 intel_sdvo->color_range_auto = true;
2385 }
2386 }
2387
2388 static bool
2389 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2390 {
2391 struct drm_encoder *encoder = &intel_sdvo->base.base;
2392 struct drm_connector *connector;
2393 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2394 struct intel_connector *intel_connector;
2395 struct intel_sdvo_connector *intel_sdvo_connector;
2396
2397 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2398 if (!intel_sdvo_connector)
2399 return false;
2400
2401 if (device == 0) {
2402 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2403 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2404 } else if (device == 1) {
2405 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2406 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2407 }
2408
2409 intel_connector = &intel_sdvo_connector->base;
2410 connector = &intel_connector->base;
2411 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2412 intel_sdvo_connector->output_flag) {
2413 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2414 /* Some SDVO devices have one-shot hotplug interrupts.
2415 * Ensure that they get re-enabled when an interrupt happens.
2416 */
2417 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2418 intel_sdvo_enable_hotplug(intel_encoder);
2419 } else {
2420 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2421 }
2422 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2423 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2424
2425 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2426 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2427 intel_sdvo->is_hdmi = true;
2428 }
2429
2430 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2431 if (intel_sdvo->is_hdmi)
2432 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2433
2434 return true;
2435 }
2436
2437 static bool
2438 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2439 {
2440 struct drm_encoder *encoder = &intel_sdvo->base.base;
2441 struct drm_connector *connector;
2442 struct intel_connector *intel_connector;
2443 struct intel_sdvo_connector *intel_sdvo_connector;
2444
2445 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2446 if (!intel_sdvo_connector)
2447 return false;
2448
2449 intel_connector = &intel_sdvo_connector->base;
2450 connector = &intel_connector->base;
2451 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2452 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2453
2454 intel_sdvo->controlled_output |= type;
2455 intel_sdvo_connector->output_flag = type;
2456
2457 intel_sdvo->is_tv = true;
2458
2459 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2460
2461 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2462 goto err;
2463
2464 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2465 goto err;
2466
2467 return true;
2468
2469 err:
2470 intel_sdvo_destroy(connector);
2471 return false;
2472 }
2473
2474 static bool
2475 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2476 {
2477 struct drm_encoder *encoder = &intel_sdvo->base.base;
2478 struct drm_connector *connector;
2479 struct intel_connector *intel_connector;
2480 struct intel_sdvo_connector *intel_sdvo_connector;
2481
2482 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2483 if (!intel_sdvo_connector)
2484 return false;
2485
2486 intel_connector = &intel_sdvo_connector->base;
2487 connector = &intel_connector->base;
2488 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2489 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2490 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2491
2492 if (device == 0) {
2493 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2494 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2495 } else if (device == 1) {
2496 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2497 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2498 }
2499
2500 intel_sdvo_connector_init(intel_sdvo_connector,
2501 intel_sdvo);
2502 return true;
2503 }
2504
2505 static bool
2506 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2507 {
2508 struct drm_encoder *encoder = &intel_sdvo->base.base;
2509 struct drm_connector *connector;
2510 struct intel_connector *intel_connector;
2511 struct intel_sdvo_connector *intel_sdvo_connector;
2512
2513 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2514 if (!intel_sdvo_connector)
2515 return false;
2516
2517 intel_connector = &intel_sdvo_connector->base;
2518 connector = &intel_connector->base;
2519 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2520 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2521
2522 if (device == 0) {
2523 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2524 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2525 } else if (device == 1) {
2526 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2527 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2528 }
2529
2530 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2531 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2532 goto err;
2533
2534 return true;
2535
2536 err:
2537 intel_sdvo_destroy(connector);
2538 return false;
2539 }
2540
2541 static bool
2542 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2543 {
2544 intel_sdvo->is_tv = false;
2545 intel_sdvo->is_lvds = false;
2546
2547 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2548
2549 if (flags & SDVO_OUTPUT_TMDS0)
2550 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2551 return false;
2552
2553 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2554 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2555 return false;
2556
2557 /* TV has no XXX1 function block */
2558 if (flags & SDVO_OUTPUT_SVID0)
2559 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2560 return false;
2561
2562 if (flags & SDVO_OUTPUT_CVBS0)
2563 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2564 return false;
2565
2566 if (flags & SDVO_OUTPUT_YPRPB0)
2567 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2568 return false;
2569
2570 if (flags & SDVO_OUTPUT_RGB0)
2571 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2572 return false;
2573
2574 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2575 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2576 return false;
2577
2578 if (flags & SDVO_OUTPUT_LVDS0)
2579 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2580 return false;
2581
2582 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2583 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2584 return false;
2585
2586 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2587 unsigned char bytes[2];
2588
2589 intel_sdvo->controlled_output = 0;
2590 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2591 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2592 SDVO_NAME(intel_sdvo),
2593 bytes[0], bytes[1]);
2594 return false;
2595 }
2596 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2597
2598 return true;
2599 }
2600
2601 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2602 {
2603 struct drm_device *dev = intel_sdvo->base.base.dev;
2604 struct drm_connector *connector, *tmp;
2605
2606 list_for_each_entry_safe(connector, tmp,
2607 &dev->mode_config.connector_list, head) {
2608 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2609 intel_sdvo_destroy(connector);
2610 }
2611 }
2612
2613 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2614 struct intel_sdvo_connector *intel_sdvo_connector,
2615 int type)
2616 {
2617 struct drm_device *dev = intel_sdvo->base.base.dev;
2618 struct intel_sdvo_tv_format format;
2619 uint32_t format_map, i;
2620
2621 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2622 return false;
2623
2624 BUILD_BUG_ON(sizeof(format) != 6);
2625 if (!intel_sdvo_get_value(intel_sdvo,
2626 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2627 &format, sizeof(format)))
2628 return false;
2629
2630 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2631
2632 if (format_map == 0)
2633 return false;
2634
2635 intel_sdvo_connector->format_supported_num = 0;
2636 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2637 if (format_map & (1 << i))
2638 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2639
2640
2641 intel_sdvo_connector->tv_format =
2642 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2643 "mode", intel_sdvo_connector->format_supported_num);
2644 if (!intel_sdvo_connector->tv_format)
2645 return false;
2646
2647 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2648 drm_property_add_enum(
2649 intel_sdvo_connector->tv_format, i,
2650 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2651
2652 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2653 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2654 intel_sdvo_connector->tv_format, 0);
2655 return true;
2656
2657 }
2658
2659 #define ENHANCEMENT(name, NAME) do { \
2660 if (enhancements.name) { \
2661 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2662 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2663 return false; \
2664 intel_sdvo_connector->max_##name = data_value[0]; \
2665 intel_sdvo_connector->cur_##name = response; \
2666 intel_sdvo_connector->name = \
2667 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2668 if (!intel_sdvo_connector->name) return false; \
2669 drm_object_attach_property(&connector->base, \
2670 intel_sdvo_connector->name, \
2671 intel_sdvo_connector->cur_##name); \
2672 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2673 data_value[0], data_value[1], response); \
2674 } \
2675 } while (0)
2676
2677 static bool
2678 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2679 struct intel_sdvo_connector *intel_sdvo_connector,
2680 struct intel_sdvo_enhancements_reply enhancements)
2681 {
2682 struct drm_device *dev = intel_sdvo->base.base.dev;
2683 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2684 uint16_t response, data_value[2];
2685
2686 /* when horizontal overscan is supported, Add the left/right property */
2687 if (enhancements.overscan_h) {
2688 if (!intel_sdvo_get_value(intel_sdvo,
2689 SDVO_CMD_GET_MAX_OVERSCAN_H,
2690 &data_value, 4))
2691 return false;
2692
2693 if (!intel_sdvo_get_value(intel_sdvo,
2694 SDVO_CMD_GET_OVERSCAN_H,
2695 &response, 2))
2696 return false;
2697
2698 intel_sdvo_connector->max_hscan = data_value[0];
2699 intel_sdvo_connector->left_margin = data_value[0] - response;
2700 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2701 intel_sdvo_connector->left =
2702 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2703 if (!intel_sdvo_connector->left)
2704 return false;
2705
2706 drm_object_attach_property(&connector->base,
2707 intel_sdvo_connector->left,
2708 intel_sdvo_connector->left_margin);
2709
2710 intel_sdvo_connector->right =
2711 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2712 if (!intel_sdvo_connector->right)
2713 return false;
2714
2715 drm_object_attach_property(&connector->base,
2716 intel_sdvo_connector->right,
2717 intel_sdvo_connector->right_margin);
2718 DRM_DEBUG_KMS("h_overscan: max %d, "
2719 "default %d, current %d\n",
2720 data_value[0], data_value[1], response);
2721 }
2722
2723 if (enhancements.overscan_v) {
2724 if (!intel_sdvo_get_value(intel_sdvo,
2725 SDVO_CMD_GET_MAX_OVERSCAN_V,
2726 &data_value, 4))
2727 return false;
2728
2729 if (!intel_sdvo_get_value(intel_sdvo,
2730 SDVO_CMD_GET_OVERSCAN_V,
2731 &response, 2))
2732 return false;
2733
2734 intel_sdvo_connector->max_vscan = data_value[0];
2735 intel_sdvo_connector->top_margin = data_value[0] - response;
2736 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2737 intel_sdvo_connector->top =
2738 drm_property_create_range(dev, 0,
2739 "top_margin", 0, data_value[0]);
2740 if (!intel_sdvo_connector->top)
2741 return false;
2742
2743 drm_object_attach_property(&connector->base,
2744 intel_sdvo_connector->top,
2745 intel_sdvo_connector->top_margin);
2746
2747 intel_sdvo_connector->bottom =
2748 drm_property_create_range(dev, 0,
2749 "bottom_margin", 0, data_value[0]);
2750 if (!intel_sdvo_connector->bottom)
2751 return false;
2752
2753 drm_object_attach_property(&connector->base,
2754 intel_sdvo_connector->bottom,
2755 intel_sdvo_connector->bottom_margin);
2756 DRM_DEBUG_KMS("v_overscan: max %d, "
2757 "default %d, current %d\n",
2758 data_value[0], data_value[1], response);
2759 }
2760
2761 ENHANCEMENT(hpos, HPOS);
2762 ENHANCEMENT(vpos, VPOS);
2763 ENHANCEMENT(saturation, SATURATION);
2764 ENHANCEMENT(contrast, CONTRAST);
2765 ENHANCEMENT(hue, HUE);
2766 ENHANCEMENT(sharpness, SHARPNESS);
2767 ENHANCEMENT(brightness, BRIGHTNESS);
2768 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2769 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2770 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2771 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2772 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2773
2774 if (enhancements.dot_crawl) {
2775 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2776 return false;
2777
2778 intel_sdvo_connector->max_dot_crawl = 1;
2779 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2780 intel_sdvo_connector->dot_crawl =
2781 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2782 if (!intel_sdvo_connector->dot_crawl)
2783 return false;
2784
2785 drm_object_attach_property(&connector->base,
2786 intel_sdvo_connector->dot_crawl,
2787 intel_sdvo_connector->cur_dot_crawl);
2788 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2789 }
2790
2791 return true;
2792 }
2793
2794 static bool
2795 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2796 struct intel_sdvo_connector *intel_sdvo_connector,
2797 struct intel_sdvo_enhancements_reply enhancements)
2798 {
2799 struct drm_device *dev = intel_sdvo->base.base.dev;
2800 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2801 uint16_t response, data_value[2];
2802
2803 ENHANCEMENT(brightness, BRIGHTNESS);
2804
2805 return true;
2806 }
2807 #undef ENHANCEMENT
2808
2809 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2810 struct intel_sdvo_connector *intel_sdvo_connector)
2811 {
2812 union {
2813 struct intel_sdvo_enhancements_reply reply;
2814 uint16_t response;
2815 } enhancements;
2816
2817 BUILD_BUG_ON(sizeof(enhancements) != 2);
2818
2819 enhancements.response = 0;
2820 intel_sdvo_get_value(intel_sdvo,
2821 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2822 &enhancements, sizeof(enhancements));
2823 if (enhancements.response == 0) {
2824 DRM_DEBUG_KMS("No enhancement is supported\n");
2825 return true;
2826 }
2827
2828 if (IS_TV(intel_sdvo_connector))
2829 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2830 else if (IS_LVDS(intel_sdvo_connector))
2831 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2832 else
2833 return true;
2834 }
2835
2836 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2837 struct i2c_msg *msgs,
2838 int num)
2839 {
2840 struct intel_sdvo *sdvo = adapter->algo_data;
2841
2842 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2843 return -EIO;
2844
2845 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2846 }
2847
2848 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2849 {
2850 struct intel_sdvo *sdvo = adapter->algo_data;
2851 return sdvo->i2c->algo->functionality(sdvo->i2c);
2852 }
2853
2854 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2855 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2856 .functionality = intel_sdvo_ddc_proxy_func
2857 };
2858
2859 static bool
2860 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2861 struct drm_device *dev)
2862 {
2863 sdvo->ddc.owner = THIS_MODULE;
2864 sdvo->ddc.class = I2C_CLASS_DDC;
2865 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2866 sdvo->ddc.dev.parent = &dev->pdev->dev;
2867 sdvo->ddc.algo_data = sdvo;
2868 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2869
2870 return i2c_add_adapter(&sdvo->ddc) == 0;
2871 }
2872
2873 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2874 {
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_encoder *intel_encoder;
2877 struct intel_sdvo *intel_sdvo;
2878 int i;
2879 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2880 if (!intel_sdvo)
2881 return false;
2882
2883 intel_sdvo->sdvo_reg = sdvo_reg;
2884 intel_sdvo->is_sdvob = is_sdvob;
2885 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
2886 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
2887 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2888 goto err_i2c_bus;
2889
2890 /* encoder type will be decided later */
2891 intel_encoder = &intel_sdvo->base;
2892 intel_encoder->type = INTEL_OUTPUT_SDVO;
2893 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2894
2895 /* Read the regs to test if we can talk to the device */
2896 for (i = 0; i < 0x40; i++) {
2897 u8 byte;
2898
2899 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
2900 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2901 SDVO_NAME(intel_sdvo));
2902 goto err;
2903 }
2904 }
2905
2906 intel_encoder->compute_config = intel_sdvo_compute_config;
2907 intel_encoder->disable = intel_disable_sdvo;
2908 intel_encoder->mode_set = intel_sdvo_mode_set;
2909 intel_encoder->enable = intel_enable_sdvo;
2910 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
2911 intel_encoder->get_config = intel_sdvo_get_config;
2912
2913 /* In default case sdvo lvds is false */
2914 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2915 goto err;
2916
2917 if (intel_sdvo_output_setup(intel_sdvo,
2918 intel_sdvo->caps.output_flags) != true) {
2919 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2920 SDVO_NAME(intel_sdvo));
2921 /* Output_setup can leave behind connectors! */
2922 goto err_output;
2923 }
2924
2925 /* Only enable the hotplug irq if we need it, to work around noisy
2926 * hotplug lines.
2927 */
2928 if (intel_sdvo->hotplug_active) {
2929 intel_encoder->hpd_pin =
2930 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2931 }
2932
2933 /*
2934 * Cloning SDVO with anything is often impossible, since the SDVO
2935 * encoder can request a special input timing mode. And even if that's
2936 * not the case we have evidence that cloning a plain unscaled mode with
2937 * VGA doesn't really work. Furthermore the cloning flags are way too
2938 * simplistic anyway to express such constraints, so just give up on
2939 * cloning for SDVO encoders.
2940 */
2941 intel_sdvo->base.cloneable = false;
2942
2943 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2944
2945 /* Set the input timing to the screen. Assume always input 0. */
2946 if (!intel_sdvo_set_target_input(intel_sdvo))
2947 goto err_output;
2948
2949 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2950 &intel_sdvo->pixel_clock_min,
2951 &intel_sdvo->pixel_clock_max))
2952 goto err_output;
2953
2954 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2955 "clock range %dMHz - %dMHz, "
2956 "input 1: %c, input 2: %c, "
2957 "output 1: %c, output 2: %c\n",
2958 SDVO_NAME(intel_sdvo),
2959 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2960 intel_sdvo->caps.device_rev_id,
2961 intel_sdvo->pixel_clock_min / 1000,
2962 intel_sdvo->pixel_clock_max / 1000,
2963 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2964 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2965 /* check currently supported outputs */
2966 intel_sdvo->caps.output_flags &
2967 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2968 intel_sdvo->caps.output_flags &
2969 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2970 return true;
2971
2972 err_output:
2973 intel_sdvo_output_cleanup(intel_sdvo);
2974
2975 err:
2976 drm_encoder_cleanup(&intel_encoder->base);
2977 i2c_del_adapter(&intel_sdvo->ddc);
2978 err_i2c_bus:
2979 intel_sdvo_unselect_i2c_bus(intel_sdvo);
2980 kfree(intel_sdvo);
2981
2982 return false;
2983 }
Linux with added FPC-III support