drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  28
  29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  31
  32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  34
  35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  37
  38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  40
  41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  42
  43
  44 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  45 {
  46         u32 gt_thread_status_mask;
  47
  48         if (IS_HASWELL(dev_priv->dev))
  49                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
  50         else
  51                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
  52
  53         /* w/a for a sporadic read returning 0 by waiting for the GT
  54          * thread to wake up.
  55          */
  56         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
  57                 DRM_ERROR("GT thread status wait timed out\n");
  58 }
  59
  60 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
  61 {
  62         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
  63         /* something from same cacheline, but !FORCEWAKE */
  64         __raw_posting_read(dev_priv, ECOBUS);
  65 }
  66
  67 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  68 {
  69         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
  70                             FORCEWAKE_ACK_TIMEOUT_MS))
  71                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  72
  73         __raw_i915_write32(dev_priv, FORCEWAKE, 1);
  74         /* something from same cacheline, but !FORCEWAKE */
  75         __raw_posting_read(dev_priv, ECOBUS);
  76
  77         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
  78                             FORCEWAKE_ACK_TIMEOUT_MS))
  79                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  80
  81         /* WaRsForcewakeWaitTC0:snb */
  82         __gen6_gt_wait_for_thread_c0(dev_priv);
  83 }
  84
  85 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
  86 {
  87         __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
  88         /* something from same cacheline, but !FORCEWAKE_MT */
  89         __raw_posting_read(dev_priv, ECOBUS);
  90 }
  91
  92 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
  93 {
  94         u32 forcewake_ack;
  95
  96         if (IS_HASWELL(dev_priv->dev))
  97                 forcewake_ack = FORCEWAKE_ACK_HSW;
  98         else
  99                 forcewake_ack = FORCEWAKE_MT_ACK;
 100
 101         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
 102                             FORCEWAKE_ACK_TIMEOUT_MS))
 103                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 104
 105         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 106                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 107         /* something from same cacheline, but !FORCEWAKE_MT */
 108         __raw_posting_read(dev_priv, ECOBUS);
 109
 110         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
 111                             FORCEWAKE_ACK_TIMEOUT_MS))
 112                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 113
 114         /* WaRsForcewakeWaitTC0:ivb,hsw */
 115         __gen6_gt_wait_for_thread_c0(dev_priv);
 116 }
 117
 118 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 119 {
 120         u32 gtfifodbg;
 121
 122         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 123         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 124              "MMIO read or write has been dropped %x\n", gtfifodbg))
 125                 __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 126 }
 127
 128 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 129 {
 130         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
 131         /* something from same cacheline, but !FORCEWAKE */
 132         __raw_posting_read(dev_priv, ECOBUS);
 133         gen6_gt_check_fifodbg(dev_priv);
 134 }
 135
 136 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 137 {
 138         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 139                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 140         /* something from same cacheline, but !FORCEWAKE_MT */
 141         __raw_posting_read(dev_priv, ECOBUS);
 142         gen6_gt_check_fifodbg(dev_priv);
 143 }
 144
 145 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 146 {
 147         int ret = 0;
 148
 149         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 150                 int loop = 500;
 151                 u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
 152                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 153                         udelay(10);
 154                         fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
 155                 }
 156                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 157                         ++ret;
 158                 dev_priv->uncore.fifo_count = fifo;
 159         }
 160         dev_priv->uncore.fifo_count--;
 161
 162         return ret;
 163 }
 164
 165 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
 166 {
 167         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 168                            _MASKED_BIT_DISABLE(0xffff));
 169         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 170                            _MASKED_BIT_DISABLE(0xffff));
 171         /* something from same cacheline, but !FORCEWAKE_VLV */
 172         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 173 }
 174
 175 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 176 {
 177         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
 178                             FORCEWAKE_ACK_TIMEOUT_MS))
 179                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 180
 181         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 182                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 183         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 184                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 185
 186         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
 187                             FORCEWAKE_ACK_TIMEOUT_MS))
 188                 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
 189
 190         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) &
 191                              FORCEWAKE_KERNEL),
 192                             FORCEWAKE_ACK_TIMEOUT_MS))
 193                 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
 194
 195         /* WaRsForcewakeWaitTC0:vlv */
 196         __gen6_gt_wait_for_thread_c0(dev_priv);
 197 }
 198
 199 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 200 {
 201         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 202                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 203         __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 204                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 205         /* The below doubles as a POSTING_READ */
 206         gen6_gt_check_fifodbg(dev_priv);
 207 }
 208
 209 static void intel_uncore_forcewake_reset(struct drm_device *dev)
 210 {
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212
 213         if (IS_VALLEYVIEW(dev)) {
 214                 vlv_force_wake_reset(dev_priv);
 215         } else if (INTEL_INFO(dev)->gen >= 6) {
 216                 __gen6_gt_force_wake_reset(dev_priv);
 217                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 218                         __gen6_gt_force_wake_mt_reset(dev_priv);
 219         }
 220 }
 221
 222 void intel_uncore_early_sanitize(struct drm_device *dev)
 223 {
 224         struct drm_i915_private *dev_priv = dev->dev_private;
 225
 226         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 227                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 228 }
 229
 230 void intel_uncore_init(struct drm_device *dev)
 231 {
 232         struct drm_i915_private *dev_priv = dev->dev_private;
 233
 234         if (IS_VALLEYVIEW(dev)) {
 235                 dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get;
 236                 dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put;
 237         } else if (IS_HASWELL(dev)) {
 238                 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
 239                 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
 240         } else if (IS_IVYBRIDGE(dev)) {
 241                 u32 ecobus;
 242
 243                 /* IVB configs may use multi-threaded forcewake */
 244
 245                 /* A small trick here - if the bios hasn't configured
 246                  * MT forcewake, and if the device is in RC6, then
 247                  * force_wake_mt_get will not wake the device and the
 248                  * ECOBUS read will return zero. Which will be
 249                  * (correctly) interpreted by the test below as MT
 250                  * forcewake being disabled.
 251                  */
 252                 mutex_lock(&dev->struct_mutex);
 253                 __gen6_gt_force_wake_mt_get(dev_priv);
 254                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
 255                 __gen6_gt_force_wake_mt_put(dev_priv);
 256                 mutex_unlock(&dev->struct_mutex);
 257
 258                 if (ecobus & FORCEWAKE_MT_ENABLE) {
 259                         dev_priv->uncore.funcs.force_wake_get =
 260                                 __gen6_gt_force_wake_mt_get;
 261                         dev_priv->uncore.funcs.force_wake_put =
 262                                 __gen6_gt_force_wake_mt_put;
 263                 } else {
 264                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
 265                         DRM_INFO("when using vblank-synced partial screen updates.\n");
 266                         dev_priv->uncore.funcs.force_wake_get =
 267                                 __gen6_gt_force_wake_get;
 268                         dev_priv->uncore.funcs.force_wake_put =
 269                                 __gen6_gt_force_wake_put;
 270                 }
 271         } else if (IS_GEN6(dev)) {
 272                 dev_priv->uncore.funcs.force_wake_get =
 273                         __gen6_gt_force_wake_get;
 274                 dev_priv->uncore.funcs.force_wake_put =
 275                         __gen6_gt_force_wake_put;
 276         }
 277
 278         intel_uncore_forcewake_reset(dev);
 279 }
 280
 281 void intel_uncore_sanitize(struct drm_device *dev)
 282 {
 283         intel_uncore_forcewake_reset(dev);
 284
 285         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 286         intel_disable_gt_powersave(dev);
 287 }
 288
 289 /*
 290  * Generally this is called implicitly by the register read function. However,
 291  * if some sequence requires the GT to not power down then this function should
 292  * be called at the beginning of the sequence followed by a call to
 293  * gen6_gt_force_wake_put() at the end of the sequence.
 294  */
 295 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 296 {
 297         unsigned long irqflags;
 298
 299         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 300         if (dev_priv->uncore.forcewake_count++ == 0)
 301                 dev_priv->uncore.funcs.force_wake_get(dev_priv);
 302         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 303 }
 304
 305 /*
 306  * see gen6_gt_force_wake_get()
 307  */
 308 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 309 {
 310         unsigned long irqflags;
 311
 312         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 313         if (--dev_priv->uncore.forcewake_count == 0)
 314                 dev_priv->uncore.funcs.force_wake_put(dev_priv);
 315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 316 }
 317
 318 /* We give fast paths for the really cool registers */
 319 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 320         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
 321          ((reg) < 0x40000) &&            \
 322          ((reg) != FORCEWAKE))
 323
 324 static void
 325 ilk_dummy_write(struct drm_i915_private *dev_priv)
 326 {
 327         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 328          * the chip from rc6 before touching it for real. MI_MODE is masked,
 329          * hence harmless to write 0 into. */
 330         __raw_i915_write32(dev_priv, MI_MODE, 0);
 331 }
 332
 333 static void
 334 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
 335 {
 336         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
 337             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
 338                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
 339                           reg);
 340                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 341         }
 342 }
 343
 344 static void
 345 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
 346 {
 347         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
 348             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
 349                 DRM_ERROR("Unclaimed write to %x\n", reg);
 350                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 351         }
 352 }
 353
 354 #define __i915_read(x) \
 355 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \
 356         unsigned long irqflags; \
 357         u##x val = 0; \
 358         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 359         if (dev_priv->info->gen == 5) \
 360                 ilk_dummy_write(dev_priv); \
 361         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 362                 if (dev_priv->uncore.forcewake_count == 0) \
 363                         dev_priv->uncore.funcs.force_wake_get(dev_priv); \
 364                 val = __raw_i915_read##x(dev_priv, reg); \
 365                 if (dev_priv->uncore.forcewake_count == 0) \
 366                         dev_priv->uncore.funcs.force_wake_put(dev_priv); \
 367         } else { \
 368                 val = __raw_i915_read##x(dev_priv, reg); \
 369         } \
 370         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 371         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 372         return val; \
 373 }
 374
 375 __i915_read(8)
 376 __i915_read(16)
 377 __i915_read(32)
 378 __i915_read(64)
 379 #undef __i915_read
 380
 381 #define __i915_write(x) \
 382 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace) { \
 383         unsigned long irqflags; \
 384         u32 __fifo_ret = 0; \
 385         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 386         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 387         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 388                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 389         } \
 390         if (dev_priv->info->gen == 5) \
 391                 ilk_dummy_write(dev_priv); \
 392         hsw_unclaimed_reg_clear(dev_priv, reg); \
 393         __raw_i915_write##x(dev_priv, reg, val); \
 394         if (unlikely(__fifo_ret)) { \
 395                 gen6_gt_check_fifodbg(dev_priv); \
 396         } \
 397         hsw_unclaimed_reg_check(dev_priv, reg); \
 398         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 399 }
 400 __i915_write(8)
 401 __i915_write(16)
 402 __i915_write(32)
 403 __i915_write(64)
 404 #undef __i915_write
 405
 406 static const struct register_whitelist {
 407         uint64_t offset;
 408         uint32_t size;
 409         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
 410 } whitelist[] = {
 411         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
 412 };
 413
 414 int i915_reg_read_ioctl(struct drm_device *dev,
 415                         void *data, struct drm_file *file)
 416 {
 417         struct drm_i915_private *dev_priv = dev->dev_private;
 418         struct drm_i915_reg_read *reg = data;
 419         struct register_whitelist const *entry = whitelist;
 420         int i;
 421
 422         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
 423                 if (entry->offset == reg->offset &&
 424                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
 425                         break;
 426         }
 427
 428         if (i == ARRAY_SIZE(whitelist))
 429                 return -EINVAL;
 430
 431         switch (entry->size) {
 432         case 8:
 433                 reg->val = I915_READ64(reg->offset);
 434                 break;
 435         case 4:
 436                 reg->val = I915_READ(reg->offset);
 437                 break;
 438         case 2:
 439                 reg->val = I915_READ16(reg->offset);
 440                 break;
 441         case 1:
 442                 reg->val = I915_READ8(reg->offset);
 443                 break;
 444         default:
 445                 WARN_ON(1);
 446                 return -EINVAL;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int i8xx_do_reset(struct drm_device *dev)
 453 {
 454         struct drm_i915_private *dev_priv = dev->dev_private;
 455
 456         if (IS_I85X(dev))
 457                 return -ENODEV;
 458
 459         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 460         POSTING_READ(D_STATE);
 461
 462         if (IS_I830(dev) || IS_845G(dev)) {
 463                 I915_WRITE(DEBUG_RESET_I830,
 464                            DEBUG_RESET_DISPLAY |
 465                            DEBUG_RESET_RENDER |
 466                            DEBUG_RESET_FULL);
 467                 POSTING_READ(DEBUG_RESET_I830);
 468                 msleep(1);
 469
 470                 I915_WRITE(DEBUG_RESET_I830, 0);
 471                 POSTING_READ(DEBUG_RESET_I830);
 472         }
 473
 474         msleep(1);
 475
 476         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 477         POSTING_READ(D_STATE);
 478
 479         return 0;
 480 }
 481
 482 static int i965_reset_complete(struct drm_device *dev)
 483 {
 484         u8 gdrst;
 485         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 486         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 487 }
 488
 489 static int i965_do_reset(struct drm_device *dev)
 490 {
 491         int ret;
 492
 493         /*
 494          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 495          * well as the reset bit (GR/bit 0).  Setting the GR bit
 496          * triggers the reset; when done, the hardware will clear it.
 497          */
 498         pci_write_config_byte(dev->pdev, I965_GDRST,
 499                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 500         ret =  wait_for(i965_reset_complete(dev), 500);
 501         if (ret)
 502                 return ret;
 503
 504         /* We can't reset render&media without also resetting display ... */
 505         pci_write_config_byte(dev->pdev, I965_GDRST,
 506                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 507
 508         ret =  wait_for(i965_reset_complete(dev), 500);
 509         if (ret)
 510                 return ret;
 511
 512         pci_write_config_byte(dev->pdev, I965_GDRST, 0);
 513
 514         return 0;
 515 }
 516
 517 static int ironlake_do_reset(struct drm_device *dev)
 518 {
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         u32 gdrst;
 521         int ret;
 522
 523         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 524         gdrst &= ~GRDOM_MASK;
 525         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 526                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 527         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 528         if (ret)
 529                 return ret;
 530
 531         /* We can't reset render&media without also resetting display ... */
 532         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 533         gdrst &= ~GRDOM_MASK;
 534         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 535                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 536         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 537 }
 538
 539 static int gen6_do_reset(struct drm_device *dev)
 540 {
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         int     ret;
 543         unsigned long irqflags;
 544
 545         /* Hold uncore.lock across reset to prevent any register access
 546          * with forcewake not set correctly
 547          */
 548         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 549
 550         /* Reset the chip */
 551
 552         /* GEN6_GDRST is not in the gt power well, no need to check
 553          * for fifo space for the write or forcewake the chip for
 554          * the read
 555          */
 556         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
 557
 558         /* Spin waiting for the device to ack the reset request */
 559         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 560
 561         intel_uncore_forcewake_reset(dev);
 562
 563         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 564         if (dev_priv->uncore.forcewake_count)
 565                 dev_priv->uncore.funcs.force_wake_get(dev_priv);
 566         else
 567                 dev_priv->uncore.funcs.force_wake_put(dev_priv);
 568
 569         /* Restore fifo count */
 570         dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
 571
 572         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 573         return ret;
 574 }
 575
 576 int intel_gpu_reset(struct drm_device *dev)
 577 {
 578         switch (INTEL_INFO(dev)->gen) {
 579         case 7:
 580         case 6: return gen6_do_reset(dev);
 581         case 5: return ironlake_do_reset(dev);
 582         case 4: return i965_do_reset(dev);
 583         case 2: return i8xx_do_reset(dev);
 584         default: return -ENODEV;
 585         }
 586 }
 587
 588 void intel_uncore_clear_errors(struct drm_device *dev)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591
 592         /* XXX needs spinlock around caller's grouping */
 593         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 594                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 595 }
 596
 597 void intel_uncore_check_errors(struct drm_device *dev)
 598 {
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600
 601         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
 602             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
 603                 DRM_ERROR("Unclaimed register before interrupt\n");
 604                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 605         }
 606 }