drivers/gpu/drm/msm/mdp4/mdp4_kms.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __MDP4_KMS_H__
  19 #define __MDP4_KMS_H__
  20
  21 #include <linux/clk.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 #include "msm_drv.h"
  26 #include "mdp4.xml.h"
  27
  28
  29 /* For transiently registering for different MDP4 irqs that various parts
  30  * of the KMS code need during setup/configuration.  We these are not
  31  * necessarily the same as what drm_vblank_get/put() are requesting, and
  32  * the hysteresis in drm_vblank_put() is not necessarily desirable for
  33  * internal housekeeping related irq usage.
  34  */
  35 struct mdp4_irq {
  36         struct list_head node;
  37         uint32_t irqmask;
  38         bool registered;
  39         void (*irq)(struct mdp4_irq *irq, uint32_t irqstatus);
  40 };
  41
  42 struct mdp4_kms {
  43         struct msm_kms base;
  44
  45         struct drm_device *dev;
  46
  47         int rev;
  48
  49         /* mapper-id used to request GEM buffer mapped for scanout: */
  50         int id;
  51
  52         void __iomem *mmio;
  53
  54         struct regulator *dsi_pll_vdda;
  55         struct regulator *dsi_pll_vddio;
  56         struct regulator *vdd;
  57
  58         struct clk *clk;
  59         struct clk *pclk;
  60         struct clk *lut_clk;
  61
  62         /* irq handling: */
  63         bool in_irq;
  64         struct list_head irq_list;    /* list of mdp4_irq */
  65         uint32_t vblank_mask;         /* irq bits set for userspace vblank */
  66         struct mdp4_irq error_handler;
  67 };
  68 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
  69
  70 /* platform config data (ie. from DT, or pdata) */
  71 struct mdp4_platform_config {
  72         struct iommu_domain *iommu;
  73         uint32_t max_clk;
  74 };
  75
  76 struct mdp4_format {
  77         struct msm_format base;
  78         enum mpd4_bpc bpc_r, bpc_g, bpc_b;
  79         enum mpd4_bpc_alpha bpc_a;
  80         uint8_t unpack[4];
  81         bool alpha_enable, unpack_tight;
  82         uint8_t cpp, unpack_count;
  83 };
  84 #define to_mdp4_format(x) container_of(x, struct mdp4_format, base)
  85
  86 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
  87 {
  88         msm_writel(data, mdp4_kms->mmio + reg);
  89 }
  90
  91 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
  92 {
  93         return msm_readl(mdp4_kms->mmio + reg);
  94 }
  95
  96 static inline uint32_t pipe2flush(enum mpd4_pipe pipe)
  97 {
  98         switch (pipe) {
  99         case VG1:      return MDP4_OVERLAY_FLUSH_VG1;
 100         case VG2:      return MDP4_OVERLAY_FLUSH_VG2;
 101         case RGB1:     return MDP4_OVERLAY_FLUSH_RGB1;
 102         case RGB2:     return MDP4_OVERLAY_FLUSH_RGB1;
 103         default:       return 0;
 104         }
 105 }
 106
 107 static inline uint32_t ovlp2flush(int ovlp)
 108 {
 109         switch (ovlp) {
 110         case 0:        return MDP4_OVERLAY_FLUSH_OVLP0;
 111         case 1:        return MDP4_OVERLAY_FLUSH_OVLP1;
 112         default:       return 0;
 113         }
 114 }
 115
 116 static inline uint32_t dma2irq(enum mdp4_dma dma)
 117 {
 118         switch (dma) {
 119         case DMA_P:    return MDP4_IRQ_DMA_P_DONE;
 120         case DMA_S:    return MDP4_IRQ_DMA_S_DONE;
 121         case DMA_E:    return MDP4_IRQ_DMA_E_DONE;
 122         default:       return 0;
 123         }
 124 }
 125
 126 static inline uint32_t dma2err(enum mdp4_dma dma)
 127 {
 128         switch (dma) {
 129         case DMA_P:    return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
 130         case DMA_S:    return 0;  // ???
 131         case DMA_E:    return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
 132         default:       return 0;
 133         }
 134 }
 135
 136 int mdp4_disable(struct mdp4_kms *mdp4_kms);
 137 int mdp4_enable(struct mdp4_kms *mdp4_kms);
 138
 139 void mdp4_irq_preinstall(struct msm_kms *kms);
 140 int mdp4_irq_postinstall(struct msm_kms *kms);
 141 void mdp4_irq_uninstall(struct msm_kms *kms);
 142 irqreturn_t mdp4_irq(struct msm_kms *kms);
 143 void mdp4_irq_wait(struct mdp4_kms *mdp4_kms, uint32_t irqmask);
 144 void mdp4_irq_register(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
 145 void mdp4_irq_unregister(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
 146 int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 147 void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 148
 149 const struct msm_format *mdp4_get_format(struct msm_kms *kms, uint32_t format);
 150
 151 void mdp4_plane_install_properties(struct drm_plane *plane,
 152                 struct drm_mode_object *obj);
 153 void mdp4_plane_set_scanout(struct drm_plane *plane,
 154                 struct drm_framebuffer *fb);
 155 int mdp4_plane_mode_set(struct drm_plane *plane,
 156                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 157                 int crtc_x, int crtc_y,
 158                 unsigned int crtc_w, unsigned int crtc_h,
 159                 uint32_t src_x, uint32_t src_y,
 160                 uint32_t src_w, uint32_t src_h);
 161 enum mpd4_pipe mdp4_plane_pipe(struct drm_plane *plane);
 162 struct drm_plane *mdp4_plane_init(struct drm_device *dev,
 163                 enum mpd4_pipe pipe_id, bool private_plane);
 164
 165 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
 166 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc);
 167 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
 168 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf);
 169 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
 170                 struct drm_plane *plane, int id, int ovlp_id,
 171                 enum mdp4_dma dma_id);
 172
 173 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
 174 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
 175
 176 #ifdef CONFIG_MSM_BUS_SCALING
 177 static inline int match_dev_name(struct device *dev, void *data)
 178 {
 179         return !strcmp(dev_name(dev), data);
 180 }
 181 /* bus scaling data is associated with extra pointless platform devices,
 182  * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
 183  * to find their pdata to make the bus-scaling stuff work.
 184  */
 185 static inline void *mdp4_find_pdata(const char *devname)
 186 {
 187         struct device *dev;
 188         dev = bus_find_device(&platform_bus_type, NULL,
 189                         (void *)devname, match_dev_name);
 190         return dev ? dev->platform_data : NULL;
 191 }
 192 #endif
 193
 194 #endif /* __MDP4_KMS_H__ */