drivers/gpu/drm/msm/msm_drv.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __MSM_DRV_H__
  19 #define __MSM_DRV_H__
  20
  21 #include <linux/kernel.h>
  22 #include <linux/clk.h>
  23 #include <linux/cpufreq.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/slab.h>
  29 #include <linux/list.h>
  30 #include <linux/iommu.h>
  31 #include <linux/types.h>
  32 #include <asm/sizes.h>
  33
  34 #ifndef CONFIG_OF
  35 #include <mach/board.h>
  36 #include <mach/socinfo.h>
  37 #include <mach/iommu_domains.h>
  38 #endif
  39
  40 #include <drm/drmP.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_fb_helper.h>
  43 #include <drm/msm_drm.h>
  44
  45 struct msm_kms;
  46 struct msm_gpu;
  47
  48 #define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */
  49
  50 struct msm_file_private {
  51         /* currently we don't do anything useful with this.. but when
  52          * per-context address spaces are supported we'd keep track of
  53          * the context's page-tables here.
  54          */
  55         int dummy;
  56 };
  57
  58 struct msm_drm_private {
  59
  60         struct msm_kms *kms;
  61
  62         /* when we have more than one 'msm_gpu' these need to be an array: */
  63         struct msm_gpu *gpu;
  64         struct msm_file_private *lastctx;
  65
  66         struct drm_fb_helper *fbdev;
  67
  68         uint32_t next_fence, completed_fence;
  69         wait_queue_head_t fence_event;
  70
  71         /* list of GEM objects: */
  72         struct list_head inactive_list;
  73
  74         struct workqueue_struct *wq;
  75
  76         /* registered IOMMU domains: */
  77         unsigned int num_iommus;
  78         struct iommu_domain *iommus[NUM_DOMAINS];
  79
  80         unsigned int num_crtcs;
  81         struct drm_crtc *crtcs[8];
  82
  83         unsigned int num_encoders;
  84         struct drm_encoder *encoders[8];
  85
  86         unsigned int num_bridges;
  87         struct drm_bridge *bridges[8];
  88
  89         unsigned int num_connectors;
  90         struct drm_connector *connectors[8];
  91 };
  92
  93 struct msm_format {
  94         uint32_t pixel_format;
  95 };
  96
  97 /* As there are different display controller blocks depending on the
  98  * snapdragon version, the kms support is split out and the appropriate
  99  * implementation is loaded at runtime.  The kms module is responsible
 100  * for constructing the appropriate planes/crtcs/encoders/connectors.
 101  */
 102 struct msm_kms_funcs {
 103         /* hw initialization: */
 104         int (*hw_init)(struct msm_kms *kms);
 105         /* irq handling: */
 106         void (*irq_preinstall)(struct msm_kms *kms);
 107         int (*irq_postinstall)(struct msm_kms *kms);
 108         void (*irq_uninstall)(struct msm_kms *kms);
 109         irqreturn_t (*irq)(struct msm_kms *kms);
 110         int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
 111         void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
 112         /* misc: */
 113         const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
 114         long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
 115                         struct drm_encoder *encoder);
 116         /* cleanup: */
 117         void (*preclose)(struct msm_kms *kms, struct drm_file *file);
 118         void (*destroy)(struct msm_kms *kms);
 119 };
 120
 121 struct msm_kms {
 122         const struct msm_kms_funcs *funcs;
 123 };
 124
 125 struct msm_kms *mdp4_kms_init(struct drm_device *dev);
 126
 127 int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu);
 128 int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu,
 129                 const char **names, int cnt);
 130
 131 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
 132                 struct timespec *timeout);
 133 void msm_update_fence(struct drm_device *dev, uint32_t fence);
 134
 135 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
 136                 struct drm_file *file);
 137
 138 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
 139 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 140 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
 141 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
 142                 uint32_t *iova);
 143 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
 144 void msm_gem_put_iova(struct drm_gem_object *obj, int id);
 145 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 146                 struct drm_mode_create_dumb *args);
 147 int msm_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 148                 uint32_t handle);
 149 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
 150                 uint32_t handle, uint64_t *offset);
 151 void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
 152 void *msm_gem_vaddr(struct drm_gem_object *obj);
 153 int msm_gem_queue_inactive_work(struct drm_gem_object *obj,
 154                 struct work_struct *work);
 155 void msm_gem_move_to_active(struct drm_gem_object *obj,
 156                 struct msm_gpu *gpu, bool write, uint32_t fence);
 157 void msm_gem_move_to_inactive(struct drm_gem_object *obj);
 158 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
 159                 struct timespec *timeout);
 160 int msm_gem_cpu_fini(struct drm_gem_object *obj);
 161 void msm_gem_free_object(struct drm_gem_object *obj);
 162 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
 163                 uint32_t size, uint32_t flags, uint32_t *handle);
 164 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
 165                 uint32_t size, uint32_t flags);
 166
 167 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
 168 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
 169 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
 170                 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
 171 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
 172                 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
 173
 174 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
 175
 176 int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
 177 void __init hdmi_register(void);
 178 void __exit hdmi_unregister(void);
 179
 180 #ifdef CONFIG_DEBUG_FS
 181 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
 182 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
 183 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
 184 #endif
 185
 186 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 187                 const char *dbgname);
 188 void msm_writel(u32 data, void __iomem *addr);
 189 u32 msm_readl(const void __iomem *addr);
 190
 191 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 192 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 193
 194 static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
 195 {
 196         struct msm_drm_private *priv = dev->dev_private;
 197         return priv->completed_fence >= fence;
 198 }
 199
 200 static inline int align_pitch(int width, int bpp)
 201 {
 202         int bytespp = (bpp + 7) / 8;
 203         /* adreno needs pitch aligned to 32 pixels: */
 204         return bytespp * ALIGN(width, 32);
 205 }
 206
 207 /* for the generated headers: */
 208 #define INVALID_IDX(idx) ({BUG(); 0;})
 209 #define fui(x)                ({BUG(); 0;})
 210 #define util_float_to_half(x) ({BUG(); 0;})
 211
 212
 213 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
 214
 215 /* for conditionally setting boolean flag(s): */
 216 #define COND(bool, val) ((bool) ? (val) : 0)
 217
 218
 219 #endif /* __MSM_DRV_H__ */