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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
blob60a97b6b908cb40265edd8193d2541743cee3e1e
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <core/engine.h>
31 #include <linux/swiotlb.h>
32
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35 #include <subdev/bar.h>
36
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_fence.h"
40
41 #include "nouveau_bo.h"
42 #include "nouveau_ttm.h"
43 #include "nouveau_gem.h"
44
45 /*
46 * NV10-NV40 tiling helpers
47 */
48
49 static void
50 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
51 u32 addr, u32 size, u32 pitch, u32 flags)
52 {
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 int i = reg - drm->tile.reg;
55 struct nouveau_fb *pfb = nouveau_fb(drm->device);
56 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
57 struct nouveau_engine *engine;
58
59 nouveau_fence_unref(&reg->fence);
60
61 if (tile->pitch)
62 pfb->tile.fini(pfb, i, tile);
63
64 if (pitch)
65 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66
67 pfb->tile.prog(pfb, i, tile);
68
69 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
70 engine->tile_prog(engine, i);
71 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
72 engine->tile_prog(engine, i);
73 }
74
75 static struct nouveau_drm_tile *
76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 {
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91 }
92
93 static void
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct nouveau_fence *fence)
96 {
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 if (fence) {
102 /* Mark it as pending. */
103 tile->fence = fence;
104 nouveau_fence_ref(fence);
105 }
106
107 tile->used = false;
108 spin_unlock(&drm->tile.lock);
109 }
110 }
111
112 static struct nouveau_drm_tile *
113 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
114 u32 size, u32 pitch, u32 flags)
115 {
116 struct nouveau_drm *drm = nouveau_drm(dev);
117 struct nouveau_fb *pfb = nouveau_fb(drm->device);
118 struct nouveau_drm_tile *tile, *found = NULL;
119 int i;
120
121 for (i = 0; i < pfb->tile.regions; i++) {
122 tile = nv10_bo_get_tile_region(dev, i);
123
124 if (pitch && !found) {
125 found = tile;
126 continue;
127
128 } else if (tile && pfb->tile.region[i].pitch) {
129 /* Kill an unused tile region. */
130 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
131 }
132
133 nv10_bo_put_tile_region(dev, tile, NULL);
134 }
135
136 if (found)
137 nv10_bo_update_tile_region(dev, found, addr, size,
138 pitch, flags);
139 return found;
140 }
141
142 static void
143 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
144 {
145 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
146 struct drm_device *dev = drm->dev;
147 struct nouveau_bo *nvbo = nouveau_bo(bo);
148
149 if (unlikely(nvbo->gem))
150 DRM_ERROR("bo %p still attached to GEM object\n", bo);
151 WARN_ON(nvbo->pin_refcnt > 0);
152 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
153 kfree(nvbo);
154 }
155
156 static void
157 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
158 int *align, int *size)
159 {
160 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
161 struct nouveau_device *device = nv_device(drm->device);
162
163 if (device->card_type < NV_50) {
164 if (nvbo->tile_mode) {
165 if (device->chipset >= 0x40) {
166 *align = 65536;
167 *size = roundup(*size, 64 * nvbo->tile_mode);
168
169 } else if (device->chipset >= 0x30) {
170 *align = 32768;
171 *size = roundup(*size, 64 * nvbo->tile_mode);
172
173 } else if (device->chipset >= 0x20) {
174 *align = 16384;
175 *size = roundup(*size, 64 * nvbo->tile_mode);
176
177 } else if (device->chipset >= 0x10) {
178 *align = 16384;
179 *size = roundup(*size, 32 * nvbo->tile_mode);
180 }
181 }
182 } else {
183 *size = roundup(*size, (1 << nvbo->page_shift));
184 *align = max((1 << nvbo->page_shift), *align);
185 }
186
187 *size = roundup(*size, PAGE_SIZE);
188 }
189
190 int
191 nouveau_bo_new(struct drm_device *dev, int size, int align,
192 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
193 struct sg_table *sg,
194 struct nouveau_bo **pnvbo)
195 {
196 struct nouveau_drm *drm = nouveau_drm(dev);
197 struct nouveau_bo *nvbo;
198 size_t acc_size;
199 int ret;
200 int type = ttm_bo_type_device;
201 int lpg_shift = 12;
202 int max_size;
203
204 if (drm->client.base.vm)
205 lpg_shift = drm->client.base.vm->vmm->lpg_shift;
206 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
207
208 if (size <= 0 || size > max_size) {
209 nv_warn(drm, "skipped size %x\n", (u32)size);
210 return -EINVAL;
211 }
212
213 if (sg)
214 type = ttm_bo_type_sg;
215
216 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
217 if (!nvbo)
218 return -ENOMEM;
219 INIT_LIST_HEAD(&nvbo->head);
220 INIT_LIST_HEAD(&nvbo->entry);
221 INIT_LIST_HEAD(&nvbo->vma_list);
222 nvbo->tile_mode = tile_mode;
223 nvbo->tile_flags = tile_flags;
224 nvbo->bo.bdev = &drm->ttm.bdev;
225
226 nvbo->page_shift = 12;
227 if (drm->client.base.vm) {
228 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
229 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
230 }
231
232 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
233 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
234 nouveau_bo_placement_set(nvbo, flags, 0);
235
236 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
237 sizeof(struct nouveau_bo));
238
239 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
240 type, &nvbo->placement,
241 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
242 nouveau_bo_del_ttm);
243 if (ret) {
244 /* ttm will call nouveau_bo_del_ttm if it fails.. */
245 return ret;
246 }
247
248 *pnvbo = nvbo;
249 return 0;
250 }
251
252 static void
253 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
254 {
255 *n = 0;
256
257 if (type & TTM_PL_FLAG_VRAM)
258 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
259 if (type & TTM_PL_FLAG_TT)
260 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
261 if (type & TTM_PL_FLAG_SYSTEM)
262 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
263 }
264
265 static void
266 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
267 {
268 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
269 struct nouveau_fb *pfb = nouveau_fb(drm->device);
270 u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
271
272 if (nv_device(drm->device)->card_type == NV_10 &&
273 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
274 nvbo->bo.mem.num_pages < vram_pages / 4) {
275 /*
276 * Make sure that the color and depth buffers are handled
277 * by independent memory controller units. Up to a 9x
278 * speed up when alpha-blending and depth-test are enabled
279 * at the same time.
280 */
281 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
282 nvbo->placement.fpfn = vram_pages / 2;
283 nvbo->placement.lpfn = ~0;
284 } else {
285 nvbo->placement.fpfn = 0;
286 nvbo->placement.lpfn = vram_pages / 2;
287 }
288 }
289 }
290
291 void
292 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
293 {
294 struct ttm_placement *pl = &nvbo->placement;
295 uint32_t flags = TTM_PL_MASK_CACHING |
296 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
297
298 pl->placement = nvbo->placements;
299 set_placement_list(nvbo->placements, &pl->num_placement,
300 type, flags);
301
302 pl->busy_placement = nvbo->busy_placements;
303 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
304 type | busy, flags);
305
306 set_placement_range(nvbo, type);
307 }
308
309 int
310 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
311 {
312 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
313 struct ttm_buffer_object *bo = &nvbo->bo;
314 int ret;
315
316 ret = ttm_bo_reserve(bo, false, false, false, 0);
317 if (ret)
318 goto out;
319
320 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
321 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
322 1 << bo->mem.mem_type, memtype);
323 ret = -EINVAL;
324 goto out;
325 }
326
327 if (nvbo->pin_refcnt++)
328 goto out;
329
330 nouveau_bo_placement_set(nvbo, memtype, 0);
331
332 ret = nouveau_bo_validate(nvbo, false, false);
333 if (ret == 0) {
334 switch (bo->mem.mem_type) {
335 case TTM_PL_VRAM:
336 drm->gem.vram_available -= bo->mem.size;
337 break;
338 case TTM_PL_TT:
339 drm->gem.gart_available -= bo->mem.size;
340 break;
341 default:
342 break;
343 }
344 }
345 out:
346 ttm_bo_unreserve(bo);
347 return ret;
348 }
349
350 int
351 nouveau_bo_unpin(struct nouveau_bo *nvbo)
352 {
353 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
354 struct ttm_buffer_object *bo = &nvbo->bo;
355 int ret, ref;
356
357 ret = ttm_bo_reserve(bo, false, false, false, 0);
358 if (ret)
359 return ret;
360
361 ref = --nvbo->pin_refcnt;
362 WARN_ON_ONCE(ref < 0);
363 if (ref)
364 goto out;
365
366 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
367
368 ret = nouveau_bo_validate(nvbo, false, false);
369 if (ret == 0) {
370 switch (bo->mem.mem_type) {
371 case TTM_PL_VRAM:
372 drm->gem.vram_available += bo->mem.size;
373 break;
374 case TTM_PL_TT:
375 drm->gem.gart_available += bo->mem.size;
376 break;
377 default:
378 break;
379 }
380 }
381
382 out:
383 ttm_bo_unreserve(bo);
384 return ret;
385 }
386
387 int
388 nouveau_bo_map(struct nouveau_bo *nvbo)
389 {
390 int ret;
391
392 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
393 if (ret)
394 return ret;
395
396 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
397 ttm_bo_unreserve(&nvbo->bo);
398 return ret;
399 }
400
401 void
402 nouveau_bo_unmap(struct nouveau_bo *nvbo)
403 {
404 if (nvbo)
405 ttm_bo_kunmap(&nvbo->kmap);
406 }
407
408 int
409 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
410 bool no_wait_gpu)
411 {
412 int ret;
413
414 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
415 interruptible, no_wait_gpu);
416 if (ret)
417 return ret;
418
419 return 0;
420 }
421
422 u16
423 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
424 {
425 bool is_iomem;
426 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
427 mem = &mem[index];
428 if (is_iomem)
429 return ioread16_native((void __force __iomem *)mem);
430 else
431 return *mem;
432 }
433
434 void
435 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
436 {
437 bool is_iomem;
438 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
439 mem = &mem[index];
440 if (is_iomem)
441 iowrite16_native(val, (void __force __iomem *)mem);
442 else
443 *mem = val;
444 }
445
446 u32
447 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
448 {
449 bool is_iomem;
450 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
451 mem = &mem[index];
452 if (is_iomem)
453 return ioread32_native((void __force __iomem *)mem);
454 else
455 return *mem;
456 }
457
458 void
459 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
460 {
461 bool is_iomem;
462 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
463 mem = &mem[index];
464 if (is_iomem)
465 iowrite32_native(val, (void __force __iomem *)mem);
466 else
467 *mem = val;
468 }
469
470 static struct ttm_tt *
471 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
472 uint32_t page_flags, struct page *dummy_read)
473 {
474 #if __OS_HAS_AGP
475 struct nouveau_drm *drm = nouveau_bdev(bdev);
476 struct drm_device *dev = drm->dev;
477
478 if (drm->agp.stat == ENABLED) {
479 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
480 page_flags, dummy_read);
481 }
482 #endif
483
484 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
485 }
486
487 static int
488 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
489 {
490 /* We'll do this from user space. */
491 return 0;
492 }
493
494 static int
495 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
496 struct ttm_mem_type_manager *man)
497 {
498 struct nouveau_drm *drm = nouveau_bdev(bdev);
499
500 switch (type) {
501 case TTM_PL_SYSTEM:
502 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
503 man->available_caching = TTM_PL_MASK_CACHING;
504 man->default_caching = TTM_PL_FLAG_CACHED;
505 break;
506 case TTM_PL_VRAM:
507 if (nv_device(drm->device)->card_type >= NV_50) {
508 man->func = &nouveau_vram_manager;
509 man->io_reserve_fastpath = false;
510 man->use_io_reserve_lru = true;
511 } else {
512 man->func = &ttm_bo_manager_func;
513 }
514 man->flags = TTM_MEMTYPE_FLAG_FIXED |
515 TTM_MEMTYPE_FLAG_MAPPABLE;
516 man->available_caching = TTM_PL_FLAG_UNCACHED |
517 TTM_PL_FLAG_WC;
518 man->default_caching = TTM_PL_FLAG_WC;
519 break;
520 case TTM_PL_TT:
521 if (nv_device(drm->device)->card_type >= NV_50)
522 man->func = &nouveau_gart_manager;
523 else
524 if (drm->agp.stat != ENABLED)
525 man->func = &nv04_gart_manager;
526 else
527 man->func = &ttm_bo_manager_func;
528
529 if (drm->agp.stat == ENABLED) {
530 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
531 man->available_caching = TTM_PL_FLAG_UNCACHED |
532 TTM_PL_FLAG_WC;
533 man->default_caching = TTM_PL_FLAG_WC;
534 } else {
535 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
536 TTM_MEMTYPE_FLAG_CMA;
537 man->available_caching = TTM_PL_MASK_CACHING;
538 man->default_caching = TTM_PL_FLAG_CACHED;
539 }
540
541 break;
542 default:
543 return -EINVAL;
544 }
545 return 0;
546 }
547
548 static void
549 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
550 {
551 struct nouveau_bo *nvbo = nouveau_bo(bo);
552
553 switch (bo->mem.mem_type) {
554 case TTM_PL_VRAM:
555 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
556 TTM_PL_FLAG_SYSTEM);
557 break;
558 default:
559 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
560 break;
561 }
562
563 *pl = nvbo->placement;
564 }
565
566
567 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
568 * TTM_PL_{VRAM,TT} directly.
569 */
570
571 static int
572 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
573 struct nouveau_bo *nvbo, bool evict,
574 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
575 {
576 struct nouveau_fence *fence = NULL;
577 int ret;
578
579 ret = nouveau_fence_new(chan, false, &fence);
580 if (ret)
581 return ret;
582
583 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, evict,
584 no_wait_gpu, new_mem);
585 nouveau_fence_unref(&fence);
586 return ret;
587 }
588
589 static int
590 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
591 {
592 int ret = RING_SPACE(chan, 2);
593 if (ret == 0) {
594 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
595 OUT_RING (chan, handle & 0x0000ffff);
596 FIRE_RING (chan);
597 }
598 return ret;
599 }
600
601 static int
602 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
603 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
604 {
605 struct nouveau_mem *node = old_mem->mm_node;
606 int ret = RING_SPACE(chan, 10);
607 if (ret == 0) {
608 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
609 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
610 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
611 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
612 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
613 OUT_RING (chan, PAGE_SIZE);
614 OUT_RING (chan, PAGE_SIZE);
615 OUT_RING (chan, PAGE_SIZE);
616 OUT_RING (chan, new_mem->num_pages);
617 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
618 }
619 return ret;
620 }
621
622 static int
623 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
624 {
625 int ret = RING_SPACE(chan, 2);
626 if (ret == 0) {
627 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
628 OUT_RING (chan, handle);
629 }
630 return ret;
631 }
632
633 static int
634 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
635 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
636 {
637 struct nouveau_mem *node = old_mem->mm_node;
638 u64 src_offset = node->vma[0].offset;
639 u64 dst_offset = node->vma[1].offset;
640 u32 page_count = new_mem->num_pages;
641 int ret;
642
643 page_count = new_mem->num_pages;
644 while (page_count) {
645 int line_count = (page_count > 8191) ? 8191 : page_count;
646
647 ret = RING_SPACE(chan, 11);
648 if (ret)
649 return ret;
650
651 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
652 OUT_RING (chan, upper_32_bits(src_offset));
653 OUT_RING (chan, lower_32_bits(src_offset));
654 OUT_RING (chan, upper_32_bits(dst_offset));
655 OUT_RING (chan, lower_32_bits(dst_offset));
656 OUT_RING (chan, PAGE_SIZE);
657 OUT_RING (chan, PAGE_SIZE);
658 OUT_RING (chan, PAGE_SIZE);
659 OUT_RING (chan, line_count);
660 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
661 OUT_RING (chan, 0x00000110);
662
663 page_count -= line_count;
664 src_offset += (PAGE_SIZE * line_count);
665 dst_offset += (PAGE_SIZE * line_count);
666 }
667
668 return 0;
669 }
670
671 static int
672 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
673 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
674 {
675 struct nouveau_mem *node = old_mem->mm_node;
676 u64 src_offset = node->vma[0].offset;
677 u64 dst_offset = node->vma[1].offset;
678 u32 page_count = new_mem->num_pages;
679 int ret;
680
681 page_count = new_mem->num_pages;
682 while (page_count) {
683 int line_count = (page_count > 2047) ? 2047 : page_count;
684
685 ret = RING_SPACE(chan, 12);
686 if (ret)
687 return ret;
688
689 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
690 OUT_RING (chan, upper_32_bits(dst_offset));
691 OUT_RING (chan, lower_32_bits(dst_offset));
692 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
693 OUT_RING (chan, upper_32_bits(src_offset));
694 OUT_RING (chan, lower_32_bits(src_offset));
695 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
696 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
697 OUT_RING (chan, PAGE_SIZE); /* line_length */
698 OUT_RING (chan, line_count);
699 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
700 OUT_RING (chan, 0x00100110);
701
702 page_count -= line_count;
703 src_offset += (PAGE_SIZE * line_count);
704 dst_offset += (PAGE_SIZE * line_count);
705 }
706
707 return 0;
708 }
709
710 static int
711 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
712 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
713 {
714 struct nouveau_mem *node = old_mem->mm_node;
715 u64 src_offset = node->vma[0].offset;
716 u64 dst_offset = node->vma[1].offset;
717 u32 page_count = new_mem->num_pages;
718 int ret;
719
720 page_count = new_mem->num_pages;
721 while (page_count) {
722 int line_count = (page_count > 8191) ? 8191 : page_count;
723
724 ret = RING_SPACE(chan, 11);
725 if (ret)
726 return ret;
727
728 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
729 OUT_RING (chan, upper_32_bits(src_offset));
730 OUT_RING (chan, lower_32_bits(src_offset));
731 OUT_RING (chan, upper_32_bits(dst_offset));
732 OUT_RING (chan, lower_32_bits(dst_offset));
733 OUT_RING (chan, PAGE_SIZE);
734 OUT_RING (chan, PAGE_SIZE);
735 OUT_RING (chan, PAGE_SIZE);
736 OUT_RING (chan, line_count);
737 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
738 OUT_RING (chan, 0x00000110);
739
740 page_count -= line_count;
741 src_offset += (PAGE_SIZE * line_count);
742 dst_offset += (PAGE_SIZE * line_count);
743 }
744
745 return 0;
746 }
747
748 static int
749 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
750 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
751 {
752 struct nouveau_mem *node = old_mem->mm_node;
753 int ret = RING_SPACE(chan, 7);
754 if (ret == 0) {
755 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
756 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
757 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
758 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
759 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
760 OUT_RING (chan, 0x00000000 /* COPY */);
761 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
762 }
763 return ret;
764 }
765
766 static int
767 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
768 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
769 {
770 struct nouveau_mem *node = old_mem->mm_node;
771 int ret = RING_SPACE(chan, 7);
772 if (ret == 0) {
773 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
774 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
775 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
776 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
777 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
778 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
779 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
780 }
781 return ret;
782 }
783
784 static int
785 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
786 {
787 int ret = RING_SPACE(chan, 6);
788 if (ret == 0) {
789 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
790 OUT_RING (chan, handle);
791 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
792 OUT_RING (chan, NvNotify0);
793 OUT_RING (chan, NvDmaFB);
794 OUT_RING (chan, NvDmaFB);
795 }
796
797 return ret;
798 }
799
800 static int
801 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
802 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
803 {
804 struct nouveau_mem *node = old_mem->mm_node;
805 u64 length = (new_mem->num_pages << PAGE_SHIFT);
806 u64 src_offset = node->vma[0].offset;
807 u64 dst_offset = node->vma[1].offset;
808 int src_tiled = !!node->memtype;
809 int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
810 int ret;
811
812 while (length) {
813 u32 amount, stride, height;
814
815 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
816 if (ret)
817 return ret;
818
819 amount = min(length, (u64)(4 * 1024 * 1024));
820 stride = 16 * 4;
821 height = amount / stride;
822
823 if (src_tiled) {
824 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
825 OUT_RING (chan, 0);
826 OUT_RING (chan, 0);
827 OUT_RING (chan, stride);
828 OUT_RING (chan, height);
829 OUT_RING (chan, 1);
830 OUT_RING (chan, 0);
831 OUT_RING (chan, 0);
832 } else {
833 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
834 OUT_RING (chan, 1);
835 }
836 if (dst_tiled) {
837 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
838 OUT_RING (chan, 0);
839 OUT_RING (chan, 0);
840 OUT_RING (chan, stride);
841 OUT_RING (chan, height);
842 OUT_RING (chan, 1);
843 OUT_RING (chan, 0);
844 OUT_RING (chan, 0);
845 } else {
846 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
847 OUT_RING (chan, 1);
848 }
849
850 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
851 OUT_RING (chan, upper_32_bits(src_offset));
852 OUT_RING (chan, upper_32_bits(dst_offset));
853 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
854 OUT_RING (chan, lower_32_bits(src_offset));
855 OUT_RING (chan, lower_32_bits(dst_offset));
856 OUT_RING (chan, stride);
857 OUT_RING (chan, stride);
858 OUT_RING (chan, stride);
859 OUT_RING (chan, height);
860 OUT_RING (chan, 0x00000101);
861 OUT_RING (chan, 0x00000000);
862 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
863 OUT_RING (chan, 0);
864
865 length -= amount;
866 src_offset += amount;
867 dst_offset += amount;
868 }
869
870 return 0;
871 }
872
873 static int
874 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
875 {
876 int ret = RING_SPACE(chan, 4);
877 if (ret == 0) {
878 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
879 OUT_RING (chan, handle);
880 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
881 OUT_RING (chan, NvNotify0);
882 }
883
884 return ret;
885 }
886
887 static inline uint32_t
888 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
889 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
890 {
891 if (mem->mem_type == TTM_PL_TT)
892 return NvDmaTT;
893 return NvDmaFB;
894 }
895
896 static int
897 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
898 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
899 {
900 u32 src_offset = old_mem->start << PAGE_SHIFT;
901 u32 dst_offset = new_mem->start << PAGE_SHIFT;
902 u32 page_count = new_mem->num_pages;
903 int ret;
904
905 ret = RING_SPACE(chan, 3);
906 if (ret)
907 return ret;
908
909 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
910 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
911 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
912
913 page_count = new_mem->num_pages;
914 while (page_count) {
915 int line_count = (page_count > 2047) ? 2047 : page_count;
916
917 ret = RING_SPACE(chan, 11);
918 if (ret)
919 return ret;
920
921 BEGIN_NV04(chan, NvSubCopy,
922 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
923 OUT_RING (chan, src_offset);
924 OUT_RING (chan, dst_offset);
925 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
926 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
927 OUT_RING (chan, PAGE_SIZE); /* line_length */
928 OUT_RING (chan, line_count);
929 OUT_RING (chan, 0x00000101);
930 OUT_RING (chan, 0x00000000);
931 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
932 OUT_RING (chan, 0);
933
934 page_count -= line_count;
935 src_offset += (PAGE_SIZE * line_count);
936 dst_offset += (PAGE_SIZE * line_count);
937 }
938
939 return 0;
940 }
941
942 static int
943 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
944 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
945 {
946 struct nouveau_mem *node = mem->mm_node;
947 int ret;
948
949 ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages <<
950 PAGE_SHIFT, node->page_shift,
951 NV_MEM_ACCESS_RW, vma);
952 if (ret)
953 return ret;
954
955 if (mem->mem_type == TTM_PL_VRAM)
956 nouveau_vm_map(vma, node);
957 else
958 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
959
960 return 0;
961 }
962
963 static int
964 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
965 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
966 {
967 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
968 struct nouveau_channel *chan = chan = drm->ttm.chan;
969 struct nouveau_bo *nvbo = nouveau_bo(bo);
970 struct ttm_mem_reg *old_mem = &bo->mem;
971 int ret;
972
973 mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING);
974
975 /* create temporary vmas for the transfer and attach them to the
976 * old nouveau_mem node, these will get cleaned up after ttm has
977 * destroyed the ttm_mem_reg
978 */
979 if (nv_device(drm->device)->card_type >= NV_50) {
980 struct nouveau_mem *node = old_mem->mm_node;
981
982 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
983 if (ret)
984 goto out;
985
986 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
987 if (ret)
988 goto out;
989 }
990
991 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
992 if (ret == 0) {
993 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
994 no_wait_gpu, new_mem);
995 }
996
997 out:
998 mutex_unlock(&chan->cli->mutex);
999 return ret;
1000 }
1001
1002 void
1003 nouveau_bo_move_init(struct nouveau_drm *drm)
1004 {
1005 static const struct {
1006 const char *name;
1007 int engine;
1008 u32 oclass;
1009 int (*exec)(struct nouveau_channel *,
1010 struct ttm_buffer_object *,
1011 struct ttm_mem_reg *, struct ttm_mem_reg *);
1012 int (*init)(struct nouveau_channel *, u32 handle);
1013 } _methods[] = {
1014 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1015 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1016 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1017 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1018 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1019 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1020 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1021 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1022 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1023 {},
1024 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1025 }, *mthd = _methods;
1026 const char *name = "CPU";
1027 int ret;
1028
1029 do {
1030 struct nouveau_object *object;
1031 struct nouveau_channel *chan;
1032 u32 handle = (mthd->engine << 16) | mthd->oclass;
1033
1034 if (mthd->engine)
1035 chan = drm->cechan;
1036 else
1037 chan = drm->channel;
1038 if (chan == NULL)
1039 continue;
1040
1041 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1042 mthd->oclass, NULL, 0, &object);
1043 if (ret == 0) {
1044 ret = mthd->init(chan, handle);
1045 if (ret) {
1046 nouveau_object_del(nv_object(drm),
1047 chan->handle, handle);
1048 continue;
1049 }
1050
1051 drm->ttm.move = mthd->exec;
1052 drm->ttm.chan = chan;
1053 name = mthd->name;
1054 break;
1055 }
1056 } while ((++mthd)->exec);
1057
1058 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1059 }
1060
1061 static int
1062 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1063 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1064 {
1065 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1066 struct ttm_placement placement;
1067 struct ttm_mem_reg tmp_mem;
1068 int ret;
1069
1070 placement.fpfn = placement.lpfn = 0;
1071 placement.num_placement = placement.num_busy_placement = 1;
1072 placement.placement = placement.busy_placement = &placement_memtype;
1073
1074 tmp_mem = *new_mem;
1075 tmp_mem.mm_node = NULL;
1076 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1077 if (ret)
1078 return ret;
1079
1080 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1081 if (ret)
1082 goto out;
1083
1084 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1085 if (ret)
1086 goto out;
1087
1088 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1089 out:
1090 ttm_bo_mem_put(bo, &tmp_mem);
1091 return ret;
1092 }
1093
1094 static int
1095 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1096 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1097 {
1098 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1099 struct ttm_placement placement;
1100 struct ttm_mem_reg tmp_mem;
1101 int ret;
1102
1103 placement.fpfn = placement.lpfn = 0;
1104 placement.num_placement = placement.num_busy_placement = 1;
1105 placement.placement = placement.busy_placement = &placement_memtype;
1106
1107 tmp_mem = *new_mem;
1108 tmp_mem.mm_node = NULL;
1109 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1110 if (ret)
1111 return ret;
1112
1113 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1114 if (ret)
1115 goto out;
1116
1117 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1118 if (ret)
1119 goto out;
1120
1121 out:
1122 ttm_bo_mem_put(bo, &tmp_mem);
1123 return ret;
1124 }
1125
1126 static void
1127 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1128 {
1129 struct nouveau_bo *nvbo = nouveau_bo(bo);
1130 struct nouveau_vma *vma;
1131
1132 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1133 if (bo->destroy != nouveau_bo_del_ttm)
1134 return;
1135
1136 list_for_each_entry(vma, &nvbo->vma_list, head) {
1137 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1138 nouveau_vm_map(vma, new_mem->mm_node);
1139 } else
1140 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1141 nvbo->page_shift == vma->vm->vmm->spg_shift) {
1142 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1143 nouveau_vm_map_sg_table(vma, 0, new_mem->
1144 num_pages << PAGE_SHIFT,
1145 new_mem->mm_node);
1146 else
1147 nouveau_vm_map_sg(vma, 0, new_mem->
1148 num_pages << PAGE_SHIFT,
1149 new_mem->mm_node);
1150 } else {
1151 nouveau_vm_unmap(vma);
1152 }
1153 }
1154 }
1155
1156 static int
1157 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1158 struct nouveau_drm_tile **new_tile)
1159 {
1160 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1161 struct drm_device *dev = drm->dev;
1162 struct nouveau_bo *nvbo = nouveau_bo(bo);
1163 u64 offset = new_mem->start << PAGE_SHIFT;
1164
1165 *new_tile = NULL;
1166 if (new_mem->mem_type != TTM_PL_VRAM)
1167 return 0;
1168
1169 if (nv_device(drm->device)->card_type >= NV_10) {
1170 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1171 nvbo->tile_mode,
1172 nvbo->tile_flags);
1173 }
1174
1175 return 0;
1176 }
1177
1178 static void
1179 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1180 struct nouveau_drm_tile *new_tile,
1181 struct nouveau_drm_tile **old_tile)
1182 {
1183 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1184 struct drm_device *dev = drm->dev;
1185
1186 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1187 *old_tile = new_tile;
1188 }
1189
1190 static int
1191 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1192 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1193 {
1194 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1195 struct nouveau_bo *nvbo = nouveau_bo(bo);
1196 struct ttm_mem_reg *old_mem = &bo->mem;
1197 struct nouveau_drm_tile *new_tile = NULL;
1198 int ret = 0;
1199
1200 if (nv_device(drm->device)->card_type < NV_50) {
1201 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1202 if (ret)
1203 return ret;
1204 }
1205
1206 /* Fake bo copy. */
1207 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1208 BUG_ON(bo->mem.mm_node != NULL);
1209 bo->mem = *new_mem;
1210 new_mem->mm_node = NULL;
1211 goto out;
1212 }
1213
1214 /* CPU copy if we have no accelerated method available */
1215 if (!drm->ttm.move) {
1216 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1217 goto out;
1218 }
1219
1220 /* Hardware assisted copy. */
1221 if (new_mem->mem_type == TTM_PL_SYSTEM)
1222 ret = nouveau_bo_move_flipd(bo, evict, intr,
1223 no_wait_gpu, new_mem);
1224 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1225 ret = nouveau_bo_move_flips(bo, evict, intr,
1226 no_wait_gpu, new_mem);
1227 else
1228 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1229 no_wait_gpu, new_mem);
1230
1231 if (!ret)
1232 goto out;
1233
1234 /* Fallback to software copy. */
1235 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1236
1237 out:
1238 if (nv_device(drm->device)->card_type < NV_50) {
1239 if (ret)
1240 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1241 else
1242 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1243 }
1244
1245 return ret;
1246 }
1247
1248 static int
1249 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1250 {
1251 struct nouveau_bo *nvbo = nouveau_bo(bo);
1252
1253 return drm_vma_node_verify_access(&nvbo->gem->vma_node, filp);
1254 }
1255
1256 static int
1257 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1258 {
1259 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1260 struct nouveau_drm *drm = nouveau_bdev(bdev);
1261 struct drm_device *dev = drm->dev;
1262 int ret;
1263
1264 mem->bus.addr = NULL;
1265 mem->bus.offset = 0;
1266 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1267 mem->bus.base = 0;
1268 mem->bus.is_iomem = false;
1269 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1270 return -EINVAL;
1271 switch (mem->mem_type) {
1272 case TTM_PL_SYSTEM:
1273 /* System memory */
1274 return 0;
1275 case TTM_PL_TT:
1276 #if __OS_HAS_AGP
1277 if (drm->agp.stat == ENABLED) {
1278 mem->bus.offset = mem->start << PAGE_SHIFT;
1279 mem->bus.base = drm->agp.base;
1280 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1281 }
1282 #endif
1283 break;
1284 case TTM_PL_VRAM:
1285 mem->bus.offset = mem->start << PAGE_SHIFT;
1286 mem->bus.base = pci_resource_start(dev->pdev, 1);
1287 mem->bus.is_iomem = true;
1288 if (nv_device(drm->device)->card_type >= NV_50) {
1289 struct nouveau_bar *bar = nouveau_bar(drm->device);
1290 struct nouveau_mem *node = mem->mm_node;
1291
1292 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1293 &node->bar_vma);
1294 if (ret)
1295 return ret;
1296
1297 mem->bus.offset = node->bar_vma.offset;
1298 }
1299 break;
1300 default:
1301 return -EINVAL;
1302 }
1303 return 0;
1304 }
1305
1306 static void
1307 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1308 {
1309 struct nouveau_drm *drm = nouveau_bdev(bdev);
1310 struct nouveau_bar *bar = nouveau_bar(drm->device);
1311 struct nouveau_mem *node = mem->mm_node;
1312
1313 if (!node->bar_vma.node)
1314 return;
1315
1316 bar->unmap(bar, &node->bar_vma);
1317 }
1318
1319 static int
1320 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1321 {
1322 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1323 struct nouveau_bo *nvbo = nouveau_bo(bo);
1324 struct nouveau_device *device = nv_device(drm->device);
1325 u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1326
1327 /* as long as the bo isn't in vram, and isn't tiled, we've got
1328 * nothing to do here.
1329 */
1330 if (bo->mem.mem_type != TTM_PL_VRAM) {
1331 if (nv_device(drm->device)->card_type < NV_50 ||
1332 !nouveau_bo_tile_layout(nvbo))
1333 return 0;
1334 }
1335
1336 /* make sure bo is in mappable vram */
1337 if (bo->mem.start + bo->mem.num_pages < mappable)
1338 return 0;
1339
1340
1341 nvbo->placement.fpfn = 0;
1342 nvbo->placement.lpfn = mappable;
1343 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1344 return nouveau_bo_validate(nvbo, false, false);
1345 }
1346
1347 static int
1348 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1349 {
1350 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1351 struct nouveau_drm *drm;
1352 struct drm_device *dev;
1353 unsigned i;
1354 int r;
1355 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1356
1357 if (ttm->state != tt_unpopulated)
1358 return 0;
1359
1360 if (slave && ttm->sg) {
1361 /* make userspace faulting work */
1362 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1363 ttm_dma->dma_address, ttm->num_pages);
1364 ttm->state = tt_unbound;
1365 return 0;
1366 }
1367
1368 drm = nouveau_bdev(ttm->bdev);
1369 dev = drm->dev;
1370
1371 #if __OS_HAS_AGP
1372 if (drm->agp.stat == ENABLED) {
1373 return ttm_agp_tt_populate(ttm);
1374 }
1375 #endif
1376
1377 #ifdef CONFIG_SWIOTLB
1378 if (swiotlb_nr_tbl()) {
1379 return ttm_dma_populate((void *)ttm, dev->dev);
1380 }
1381 #endif
1382
1383 r = ttm_pool_populate(ttm);
1384 if (r) {
1385 return r;
1386 }
1387
1388 for (i = 0; i < ttm->num_pages; i++) {
1389 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1390 0, PAGE_SIZE,
1391 PCI_DMA_BIDIRECTIONAL);
1392 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1393 while (--i) {
1394 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1395 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1396 ttm_dma->dma_address[i] = 0;
1397 }
1398 ttm_pool_unpopulate(ttm);
1399 return -EFAULT;
1400 }
1401 }
1402 return 0;
1403 }
1404
1405 static void
1406 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1407 {
1408 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1409 struct nouveau_drm *drm;
1410 struct drm_device *dev;
1411 unsigned i;
1412 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1413
1414 if (slave)
1415 return;
1416
1417 drm = nouveau_bdev(ttm->bdev);
1418 dev = drm->dev;
1419
1420 #if __OS_HAS_AGP
1421 if (drm->agp.stat == ENABLED) {
1422 ttm_agp_tt_unpopulate(ttm);
1423 return;
1424 }
1425 #endif
1426
1427 #ifdef CONFIG_SWIOTLB
1428 if (swiotlb_nr_tbl()) {
1429 ttm_dma_unpopulate((void *)ttm, dev->dev);
1430 return;
1431 }
1432 #endif
1433
1434 for (i = 0; i < ttm->num_pages; i++) {
1435 if (ttm_dma->dma_address[i]) {
1436 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1437 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1438 }
1439 }
1440
1441 ttm_pool_unpopulate(ttm);
1442 }
1443
1444 void
1445 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1446 {
1447 struct nouveau_fence *old_fence = NULL;
1448
1449 if (likely(fence))
1450 nouveau_fence_ref(fence);
1451
1452 spin_lock(&nvbo->bo.bdev->fence_lock);
1453 old_fence = nvbo->bo.sync_obj;
1454 nvbo->bo.sync_obj = fence;
1455 spin_unlock(&nvbo->bo.bdev->fence_lock);
1456
1457 nouveau_fence_unref(&old_fence);
1458 }
1459
1460 static void
1461 nouveau_bo_fence_unref(void **sync_obj)
1462 {
1463 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1464 }
1465
1466 static void *
1467 nouveau_bo_fence_ref(void *sync_obj)
1468 {
1469 return nouveau_fence_ref(sync_obj);
1470 }
1471
1472 static bool
1473 nouveau_bo_fence_signalled(void *sync_obj)
1474 {
1475 return nouveau_fence_done(sync_obj);
1476 }
1477
1478 static int
1479 nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1480 {
1481 return nouveau_fence_wait(sync_obj, lazy, intr);
1482 }
1483
1484 static int
1485 nouveau_bo_fence_flush(void *sync_obj)
1486 {
1487 return 0;
1488 }
1489
1490 struct ttm_bo_driver nouveau_bo_driver = {
1491 .ttm_tt_create = &nouveau_ttm_tt_create,
1492 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1493 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1494 .invalidate_caches = nouveau_bo_invalidate_caches,
1495 .init_mem_type = nouveau_bo_init_mem_type,
1496 .evict_flags = nouveau_bo_evict_flags,
1497 .move_notify = nouveau_bo_move_ntfy,
1498 .move = nouveau_bo_move,
1499 .verify_access = nouveau_bo_verify_access,
1500 .sync_obj_signaled = nouveau_bo_fence_signalled,
1501 .sync_obj_wait = nouveau_bo_fence_wait,
1502 .sync_obj_flush = nouveau_bo_fence_flush,
1503 .sync_obj_unref = nouveau_bo_fence_unref,
1504 .sync_obj_ref = nouveau_bo_fence_ref,
1505 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1506 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1507 .io_mem_free = &nouveau_ttm_io_mem_free,
1508 };
1509
1510 struct nouveau_vma *
1511 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1512 {
1513 struct nouveau_vma *vma;
1514 list_for_each_entry(vma, &nvbo->vma_list, head) {
1515 if (vma->vm == vm)
1516 return vma;
1517 }
1518
1519 return NULL;
1520 }
1521
1522 int
1523 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1524 struct nouveau_vma *vma)
1525 {
1526 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1527 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1528 int ret;
1529
1530 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1531 NV_MEM_ACCESS_RW, vma);
1532 if (ret)
1533 return ret;
1534
1535 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1536 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1537 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1538 if (node->sg)
1539 nouveau_vm_map_sg_table(vma, 0, size, node);
1540 else
1541 nouveau_vm_map_sg(vma, 0, size, node);
1542 }
1543
1544 list_add_tail(&vma->head, &nvbo->vma_list);
1545 vma->refcount = 1;
1546 return 0;
1547 }
1548
1549 void
1550 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1551 {
1552 if (vma->node) {
1553 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1554 nouveau_vm_unmap(vma);
1555 nouveau_vm_put(vma);
1556 list_del(&vma->head);
1557 }
1558 }
Linux with added FPC-III support