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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nv50_pm.c
blob4efc33fa73fc6cc87dd6684b29c90bcb2daa4d50
1 /*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <drm/drmP.h>
26 #include "nouveau_drm.h"
27 #include "nouveau_bios.h"
28 #include "dispnv04/hw.h"
29 #include "nouveau_pm.h"
30 #include "nouveau_hwsq.h"
31
32 #include "nv50_display.h"
33
34 #include <subdev/bios/pll.h>
35 #include <subdev/clock.h>
36 #include <subdev/timer.h>
37 #include <subdev/fb.h>
38
39 enum clk_src {
40 clk_src_crystal,
41 clk_src_href,
42 clk_src_hclk,
43 clk_src_hclkm3,
44 clk_src_hclkm3d2,
45 clk_src_host,
46 clk_src_nvclk,
47 clk_src_sclk,
48 clk_src_mclk,
49 clk_src_vdec,
50 clk_src_dom6
51 };
52
53 static u32 read_clk(struct drm_device *, enum clk_src);
54
55 static u32
56 read_div(struct drm_device *dev)
57 {
58 struct nouveau_device *device = nouveau_dev(dev);
59 struct nouveau_drm *drm = nouveau_drm(dev);
60
61 switch (nv_device(drm->device)->chipset) {
62 case 0x50: /* it exists, but only has bit 31, not the dividers.. */
63 case 0x84:
64 case 0x86:
65 case 0x98:
66 case 0xa0:
67 return nv_rd32(device, 0x004700);
68 case 0x92:
69 case 0x94:
70 case 0x96:
71 return nv_rd32(device, 0x004800);
72 default:
73 return 0x00000000;
74 }
75 }
76
77 static u32
78 read_pll_src(struct drm_device *dev, u32 base)
79 {
80 struct nouveau_device *device = nouveau_dev(dev);
81 struct nouveau_drm *drm = nouveau_drm(dev);
82 u32 coef, ref = read_clk(dev, clk_src_crystal);
83 u32 rsel = nv_rd32(device, 0x00e18c);
84 int P, N, M, id;
85
86 switch (nv_device(drm->device)->chipset) {
87 case 0x50:
88 case 0xa0:
89 switch (base) {
90 case 0x4020:
91 case 0x4028: id = !!(rsel & 0x00000004); break;
92 case 0x4008: id = !!(rsel & 0x00000008); break;
93 case 0x4030: id = 0; break;
94 default:
95 NV_ERROR(drm, "ref: bad pll 0x%06x\n", base);
96 return 0;
97 }
98
99 coef = nv_rd32(device, 0x00e81c + (id * 0x0c));
100 ref *= (coef & 0x01000000) ? 2 : 4;
101 P = (coef & 0x00070000) >> 16;
102 N = ((coef & 0x0000ff00) >> 8) + 1;
103 M = ((coef & 0x000000ff) >> 0) + 1;
104 break;
105 case 0x84:
106 case 0x86:
107 case 0x92:
108 coef = nv_rd32(device, 0x00e81c);
109 P = (coef & 0x00070000) >> 16;
110 N = (coef & 0x0000ff00) >> 8;
111 M = (coef & 0x000000ff) >> 0;
112 break;
113 case 0x94:
114 case 0x96:
115 case 0x98:
116 rsel = nv_rd32(device, 0x00c050);
117 switch (base) {
118 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
119 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
120 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
121 case 0x4030: rsel = 3; break;
122 default:
123 NV_ERROR(drm, "ref: bad pll 0x%06x\n", base);
124 return 0;
125 }
126
127 switch (rsel) {
128 case 0: id = 1; break;
129 case 1: return read_clk(dev, clk_src_crystal);
130 case 2: return read_clk(dev, clk_src_href);
131 case 3: id = 0; break;
132 }
133
134 coef = nv_rd32(device, 0x00e81c + (id * 0x28));
135 P = (nv_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7;
136 P += (coef & 0x00070000) >> 16;
137 N = (coef & 0x0000ff00) >> 8;
138 M = (coef & 0x000000ff) >> 0;
139 break;
140 default:
141 BUG_ON(1);
142 }
143
144 if (M)
145 return (ref * N / M) >> P;
146 return 0;
147 }
148
149 static u32
150 read_pll_ref(struct drm_device *dev, u32 base)
151 {
152 struct nouveau_device *device = nouveau_dev(dev);
153 struct nouveau_drm *drm = nouveau_drm(dev);
154 u32 src, mast = nv_rd32(device, 0x00c040);
155
156 switch (base) {
157 case 0x004028:
158 src = !!(mast & 0x00200000);
159 break;
160 case 0x004020:
161 src = !!(mast & 0x00400000);
162 break;
163 case 0x004008:
164 src = !!(mast & 0x00010000);
165 break;
166 case 0x004030:
167 src = !!(mast & 0x02000000);
168 break;
169 case 0x00e810:
170 return read_clk(dev, clk_src_crystal);
171 default:
172 NV_ERROR(drm, "bad pll 0x%06x\n", base);
173 return 0;
174 }
175
176 if (src)
177 return read_clk(dev, clk_src_href);
178 return read_pll_src(dev, base);
179 }
180
181 static u32
182 read_pll(struct drm_device *dev, u32 base)
183 {
184 struct nouveau_device *device = nouveau_dev(dev);
185 struct nouveau_drm *drm = nouveau_drm(dev);
186 u32 mast = nv_rd32(device, 0x00c040);
187 u32 ctrl = nv_rd32(device, base + 0);
188 u32 coef = nv_rd32(device, base + 4);
189 u32 ref = read_pll_ref(dev, base);
190 u32 clk = 0;
191 int N1, N2, M1, M2;
192
193 if (base == 0x004028 && (mast & 0x00100000)) {
194 /* wtf, appears to only disable post-divider on nva0 */
195 if (nv_device(drm->device)->chipset != 0xa0)
196 return read_clk(dev, clk_src_dom6);
197 }
198
199 N2 = (coef & 0xff000000) >> 24;
200 M2 = (coef & 0x00ff0000) >> 16;
201 N1 = (coef & 0x0000ff00) >> 8;
202 M1 = (coef & 0x000000ff);
203 if ((ctrl & 0x80000000) && M1) {
204 clk = ref * N1 / M1;
205 if ((ctrl & 0x40000100) == 0x40000000) {
206 if (M2)
207 clk = clk * N2 / M2;
208 else
209 clk = 0;
210 }
211 }
212
213 return clk;
214 }
215
216 static u32
217 read_clk(struct drm_device *dev, enum clk_src src)
218 {
219 struct nouveau_device *device = nouveau_dev(dev);
220 struct nouveau_drm *drm = nouveau_drm(dev);
221 u32 mast = nv_rd32(device, 0x00c040);
222 u32 P = 0;
223
224 switch (src) {
225 case clk_src_crystal:
226 return device->crystal;
227 case clk_src_href:
228 return 100000; /* PCIE reference clock */
229 case clk_src_hclk:
230 return read_clk(dev, clk_src_href) * 27778 / 10000;
231 case clk_src_hclkm3:
232 return read_clk(dev, clk_src_hclk) * 3;
233 case clk_src_hclkm3d2:
234 return read_clk(dev, clk_src_hclk) * 3 / 2;
235 case clk_src_host:
236 switch (mast & 0x30000000) {
237 case 0x00000000: return read_clk(dev, clk_src_href);
238 case 0x10000000: break;
239 case 0x20000000: /* !0x50 */
240 case 0x30000000: return read_clk(dev, clk_src_hclk);
241 }
242 break;
243 case clk_src_nvclk:
244 if (!(mast & 0x00100000))
245 P = (nv_rd32(device, 0x004028) & 0x00070000) >> 16;
246 switch (mast & 0x00000003) {
247 case 0x00000000: return read_clk(dev, clk_src_crystal) >> P;
248 case 0x00000001: return read_clk(dev, clk_src_dom6);
249 case 0x00000002: return read_pll(dev, 0x004020) >> P;
250 case 0x00000003: return read_pll(dev, 0x004028) >> P;
251 }
252 break;
253 case clk_src_sclk:
254 P = (nv_rd32(device, 0x004020) & 0x00070000) >> 16;
255 switch (mast & 0x00000030) {
256 case 0x00000000:
257 if (mast & 0x00000080)
258 return read_clk(dev, clk_src_host) >> P;
259 return read_clk(dev, clk_src_crystal) >> P;
260 case 0x00000010: break;
261 case 0x00000020: return read_pll(dev, 0x004028) >> P;
262 case 0x00000030: return read_pll(dev, 0x004020) >> P;
263 }
264 break;
265 case clk_src_mclk:
266 P = (nv_rd32(device, 0x004008) & 0x00070000) >> 16;
267 if (nv_rd32(device, 0x004008) & 0x00000200) {
268 switch (mast & 0x0000c000) {
269 case 0x00000000:
270 return read_clk(dev, clk_src_crystal) >> P;
271 case 0x00008000:
272 case 0x0000c000:
273 return read_clk(dev, clk_src_href) >> P;
274 }
275 } else {
276 return read_pll(dev, 0x004008) >> P;
277 }
278 break;
279 case clk_src_vdec:
280 P = (read_div(dev) & 0x00000700) >> 8;
281 switch (nv_device(drm->device)->chipset) {
282 case 0x84:
283 case 0x86:
284 case 0x92:
285 case 0x94:
286 case 0x96:
287 case 0xa0:
288 switch (mast & 0x00000c00) {
289 case 0x00000000:
290 if (nv_device(drm->device)->chipset == 0xa0) /* wtf?? */
291 return read_clk(dev, clk_src_nvclk) >> P;
292 return read_clk(dev, clk_src_crystal) >> P;
293 case 0x00000400:
294 return 0;
295 case 0x00000800:
296 if (mast & 0x01000000)
297 return read_pll(dev, 0x004028) >> P;
298 return read_pll(dev, 0x004030) >> P;
299 case 0x00000c00:
300 return read_clk(dev, clk_src_nvclk) >> P;
301 }
302 break;
303 case 0x98:
304 switch (mast & 0x00000c00) {
305 case 0x00000000:
306 return read_clk(dev, clk_src_nvclk) >> P;
307 case 0x00000400:
308 return 0;
309 case 0x00000800:
310 return read_clk(dev, clk_src_hclkm3d2) >> P;
311 case 0x00000c00:
312 return read_clk(dev, clk_src_mclk) >> P;
313 }
314 break;
315 }
316 break;
317 case clk_src_dom6:
318 switch (nv_device(drm->device)->chipset) {
319 case 0x50:
320 case 0xa0:
321 return read_pll(dev, 0x00e810) >> 2;
322 case 0x84:
323 case 0x86:
324 case 0x92:
325 case 0x94:
326 case 0x96:
327 case 0x98:
328 P = (read_div(dev) & 0x00000007) >> 0;
329 switch (mast & 0x0c000000) {
330 case 0x00000000: return read_clk(dev, clk_src_href);
331 case 0x04000000: break;
332 case 0x08000000: return read_clk(dev, clk_src_hclk);
333 case 0x0c000000:
334 return read_clk(dev, clk_src_hclkm3) >> P;
335 }
336 break;
337 default:
338 break;
339 }
340 default:
341 break;
342 }
343
344 NV_DEBUG(drm, "unknown clock source %d 0x%08x\n", src, mast);
345 return 0;
346 }
347
348 int
349 nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
350 {
351 struct nouveau_drm *drm = nouveau_drm(dev);
352 if (nv_device(drm->device)->chipset == 0xaa ||
353 nv_device(drm->device)->chipset == 0xac)
354 return 0;
355
356 perflvl->core = read_clk(dev, clk_src_nvclk);
357 perflvl->shader = read_clk(dev, clk_src_sclk);
358 perflvl->memory = read_clk(dev, clk_src_mclk);
359 if (nv_device(drm->device)->chipset != 0x50) {
360 perflvl->vdec = read_clk(dev, clk_src_vdec);
361 perflvl->dom6 = read_clk(dev, clk_src_dom6);
362 }
363
364 return 0;
365 }
366
367 struct nv50_pm_state {
368 struct nouveau_pm_level *perflvl;
369 struct hwsq_ucode eclk_hwsq;
370 struct hwsq_ucode mclk_hwsq;
371 u32 mscript;
372 u32 mmast;
373 u32 mctrl;
374 u32 mcoef;
375 };
376
377 static u32
378 calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
379 u32 clk, int *N1, int *M1, int *log2P)
380 {
381 struct nouveau_device *device = nouveau_dev(dev);
382 struct nouveau_bios *bios = nouveau_bios(device);
383 struct nouveau_clock *pclk = nouveau_clock(device);
384 struct nouveau_pll_vals coef;
385 int ret;
386
387 ret = nvbios_pll_parse(bios, reg, pll);
388 if (ret)
389 return 0;
390
391 pll->vco2.max_freq = 0;
392 pll->refclk = read_pll_ref(dev, reg);
393 if (!pll->refclk)
394 return 0;
395
396 ret = pclk->pll_calc(pclk, pll, clk, &coef);
397 if (ret == 0)
398 return 0;
399
400 *N1 = coef.N1;
401 *M1 = coef.M1;
402 *log2P = coef.log2P;
403 return ret;
404 }
405
406 static inline u32
407 calc_div(u32 src, u32 target, int *div)
408 {
409 u32 clk0 = src, clk1 = src;
410 for (*div = 0; *div <= 7; (*div)++) {
411 if (clk0 <= target) {
412 clk1 = clk0 << (*div ? 1 : 0);
413 break;
414 }
415 clk0 >>= 1;
416 }
417
418 if (target - clk0 <= clk1 - target)
419 return clk0;
420 (*div)--;
421 return clk1;
422 }
423
424 static inline u32
425 clk_same(u32 a, u32 b)
426 {
427 return ((a / 1000) == (b / 1000));
428 }
429
430 static void
431 mclk_precharge(struct nouveau_mem_exec_func *exec)
432 {
433 struct nv50_pm_state *info = exec->priv;
434 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
435
436 hwsq_wr32(hwsq, 0x1002d4, 0x00000001);
437 }
438
439 static void
440 mclk_refresh(struct nouveau_mem_exec_func *exec)
441 {
442 struct nv50_pm_state *info = exec->priv;
443 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
444
445 hwsq_wr32(hwsq, 0x1002d0, 0x00000001);
446 }
447
448 static void
449 mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
450 {
451 struct nv50_pm_state *info = exec->priv;
452 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
453
454 hwsq_wr32(hwsq, 0x100210, enable ? 0x80000000 : 0x00000000);
455 }
456
457 static void
458 mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
459 {
460 struct nv50_pm_state *info = exec->priv;
461 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
462
463 hwsq_wr32(hwsq, 0x1002dc, enable ? 0x00000001 : 0x00000000);
464 }
465
466 static void
467 mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
468 {
469 struct nv50_pm_state *info = exec->priv;
470 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
471
472 if (nsec > 1000)
473 hwsq_usec(hwsq, (nsec + 500) / 1000);
474 }
475
476 static u32
477 mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
478 {
479 struct nouveau_device *device = nouveau_dev(exec->dev);
480 if (mr <= 1)
481 return nv_rd32(device, 0x1002c0 + ((mr - 0) * 4));
482 if (mr <= 3)
483 return nv_rd32(device, 0x1002e0 + ((mr - 2) * 4));
484 return 0;
485 }
486
487 static void
488 mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
489 {
490 struct nouveau_device *device = nouveau_dev(exec->dev);
491 struct nouveau_fb *pfb = nouveau_fb(device);
492 struct nv50_pm_state *info = exec->priv;
493 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
494
495 if (mr <= 1) {
496 if (pfb->ram->ranks > 1)
497 hwsq_wr32(hwsq, 0x1002c8 + ((mr - 0) * 4), data);
498 hwsq_wr32(hwsq, 0x1002c0 + ((mr - 0) * 4), data);
499 } else
500 if (mr <= 3) {
501 if (pfb->ram->ranks > 1)
502 hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data);
503 hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data);
504 }
505 }
506
507 static void
508 mclk_clock_set(struct nouveau_mem_exec_func *exec)
509 {
510 struct nouveau_device *device = nouveau_dev(exec->dev);
511 struct nv50_pm_state *info = exec->priv;
512 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
513 u32 ctrl = nv_rd32(device, 0x004008);
514
515 info->mmast = nv_rd32(device, 0x00c040);
516 info->mmast &= ~0xc0000000; /* get MCLK_2 from HREF */
517 info->mmast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
518
519 hwsq_wr32(hwsq, 0xc040, info->mmast);
520 hwsq_wr32(hwsq, 0x4008, ctrl | 0x00000200); /* bypass MPLL */
521 if (info->mctrl & 0x80000000)
522 hwsq_wr32(hwsq, 0x400c, info->mcoef);
523 hwsq_wr32(hwsq, 0x4008, info->mctrl);
524 }
525
526 static void
527 mclk_timing_set(struct nouveau_mem_exec_func *exec)
528 {
529 struct nouveau_device *device = nouveau_dev(exec->dev);
530 struct nv50_pm_state *info = exec->priv;
531 struct nouveau_pm_level *perflvl = info->perflvl;
532 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
533 int i;
534
535 for (i = 0; i < 9; i++) {
536 u32 reg = 0x100220 + (i * 4);
537 u32 val = nv_rd32(device, reg);
538 if (val != perflvl->timing.reg[i])
539 hwsq_wr32(hwsq, reg, perflvl->timing.reg[i]);
540 }
541 }
542
543 static int
544 calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
545 struct nv50_pm_state *info)
546 {
547 struct nouveau_drm *drm = nouveau_drm(dev);
548 struct nouveau_device *device = nouveau_dev(dev);
549 u32 crtc_mask = 0; /*XXX: nv50_display_active_crtcs(dev); */
550 struct nouveau_mem_exec_func exec = {
551 .dev = dev,
552 .precharge = mclk_precharge,
553 .refresh = mclk_refresh,
554 .refresh_auto = mclk_refresh_auto,
555 .refresh_self = mclk_refresh_self,
556 .wait = mclk_wait,
557 .mrg = mclk_mrg,
558 .mrs = mclk_mrs,
559 .clock_set = mclk_clock_set,
560 .timing_set = mclk_timing_set,
561 .priv = info
562 };
563 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
564 struct nvbios_pll pll;
565 int N, M, P;
566 int ret;
567
568 /* use pcie refclock if possible, otherwise use mpll */
569 info->mctrl = nv_rd32(device, 0x004008);
570 info->mctrl &= ~0x81ff0200;
571 if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
572 info->mctrl |= 0x00000200 | (pll.bias_p << 19);
573 } else {
574 ret = calc_pll(dev, 0x4008, &pll, perflvl->memory, &N, &M, &P);
575 if (ret == 0)
576 return -EINVAL;
577
578 info->mctrl |= 0x80000000 | (P << 22) | (P << 16);
579 info->mctrl |= pll.bias_p << 19;
580 info->mcoef = (N << 8) | M;
581 }
582
583 /* build the ucode which will reclock the memory for us */
584 hwsq_init(hwsq);
585 if (crtc_mask) {
586 hwsq_op5f(hwsq, crtc_mask, 0x00); /* wait for scanout */
587 hwsq_op5f(hwsq, crtc_mask, 0x01); /* wait for vblank */
588 }
589 if (nv_device(drm->device)->chipset >= 0x92)
590 hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */
591 hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
592 hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */
593
594 ret = nouveau_mem_exec(&exec, perflvl);
595 if (ret)
596 return ret;
597
598 hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
599 hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
600 if (nv_device(drm->device)->chipset >= 0x92)
601 hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */
602 hwsq_fini(hwsq);
603 return 0;
604 }
605
606 void *
607 nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
608 {
609 struct nouveau_device *device = nouveau_dev(dev);
610 struct nouveau_drm *drm = nouveau_drm(dev);
611 struct nv50_pm_state *info;
612 struct hwsq_ucode *hwsq;
613 struct nvbios_pll pll;
614 u32 out, mast, divs, ctrl;
615 int clk, ret = -EINVAL;
616 int N, M, P1, P2;
617
618 if (nv_device(drm->device)->chipset == 0xaa ||
619 nv_device(drm->device)->chipset == 0xac)
620 return ERR_PTR(-ENODEV);
621
622 info = kmalloc(sizeof(*info), GFP_KERNEL);
623 if (!info)
624 return ERR_PTR(-ENOMEM);
625 info->perflvl = perflvl;
626
627 /* memory: build hwsq ucode which we'll use to reclock memory.
628 * use pcie refclock if possible, otherwise use mpll */
629 info->mclk_hwsq.len = 0;
630 if (perflvl->memory) {
631 ret = calc_mclk(dev, perflvl, info);
632 if (ret)
633 goto error;
634 info->mscript = perflvl->memscript;
635 }
636
637 divs = read_div(dev);
638 mast = info->mmast;
639
640 /* start building HWSQ script for engine reclocking */
641 hwsq = &info->eclk_hwsq;
642 hwsq_init(hwsq);
643 hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
644 hwsq_op5f(hwsq, 0x00, 0x01); /* wait for access disabled? */
645
646 /* vdec/dom6: switch to "safe" clocks temporarily */
647 if (perflvl->vdec) {
648 mast &= ~0x00000c00;
649 divs &= ~0x00000700;
650 }
651
652 if (perflvl->dom6) {
653 mast &= ~0x0c000000;
654 divs &= ~0x00000007;
655 }
656
657 hwsq_wr32(hwsq, 0x00c040, mast);
658
659 /* vdec: avoid modifying xpll until we know exactly how the other
660 * clock domains work, i suspect at least some of them can also be
661 * tied to xpll...
662 */
663 if (perflvl->vdec) {
664 /* see how close we can get using nvclk as a source */
665 clk = calc_div(perflvl->core, perflvl->vdec, &P1);
666
667 /* see how close we can get using xpll/hclk as a source */
668 if (nv_device(drm->device)->chipset != 0x98)
669 out = read_pll(dev, 0x004030);
670 else
671 out = read_clk(dev, clk_src_hclkm3d2);
672 out = calc_div(out, perflvl->vdec, &P2);
673
674 /* select whichever gets us closest */
675 if (abs((int)perflvl->vdec - clk) <=
676 abs((int)perflvl->vdec - out)) {
677 if (nv_device(drm->device)->chipset != 0x98)
678 mast |= 0x00000c00;
679 divs |= P1 << 8;
680 } else {
681 mast |= 0x00000800;
682 divs |= P2 << 8;
683 }
684 }
685
686 /* dom6: nfi what this is, but we're limited to various combinations
687 * of the host clock frequency
688 */
689 if (perflvl->dom6) {
690 if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) {
691 mast |= 0x00000000;
692 } else
693 if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) {
694 mast |= 0x08000000;
695 } else {
696 clk = read_clk(dev, clk_src_hclk) * 3;
697 clk = calc_div(clk, perflvl->dom6, &P1);
698
699 mast |= 0x0c000000;
700 divs |= P1;
701 }
702 }
703
704 /* vdec/dom6: complete switch to new clocks */
705 switch (nv_device(drm->device)->chipset) {
706 case 0x92:
707 case 0x94:
708 case 0x96:
709 hwsq_wr32(hwsq, 0x004800, divs);
710 break;
711 default:
712 hwsq_wr32(hwsq, 0x004700, divs);
713 break;
714 }
715
716 hwsq_wr32(hwsq, 0x00c040, mast);
717
718 /* core/shader: make sure sclk/nvclk are disconnected from their
719 * PLLs (nvclk to dom6, sclk to hclk)
720 */
721 if (nv_device(drm->device)->chipset < 0x92)
722 mast = (mast & ~0x001000b0) | 0x00100080;
723 else
724 mast = (mast & ~0x000000b3) | 0x00000081;
725
726 hwsq_wr32(hwsq, 0x00c040, mast);
727
728 /* core: for the moment at least, always use nvpll */
729 clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
730 if (clk == 0)
731 goto error;
732
733 ctrl = nv_rd32(device, 0x004028) & ~0xc03f0100;
734 mast &= ~0x00100000;
735 mast |= 3;
736
737 hwsq_wr32(hwsq, 0x004028, 0x80000000 | (P1 << 19) | (P1 << 16) | ctrl);
738 hwsq_wr32(hwsq, 0x00402c, (N << 8) | M);
739
740 /* shader: tie to nvclk if possible, otherwise use spll. have to be
741 * very careful that the shader clock is at least twice the core, or
742 * some chipsets will be very unhappy. i expect most or all of these
743 * cases will be handled by tying to nvclk, but it's possible there's
744 * corners
745 */
746 ctrl = nv_rd32(device, 0x004020) & ~0xc03f0100;
747
748 if (P1-- && perflvl->shader == (perflvl->core << 1)) {
749 hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
750 hwsq_wr32(hwsq, 0x00c040, 0x00000020 | mast);
751 } else {
752 clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
753 if (clk == 0)
754 goto error;
755 ctrl |= 0x80000000;
756
757 hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
758 hwsq_wr32(hwsq, 0x004024, (N << 8) | M);
759 hwsq_wr32(hwsq, 0x00c040, 0x00000030 | mast);
760 }
761
762 hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
763 hwsq_op5f(hwsq, 0x00, 0x00); /* wait for access enabled? */
764 hwsq_fini(hwsq);
765
766 return info;
767 error:
768 kfree(info);
769 return ERR_PTR(ret);
770 }
771
772 static int
773 prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq)
774 {
775 struct nouveau_device *device = nouveau_dev(dev);
776 struct nouveau_drm *drm = nouveau_drm(dev);
777 u32 hwsq_data, hwsq_kick;
778 int i;
779
780 if (nv_device(drm->device)->chipset < 0x94) {
781 hwsq_data = 0x001400;
782 hwsq_kick = 0x00000003;
783 } else {
784 hwsq_data = 0x080000;
785 hwsq_kick = 0x00000001;
786 }
787 /* upload hwsq ucode */
788 nv_mask(device, 0x001098, 0x00000008, 0x00000000);
789 nv_wr32(device, 0x001304, 0x00000000);
790 if (nv_device(drm->device)->chipset >= 0x92)
791 nv_wr32(device, 0x001318, 0x00000000);
792 for (i = 0; i < hwsq->len / 4; i++)
793 nv_wr32(device, hwsq_data + (i * 4), hwsq->ptr.u32[i]);
794 nv_mask(device, 0x001098, 0x00000018, 0x00000018);
795
796 /* launch, and wait for completion */
797 nv_wr32(device, 0x00130c, hwsq_kick);
798 if (!nv_wait(device, 0x001308, 0x00000100, 0x00000000)) {
799 NV_ERROR(drm, "hwsq ucode exec timed out\n");
800 NV_ERROR(drm, "0x001308: 0x%08x\n", nv_rd32(device, 0x001308));
801 for (i = 0; i < hwsq->len / 4; i++) {
802 NV_ERROR(drm, "0x%06x: 0x%08x\n", 0x1400 + (i * 4),
803 nv_rd32(device, 0x001400 + (i * 4)));
804 }
805
806 return -EIO;
807 }
808
809 return 0;
810 }
811
812 int
813 nv50_pm_clocks_set(struct drm_device *dev, void *data)
814 {
815 struct nouveau_device *device = nouveau_dev(dev);
816 struct nv50_pm_state *info = data;
817 struct bit_entry M;
818 int ret = -EBUSY;
819
820 /* halt and idle execution engines */
821 nv_mask(device, 0x002504, 0x00000001, 0x00000001);
822 if (!nv_wait(device, 0x002504, 0x00000010, 0x00000010))
823 goto resume;
824 if (!nv_wait(device, 0x00251c, 0x0000003f, 0x0000003f))
825 goto resume;
826
827 /* program memory clock, if necessary - must come before engine clock
828 * reprogramming due to how we construct the hwsq scripts in pre()
829 */
830 #define nouveau_bios_init_exec(a,b) nouveau_bios_run_init_table((a), (b), NULL, 0)
831 if (info->mclk_hwsq.len) {
832 /* execute some scripts that do ??? from the vbios.. */
833 if (!bit_table(dev, 'M', &M) && M.version == 1) {
834 if (M.length >= 6)
835 nouveau_bios_init_exec(dev, ROM16(M.data[5]));
836 if (M.length >= 8)
837 nouveau_bios_init_exec(dev, ROM16(M.data[7]));
838 if (M.length >= 10)
839 nouveau_bios_init_exec(dev, ROM16(M.data[9]));
840 nouveau_bios_init_exec(dev, info->mscript);
841 }
842
843 ret = prog_hwsq(dev, &info->mclk_hwsq);
844 if (ret)
845 goto resume;
846 }
847
848 /* program engine clocks */
849 ret = prog_hwsq(dev, &info->eclk_hwsq);
850
851 resume:
852 nv_mask(device, 0x002504, 0x00000001, 0x00000000);
853 kfree(info);
854 return ret;
855 }
Linux with added FPC-III support