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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / ni.c
blob474343adf262ce7643b8e08e236617aca291e705
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <drm/drmP.h>
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
31 #include "nid.h"
32 #include "atom.h"
33 #include "ni_reg.h"
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
37
38 static const u32 tn_rlc_save_restore_register_list[] =
39 {
40 0x98fc,
41 0x98f0,
42 0x9834,
43 0x9838,
44 0x9870,
45 0x9874,
46 0x8a14,
47 0x8b24,
48 0x8bcc,
49 0x8b10,
50 0x8c30,
51 0x8d00,
52 0x8d04,
53 0x8c00,
54 0x8c04,
55 0x8c10,
56 0x8c14,
57 0x8d8c,
58 0x8cf0,
59 0x8e38,
60 0x9508,
61 0x9688,
62 0x9608,
63 0x960c,
64 0x9610,
65 0x9614,
66 0x88c4,
67 0x8978,
68 0x88d4,
69 0x900c,
70 0x9100,
71 0x913c,
72 0x90e8,
73 0x9354,
74 0xa008,
75 0x98f8,
76 0x9148,
77 0x914c,
78 0x3f94,
79 0x98f4,
80 0x9b7c,
81 0x3f8c,
82 0x8950,
83 0x8954,
84 0x8a18,
85 0x8b28,
86 0x9144,
87 0x3f90,
88 0x915c,
89 0x9160,
90 0x9178,
91 0x917c,
92 0x9180,
93 0x918c,
94 0x9190,
95 0x9194,
96 0x9198,
97 0x919c,
98 0x91a8,
99 0x91ac,
100 0x91b0,
101 0x91b4,
102 0x91b8,
103 0x91c4,
104 0x91c8,
105 0x91cc,
106 0x91d0,
107 0x91d4,
108 0x91e0,
109 0x91e4,
110 0x91ec,
111 0x91f0,
112 0x91f4,
113 0x9200,
114 0x9204,
115 0x929c,
116 0x8030,
117 0x9150,
118 0x9a60,
119 0x920c,
120 0x9210,
121 0x9228,
122 0x922c,
123 0x9244,
124 0x9248,
125 0x91e8,
126 0x9294,
127 0x9208,
128 0x9224,
129 0x9240,
130 0x9220,
131 0x923c,
132 0x9258,
133 0x9744,
134 0xa200,
135 0xa204,
136 0xa208,
137 0xa20c,
138 0x8d58,
139 0x9030,
140 0x9034,
141 0x9038,
142 0x903c,
143 0x9040,
144 0x9654,
145 0x897c,
146 0xa210,
147 0xa214,
148 0x9868,
149 0xa02c,
150 0x9664,
151 0x9698,
152 0x949c,
153 0x8e10,
154 0x8e18,
155 0x8c50,
156 0x8c58,
157 0x8c60,
158 0x8c68,
159 0x89b4,
160 0x9830,
161 0x802c,
162 };
163
164 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
165 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
166 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
167 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
168 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
169 extern void evergreen_mc_program(struct radeon_device *rdev);
170 extern void evergreen_irq_suspend(struct radeon_device *rdev);
171 extern int evergreen_mc_init(struct radeon_device *rdev);
172 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
173 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174 extern void evergreen_program_aspm(struct radeon_device *rdev);
175 extern void sumo_rlc_fini(struct radeon_device *rdev);
176 extern int sumo_rlc_init(struct radeon_device *rdev);
177 extern void cayman_dma_vm_set_page(struct radeon_device *rdev,
178 struct radeon_ib *ib,
179 uint64_t pe,
180 uint64_t addr, unsigned count,
181 uint32_t incr, uint32_t flags);
182
183 /* Firmware Names */
184 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
185 MODULE_FIRMWARE("radeon/BARTS_me.bin");
186 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
187 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
188 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
189 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
190 MODULE_FIRMWARE("radeon/TURKS_me.bin");
191 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
192 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
193 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
194 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
195 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
196 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
197 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
198 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
199 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
200 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
201 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
202 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
203 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
204 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
205
206
207 static const u32 cayman_golden_registers2[] =
208 {
209 0x3e5c, 0xffffffff, 0x00000000,
210 0x3e48, 0xffffffff, 0x00000000,
211 0x3e4c, 0xffffffff, 0x00000000,
212 0x3e64, 0xffffffff, 0x00000000,
213 0x3e50, 0xffffffff, 0x00000000,
214 0x3e60, 0xffffffff, 0x00000000
215 };
216
217 static const u32 cayman_golden_registers[] =
218 {
219 0x5eb4, 0xffffffff, 0x00000002,
220 0x5e78, 0x8f311ff1, 0x001000f0,
221 0x3f90, 0xffff0000, 0xff000000,
222 0x9148, 0xffff0000, 0xff000000,
223 0x3f94, 0xffff0000, 0xff000000,
224 0x914c, 0xffff0000, 0xff000000,
225 0xc78, 0x00000080, 0x00000080,
226 0xbd4, 0x70073777, 0x00011003,
227 0xd02c, 0xbfffff1f, 0x08421000,
228 0xd0b8, 0x73773777, 0x02011003,
229 0x5bc0, 0x00200000, 0x50100000,
230 0x98f8, 0x33773777, 0x02011003,
231 0x98fc, 0xffffffff, 0x76541032,
232 0x7030, 0x31000311, 0x00000011,
233 0x2f48, 0x33773777, 0x42010001,
234 0x6b28, 0x00000010, 0x00000012,
235 0x7728, 0x00000010, 0x00000012,
236 0x10328, 0x00000010, 0x00000012,
237 0x10f28, 0x00000010, 0x00000012,
238 0x11b28, 0x00000010, 0x00000012,
239 0x12728, 0x00000010, 0x00000012,
240 0x240c, 0x000007ff, 0x00000000,
241 0x8a14, 0xf000001f, 0x00000007,
242 0x8b24, 0x3fff3fff, 0x00ff0fff,
243 0x8b10, 0x0000ff0f, 0x00000000,
244 0x28a4c, 0x07ffffff, 0x06000000,
245 0x10c, 0x00000001, 0x00010003,
246 0xa02c, 0xffffffff, 0x0000009b,
247 0x913c, 0x0000010f, 0x01000100,
248 0x8c04, 0xf8ff00ff, 0x40600060,
249 0x28350, 0x00000f01, 0x00000000,
250 0x9508, 0x3700001f, 0x00000002,
251 0x960c, 0xffffffff, 0x54763210,
252 0x88c4, 0x001f3ae3, 0x00000082,
253 0x88d0, 0xffffffff, 0x0f40df40,
254 0x88d4, 0x0000001f, 0x00000010,
255 0x8974, 0xffffffff, 0x00000000
256 };
257
258 static const u32 dvst_golden_registers2[] =
259 {
260 0x8f8, 0xffffffff, 0,
261 0x8fc, 0x00380000, 0,
262 0x8f8, 0xffffffff, 1,
263 0x8fc, 0x0e000000, 0
264 };
265
266 static const u32 dvst_golden_registers[] =
267 {
268 0x690, 0x3fff3fff, 0x20c00033,
269 0x918c, 0x0fff0fff, 0x00010006,
270 0x91a8, 0x0fff0fff, 0x00010006,
271 0x9150, 0xffffdfff, 0x6e944040,
272 0x917c, 0x0fff0fff, 0x00030002,
273 0x9198, 0x0fff0fff, 0x00030002,
274 0x915c, 0x0fff0fff, 0x00010000,
275 0x3f90, 0xffff0001, 0xff000000,
276 0x9178, 0x0fff0fff, 0x00070000,
277 0x9194, 0x0fff0fff, 0x00070000,
278 0x9148, 0xffff0001, 0xff000000,
279 0x9190, 0x0fff0fff, 0x00090008,
280 0x91ac, 0x0fff0fff, 0x00090008,
281 0x3f94, 0xffff0000, 0xff000000,
282 0x914c, 0xffff0000, 0xff000000,
283 0x929c, 0x00000fff, 0x00000001,
284 0x55e4, 0xff607fff, 0xfc000100,
285 0x8a18, 0xff000fff, 0x00000100,
286 0x8b28, 0xff000fff, 0x00000100,
287 0x9144, 0xfffc0fff, 0x00000100,
288 0x6ed8, 0x00010101, 0x00010000,
289 0x9830, 0xffffffff, 0x00000000,
290 0x9834, 0xf00fffff, 0x00000400,
291 0x9838, 0xfffffffe, 0x00000000,
292 0xd0c0, 0xff000fff, 0x00000100,
293 0xd02c, 0xbfffff1f, 0x08421000,
294 0xd0b8, 0x73773777, 0x12010001,
295 0x5bb0, 0x000000f0, 0x00000070,
296 0x98f8, 0x73773777, 0x12010001,
297 0x98fc, 0xffffffff, 0x00000010,
298 0x9b7c, 0x00ff0000, 0x00fc0000,
299 0x8030, 0x00001f0f, 0x0000100a,
300 0x2f48, 0x73773777, 0x12010001,
301 0x2408, 0x00030000, 0x000c007f,
302 0x8a14, 0xf000003f, 0x00000007,
303 0x8b24, 0x3fff3fff, 0x00ff0fff,
304 0x8b10, 0x0000ff0f, 0x00000000,
305 0x28a4c, 0x07ffffff, 0x06000000,
306 0x4d8, 0x00000fff, 0x00000100,
307 0xa008, 0xffffffff, 0x00010000,
308 0x913c, 0xffff03ff, 0x01000100,
309 0x8c00, 0x000000ff, 0x00000003,
310 0x8c04, 0xf8ff00ff, 0x40600060,
311 0x8cf0, 0x1fff1fff, 0x08e00410,
312 0x28350, 0x00000f01, 0x00000000,
313 0x9508, 0xf700071f, 0x00000002,
314 0x960c, 0xffffffff, 0x54763210,
315 0x20ef8, 0x01ff01ff, 0x00000002,
316 0x20e98, 0xfffffbff, 0x00200000,
317 0x2015c, 0xffffffff, 0x00000f40,
318 0x88c4, 0x001f3ae3, 0x00000082,
319 0x8978, 0x3fffffff, 0x04050140,
320 0x88d4, 0x0000001f, 0x00000010,
321 0x8974, 0xffffffff, 0x00000000
322 };
323
324 static const u32 scrapper_golden_registers[] =
325 {
326 0x690, 0x3fff3fff, 0x20c00033,
327 0x918c, 0x0fff0fff, 0x00010006,
328 0x918c, 0x0fff0fff, 0x00010006,
329 0x91a8, 0x0fff0fff, 0x00010006,
330 0x91a8, 0x0fff0fff, 0x00010006,
331 0x9150, 0xffffdfff, 0x6e944040,
332 0x9150, 0xffffdfff, 0x6e944040,
333 0x917c, 0x0fff0fff, 0x00030002,
334 0x917c, 0x0fff0fff, 0x00030002,
335 0x9198, 0x0fff0fff, 0x00030002,
336 0x9198, 0x0fff0fff, 0x00030002,
337 0x915c, 0x0fff0fff, 0x00010000,
338 0x915c, 0x0fff0fff, 0x00010000,
339 0x3f90, 0xffff0001, 0xff000000,
340 0x3f90, 0xffff0001, 0xff000000,
341 0x9178, 0x0fff0fff, 0x00070000,
342 0x9178, 0x0fff0fff, 0x00070000,
343 0x9194, 0x0fff0fff, 0x00070000,
344 0x9194, 0x0fff0fff, 0x00070000,
345 0x9148, 0xffff0001, 0xff000000,
346 0x9148, 0xffff0001, 0xff000000,
347 0x9190, 0x0fff0fff, 0x00090008,
348 0x9190, 0x0fff0fff, 0x00090008,
349 0x91ac, 0x0fff0fff, 0x00090008,
350 0x91ac, 0x0fff0fff, 0x00090008,
351 0x3f94, 0xffff0000, 0xff000000,
352 0x3f94, 0xffff0000, 0xff000000,
353 0x914c, 0xffff0000, 0xff000000,
354 0x914c, 0xffff0000, 0xff000000,
355 0x929c, 0x00000fff, 0x00000001,
356 0x929c, 0x00000fff, 0x00000001,
357 0x55e4, 0xff607fff, 0xfc000100,
358 0x8a18, 0xff000fff, 0x00000100,
359 0x8a18, 0xff000fff, 0x00000100,
360 0x8b28, 0xff000fff, 0x00000100,
361 0x8b28, 0xff000fff, 0x00000100,
362 0x9144, 0xfffc0fff, 0x00000100,
363 0x9144, 0xfffc0fff, 0x00000100,
364 0x6ed8, 0x00010101, 0x00010000,
365 0x9830, 0xffffffff, 0x00000000,
366 0x9830, 0xffffffff, 0x00000000,
367 0x9834, 0xf00fffff, 0x00000400,
368 0x9834, 0xf00fffff, 0x00000400,
369 0x9838, 0xfffffffe, 0x00000000,
370 0x9838, 0xfffffffe, 0x00000000,
371 0xd0c0, 0xff000fff, 0x00000100,
372 0xd02c, 0xbfffff1f, 0x08421000,
373 0xd02c, 0xbfffff1f, 0x08421000,
374 0xd0b8, 0x73773777, 0x12010001,
375 0xd0b8, 0x73773777, 0x12010001,
376 0x5bb0, 0x000000f0, 0x00000070,
377 0x98f8, 0x73773777, 0x12010001,
378 0x98f8, 0x73773777, 0x12010001,
379 0x98fc, 0xffffffff, 0x00000010,
380 0x98fc, 0xffffffff, 0x00000010,
381 0x9b7c, 0x00ff0000, 0x00fc0000,
382 0x9b7c, 0x00ff0000, 0x00fc0000,
383 0x8030, 0x00001f0f, 0x0000100a,
384 0x8030, 0x00001f0f, 0x0000100a,
385 0x2f48, 0x73773777, 0x12010001,
386 0x2f48, 0x73773777, 0x12010001,
387 0x2408, 0x00030000, 0x000c007f,
388 0x8a14, 0xf000003f, 0x00000007,
389 0x8a14, 0xf000003f, 0x00000007,
390 0x8b24, 0x3fff3fff, 0x00ff0fff,
391 0x8b24, 0x3fff3fff, 0x00ff0fff,
392 0x8b10, 0x0000ff0f, 0x00000000,
393 0x8b10, 0x0000ff0f, 0x00000000,
394 0x28a4c, 0x07ffffff, 0x06000000,
395 0x28a4c, 0x07ffffff, 0x06000000,
396 0x4d8, 0x00000fff, 0x00000100,
397 0x4d8, 0x00000fff, 0x00000100,
398 0xa008, 0xffffffff, 0x00010000,
399 0xa008, 0xffffffff, 0x00010000,
400 0x913c, 0xffff03ff, 0x01000100,
401 0x913c, 0xffff03ff, 0x01000100,
402 0x90e8, 0x001fffff, 0x010400c0,
403 0x8c00, 0x000000ff, 0x00000003,
404 0x8c00, 0x000000ff, 0x00000003,
405 0x8c04, 0xf8ff00ff, 0x40600060,
406 0x8c04, 0xf8ff00ff, 0x40600060,
407 0x8c30, 0x0000000f, 0x00040005,
408 0x8cf0, 0x1fff1fff, 0x08e00410,
409 0x8cf0, 0x1fff1fff, 0x08e00410,
410 0x900c, 0x00ffffff, 0x0017071f,
411 0x28350, 0x00000f01, 0x00000000,
412 0x28350, 0x00000f01, 0x00000000,
413 0x9508, 0xf700071f, 0x00000002,
414 0x9508, 0xf700071f, 0x00000002,
415 0x9688, 0x00300000, 0x0017000f,
416 0x960c, 0xffffffff, 0x54763210,
417 0x960c, 0xffffffff, 0x54763210,
418 0x20ef8, 0x01ff01ff, 0x00000002,
419 0x20e98, 0xfffffbff, 0x00200000,
420 0x2015c, 0xffffffff, 0x00000f40,
421 0x88c4, 0x001f3ae3, 0x00000082,
422 0x88c4, 0x001f3ae3, 0x00000082,
423 0x8978, 0x3fffffff, 0x04050140,
424 0x8978, 0x3fffffff, 0x04050140,
425 0x88d4, 0x0000001f, 0x00000010,
426 0x88d4, 0x0000001f, 0x00000010,
427 0x8974, 0xffffffff, 0x00000000,
428 0x8974, 0xffffffff, 0x00000000
429 };
430
431 static void ni_init_golden_registers(struct radeon_device *rdev)
432 {
433 switch (rdev->family) {
434 case CHIP_CAYMAN:
435 radeon_program_register_sequence(rdev,
436 cayman_golden_registers,
437 (const u32)ARRAY_SIZE(cayman_golden_registers));
438 radeon_program_register_sequence(rdev,
439 cayman_golden_registers2,
440 (const u32)ARRAY_SIZE(cayman_golden_registers2));
441 break;
442 case CHIP_ARUBA:
443 if ((rdev->pdev->device == 0x9900) ||
444 (rdev->pdev->device == 0x9901) ||
445 (rdev->pdev->device == 0x9903) ||
446 (rdev->pdev->device == 0x9904) ||
447 (rdev->pdev->device == 0x9905) ||
448 (rdev->pdev->device == 0x9906) ||
449 (rdev->pdev->device == 0x9907) ||
450 (rdev->pdev->device == 0x9908) ||
451 (rdev->pdev->device == 0x9909) ||
452 (rdev->pdev->device == 0x990A) ||
453 (rdev->pdev->device == 0x990B) ||
454 (rdev->pdev->device == 0x990C) ||
455 (rdev->pdev->device == 0x990D) ||
456 (rdev->pdev->device == 0x990E) ||
457 (rdev->pdev->device == 0x990F) ||
458 (rdev->pdev->device == 0x9910) ||
459 (rdev->pdev->device == 0x9913) ||
460 (rdev->pdev->device == 0x9917) ||
461 (rdev->pdev->device == 0x9918)) {
462 radeon_program_register_sequence(rdev,
463 dvst_golden_registers,
464 (const u32)ARRAY_SIZE(dvst_golden_registers));
465 radeon_program_register_sequence(rdev,
466 dvst_golden_registers2,
467 (const u32)ARRAY_SIZE(dvst_golden_registers2));
468 } else {
469 radeon_program_register_sequence(rdev,
470 scrapper_golden_registers,
471 (const u32)ARRAY_SIZE(scrapper_golden_registers));
472 radeon_program_register_sequence(rdev,
473 dvst_golden_registers2,
474 (const u32)ARRAY_SIZE(dvst_golden_registers2));
475 }
476 break;
477 default:
478 break;
479 }
480 }
481
482 #define BTC_IO_MC_REGS_SIZE 29
483
484 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
485 {0x00000077, 0xff010100},
486 {0x00000078, 0x00000000},
487 {0x00000079, 0x00001434},
488 {0x0000007a, 0xcc08ec08},
489 {0x0000007b, 0x00040000},
490 {0x0000007c, 0x000080c0},
491 {0x0000007d, 0x09000000},
492 {0x0000007e, 0x00210404},
493 {0x00000081, 0x08a8e800},
494 {0x00000082, 0x00030444},
495 {0x00000083, 0x00000000},
496 {0x00000085, 0x00000001},
497 {0x00000086, 0x00000002},
498 {0x00000087, 0x48490000},
499 {0x00000088, 0x20244647},
500 {0x00000089, 0x00000005},
501 {0x0000008b, 0x66030000},
502 {0x0000008c, 0x00006603},
503 {0x0000008d, 0x00000100},
504 {0x0000008f, 0x00001c0a},
505 {0x00000090, 0xff000001},
506 {0x00000094, 0x00101101},
507 {0x00000095, 0x00000fff},
508 {0x00000096, 0x00116fff},
509 {0x00000097, 0x60010000},
510 {0x00000098, 0x10010000},
511 {0x00000099, 0x00006000},
512 {0x0000009a, 0x00001000},
513 {0x0000009f, 0x00946a00}
514 };
515
516 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
517 {0x00000077, 0xff010100},
518 {0x00000078, 0x00000000},
519 {0x00000079, 0x00001434},
520 {0x0000007a, 0xcc08ec08},
521 {0x0000007b, 0x00040000},
522 {0x0000007c, 0x000080c0},
523 {0x0000007d, 0x09000000},
524 {0x0000007e, 0x00210404},
525 {0x00000081, 0x08a8e800},
526 {0x00000082, 0x00030444},
527 {0x00000083, 0x00000000},
528 {0x00000085, 0x00000001},
529 {0x00000086, 0x00000002},
530 {0x00000087, 0x48490000},
531 {0x00000088, 0x20244647},
532 {0x00000089, 0x00000005},
533 {0x0000008b, 0x66030000},
534 {0x0000008c, 0x00006603},
535 {0x0000008d, 0x00000100},
536 {0x0000008f, 0x00001c0a},
537 {0x00000090, 0xff000001},
538 {0x00000094, 0x00101101},
539 {0x00000095, 0x00000fff},
540 {0x00000096, 0x00116fff},
541 {0x00000097, 0x60010000},
542 {0x00000098, 0x10010000},
543 {0x00000099, 0x00006000},
544 {0x0000009a, 0x00001000},
545 {0x0000009f, 0x00936a00}
546 };
547
548 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
549 {0x00000077, 0xff010100},
550 {0x00000078, 0x00000000},
551 {0x00000079, 0x00001434},
552 {0x0000007a, 0xcc08ec08},
553 {0x0000007b, 0x00040000},
554 {0x0000007c, 0x000080c0},
555 {0x0000007d, 0x09000000},
556 {0x0000007e, 0x00210404},
557 {0x00000081, 0x08a8e800},
558 {0x00000082, 0x00030444},
559 {0x00000083, 0x00000000},
560 {0x00000085, 0x00000001},
561 {0x00000086, 0x00000002},
562 {0x00000087, 0x48490000},
563 {0x00000088, 0x20244647},
564 {0x00000089, 0x00000005},
565 {0x0000008b, 0x66030000},
566 {0x0000008c, 0x00006603},
567 {0x0000008d, 0x00000100},
568 {0x0000008f, 0x00001c0a},
569 {0x00000090, 0xff000001},
570 {0x00000094, 0x00101101},
571 {0x00000095, 0x00000fff},
572 {0x00000096, 0x00116fff},
573 {0x00000097, 0x60010000},
574 {0x00000098, 0x10010000},
575 {0x00000099, 0x00006000},
576 {0x0000009a, 0x00001000},
577 {0x0000009f, 0x00916a00}
578 };
579
580 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
581 {0x00000077, 0xff010100},
582 {0x00000078, 0x00000000},
583 {0x00000079, 0x00001434},
584 {0x0000007a, 0xcc08ec08},
585 {0x0000007b, 0x00040000},
586 {0x0000007c, 0x000080c0},
587 {0x0000007d, 0x09000000},
588 {0x0000007e, 0x00210404},
589 {0x00000081, 0x08a8e800},
590 {0x00000082, 0x00030444},
591 {0x00000083, 0x00000000},
592 {0x00000085, 0x00000001},
593 {0x00000086, 0x00000002},
594 {0x00000087, 0x48490000},
595 {0x00000088, 0x20244647},
596 {0x00000089, 0x00000005},
597 {0x0000008b, 0x66030000},
598 {0x0000008c, 0x00006603},
599 {0x0000008d, 0x00000100},
600 {0x0000008f, 0x00001c0a},
601 {0x00000090, 0xff000001},
602 {0x00000094, 0x00101101},
603 {0x00000095, 0x00000fff},
604 {0x00000096, 0x00116fff},
605 {0x00000097, 0x60010000},
606 {0x00000098, 0x10010000},
607 {0x00000099, 0x00006000},
608 {0x0000009a, 0x00001000},
609 {0x0000009f, 0x00976b00}
610 };
611
612 int ni_mc_load_microcode(struct radeon_device *rdev)
613 {
614 const __be32 *fw_data;
615 u32 mem_type, running, blackout = 0;
616 u32 *io_mc_regs;
617 int i, ucode_size, regs_size;
618
619 if (!rdev->mc_fw)
620 return -EINVAL;
621
622 switch (rdev->family) {
623 case CHIP_BARTS:
624 io_mc_regs = (u32 *)&barts_io_mc_regs;
625 ucode_size = BTC_MC_UCODE_SIZE;
626 regs_size = BTC_IO_MC_REGS_SIZE;
627 break;
628 case CHIP_TURKS:
629 io_mc_regs = (u32 *)&turks_io_mc_regs;
630 ucode_size = BTC_MC_UCODE_SIZE;
631 regs_size = BTC_IO_MC_REGS_SIZE;
632 break;
633 case CHIP_CAICOS:
634 default:
635 io_mc_regs = (u32 *)&caicos_io_mc_regs;
636 ucode_size = BTC_MC_UCODE_SIZE;
637 regs_size = BTC_IO_MC_REGS_SIZE;
638 break;
639 case CHIP_CAYMAN:
640 io_mc_regs = (u32 *)&cayman_io_mc_regs;
641 ucode_size = CAYMAN_MC_UCODE_SIZE;
642 regs_size = BTC_IO_MC_REGS_SIZE;
643 break;
644 }
645
646 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
647 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
648
649 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
650 if (running) {
651 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
652 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
653 }
654
655 /* reset the engine and set to writable */
656 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
657 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
658
659 /* load mc io regs */
660 for (i = 0; i < regs_size; i++) {
661 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
662 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
663 }
664 /* load the MC ucode */
665 fw_data = (const __be32 *)rdev->mc_fw->data;
666 for (i = 0; i < ucode_size; i++)
667 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
668
669 /* put the engine back into the active state */
670 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
671 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
672 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
673
674 /* wait for training to complete */
675 for (i = 0; i < rdev->usec_timeout; i++) {
676 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
677 break;
678 udelay(1);
679 }
680
681 if (running)
682 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
683 }
684
685 return 0;
686 }
687
688 int ni_init_microcode(struct radeon_device *rdev)
689 {
690 const char *chip_name;
691 const char *rlc_chip_name;
692 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
693 size_t smc_req_size = 0;
694 char fw_name[30];
695 int err;
696
697 DRM_DEBUG("\n");
698
699 switch (rdev->family) {
700 case CHIP_BARTS:
701 chip_name = "BARTS";
702 rlc_chip_name = "BTC";
703 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
704 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
705 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
706 mc_req_size = BTC_MC_UCODE_SIZE * 4;
707 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
708 break;
709 case CHIP_TURKS:
710 chip_name = "TURKS";
711 rlc_chip_name = "BTC";
712 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
713 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
714 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
715 mc_req_size = BTC_MC_UCODE_SIZE * 4;
716 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
717 break;
718 case CHIP_CAICOS:
719 chip_name = "CAICOS";
720 rlc_chip_name = "BTC";
721 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
722 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
723 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
724 mc_req_size = BTC_MC_UCODE_SIZE * 4;
725 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
726 break;
727 case CHIP_CAYMAN:
728 chip_name = "CAYMAN";
729 rlc_chip_name = "CAYMAN";
730 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
731 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
732 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
733 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
734 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
735 break;
736 case CHIP_ARUBA:
737 chip_name = "ARUBA";
738 rlc_chip_name = "ARUBA";
739 /* pfp/me same size as CAYMAN */
740 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
741 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
742 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
743 mc_req_size = 0;
744 break;
745 default: BUG();
746 }
747
748 DRM_INFO("Loading %s Microcode\n", chip_name);
749
750 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
751 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
752 if (err)
753 goto out;
754 if (rdev->pfp_fw->size != pfp_req_size) {
755 printk(KERN_ERR
756 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
757 rdev->pfp_fw->size, fw_name);
758 err = -EINVAL;
759 goto out;
760 }
761
762 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
763 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
764 if (err)
765 goto out;
766 if (rdev->me_fw->size != me_req_size) {
767 printk(KERN_ERR
768 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
769 rdev->me_fw->size, fw_name);
770 err = -EINVAL;
771 }
772
773 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
774 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
775 if (err)
776 goto out;
777 if (rdev->rlc_fw->size != rlc_req_size) {
778 printk(KERN_ERR
779 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
780 rdev->rlc_fw->size, fw_name);
781 err = -EINVAL;
782 }
783
784 /* no MC ucode on TN */
785 if (!(rdev->flags & RADEON_IS_IGP)) {
786 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
787 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
788 if (err)
789 goto out;
790 if (rdev->mc_fw->size != mc_req_size) {
791 printk(KERN_ERR
792 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
793 rdev->mc_fw->size, fw_name);
794 err = -EINVAL;
795 }
796 }
797
798 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
799 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
800 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
801 if (err) {
802 printk(KERN_ERR
803 "smc: error loading firmware \"%s\"\n",
804 fw_name);
805 release_firmware(rdev->smc_fw);
806 rdev->smc_fw = NULL;
807 err = 0;
808 } else if (rdev->smc_fw->size != smc_req_size) {
809 printk(KERN_ERR
810 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
811 rdev->mc_fw->size, fw_name);
812 err = -EINVAL;
813 }
814 }
815
816 out:
817 if (err) {
818 if (err != -EINVAL)
819 printk(KERN_ERR
820 "ni_cp: Failed to load firmware \"%s\"\n",
821 fw_name);
822 release_firmware(rdev->pfp_fw);
823 rdev->pfp_fw = NULL;
824 release_firmware(rdev->me_fw);
825 rdev->me_fw = NULL;
826 release_firmware(rdev->rlc_fw);
827 rdev->rlc_fw = NULL;
828 release_firmware(rdev->mc_fw);
829 rdev->mc_fw = NULL;
830 }
831 return err;
832 }
833
834 int tn_get_temp(struct radeon_device *rdev)
835 {
836 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
837 int actual_temp = (temp / 8) - 49;
838
839 return actual_temp * 1000;
840 }
841
842 /*
843 * Core functions
844 */
845 static void cayman_gpu_init(struct radeon_device *rdev)
846 {
847 u32 gb_addr_config = 0;
848 u32 mc_shared_chmap, mc_arb_ramcfg;
849 u32 cgts_tcc_disable;
850 u32 sx_debug_1;
851 u32 smx_dc_ctl0;
852 u32 cgts_sm_ctrl_reg;
853 u32 hdp_host_path_cntl;
854 u32 tmp;
855 u32 disabled_rb_mask;
856 int i, j;
857
858 switch (rdev->family) {
859 case CHIP_CAYMAN:
860 rdev->config.cayman.max_shader_engines = 2;
861 rdev->config.cayman.max_pipes_per_simd = 4;
862 rdev->config.cayman.max_tile_pipes = 8;
863 rdev->config.cayman.max_simds_per_se = 12;
864 rdev->config.cayman.max_backends_per_se = 4;
865 rdev->config.cayman.max_texture_channel_caches = 8;
866 rdev->config.cayman.max_gprs = 256;
867 rdev->config.cayman.max_threads = 256;
868 rdev->config.cayman.max_gs_threads = 32;
869 rdev->config.cayman.max_stack_entries = 512;
870 rdev->config.cayman.sx_num_of_sets = 8;
871 rdev->config.cayman.sx_max_export_size = 256;
872 rdev->config.cayman.sx_max_export_pos_size = 64;
873 rdev->config.cayman.sx_max_export_smx_size = 192;
874 rdev->config.cayman.max_hw_contexts = 8;
875 rdev->config.cayman.sq_num_cf_insts = 2;
876
877 rdev->config.cayman.sc_prim_fifo_size = 0x100;
878 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
879 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
880 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
881 break;
882 case CHIP_ARUBA:
883 default:
884 rdev->config.cayman.max_shader_engines = 1;
885 rdev->config.cayman.max_pipes_per_simd = 4;
886 rdev->config.cayman.max_tile_pipes = 2;
887 if ((rdev->pdev->device == 0x9900) ||
888 (rdev->pdev->device == 0x9901) ||
889 (rdev->pdev->device == 0x9905) ||
890 (rdev->pdev->device == 0x9906) ||
891 (rdev->pdev->device == 0x9907) ||
892 (rdev->pdev->device == 0x9908) ||
893 (rdev->pdev->device == 0x9909) ||
894 (rdev->pdev->device == 0x990B) ||
895 (rdev->pdev->device == 0x990C) ||
896 (rdev->pdev->device == 0x990F) ||
897 (rdev->pdev->device == 0x9910) ||
898 (rdev->pdev->device == 0x9917) ||
899 (rdev->pdev->device == 0x9999) ||
900 (rdev->pdev->device == 0x999C)) {
901 rdev->config.cayman.max_simds_per_se = 6;
902 rdev->config.cayman.max_backends_per_se = 2;
903 rdev->config.cayman.max_hw_contexts = 8;
904 rdev->config.cayman.sx_max_export_size = 256;
905 rdev->config.cayman.sx_max_export_pos_size = 64;
906 rdev->config.cayman.sx_max_export_smx_size = 192;
907 } else if ((rdev->pdev->device == 0x9903) ||
908 (rdev->pdev->device == 0x9904) ||
909 (rdev->pdev->device == 0x990A) ||
910 (rdev->pdev->device == 0x990D) ||
911 (rdev->pdev->device == 0x990E) ||
912 (rdev->pdev->device == 0x9913) ||
913 (rdev->pdev->device == 0x9918) ||
914 (rdev->pdev->device == 0x999D)) {
915 rdev->config.cayman.max_simds_per_se = 4;
916 rdev->config.cayman.max_backends_per_se = 2;
917 rdev->config.cayman.max_hw_contexts = 8;
918 rdev->config.cayman.sx_max_export_size = 256;
919 rdev->config.cayman.sx_max_export_pos_size = 64;
920 rdev->config.cayman.sx_max_export_smx_size = 192;
921 } else if ((rdev->pdev->device == 0x9919) ||
922 (rdev->pdev->device == 0x9990) ||
923 (rdev->pdev->device == 0x9991) ||
924 (rdev->pdev->device == 0x9994) ||
925 (rdev->pdev->device == 0x9995) ||
926 (rdev->pdev->device == 0x9996) ||
927 (rdev->pdev->device == 0x999A) ||
928 (rdev->pdev->device == 0x99A0)) {
929 rdev->config.cayman.max_simds_per_se = 3;
930 rdev->config.cayman.max_backends_per_se = 1;
931 rdev->config.cayman.max_hw_contexts = 4;
932 rdev->config.cayman.sx_max_export_size = 128;
933 rdev->config.cayman.sx_max_export_pos_size = 32;
934 rdev->config.cayman.sx_max_export_smx_size = 96;
935 } else {
936 rdev->config.cayman.max_simds_per_se = 2;
937 rdev->config.cayman.max_backends_per_se = 1;
938 rdev->config.cayman.max_hw_contexts = 4;
939 rdev->config.cayman.sx_max_export_size = 128;
940 rdev->config.cayman.sx_max_export_pos_size = 32;
941 rdev->config.cayman.sx_max_export_smx_size = 96;
942 }
943 rdev->config.cayman.max_texture_channel_caches = 2;
944 rdev->config.cayman.max_gprs = 256;
945 rdev->config.cayman.max_threads = 256;
946 rdev->config.cayman.max_gs_threads = 32;
947 rdev->config.cayman.max_stack_entries = 512;
948 rdev->config.cayman.sx_num_of_sets = 8;
949 rdev->config.cayman.sq_num_cf_insts = 2;
950
951 rdev->config.cayman.sc_prim_fifo_size = 0x40;
952 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
953 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
954 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
955 break;
956 }
957
958 /* Initialize HDP */
959 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
960 WREG32((0x2c14 + j), 0x00000000);
961 WREG32((0x2c18 + j), 0x00000000);
962 WREG32((0x2c1c + j), 0x00000000);
963 WREG32((0x2c20 + j), 0x00000000);
964 WREG32((0x2c24 + j), 0x00000000);
965 }
966
967 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
968
969 evergreen_fix_pci_max_read_req_size(rdev);
970
971 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
972 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
973
974 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
975 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
976 if (rdev->config.cayman.mem_row_size_in_kb > 4)
977 rdev->config.cayman.mem_row_size_in_kb = 4;
978 /* XXX use MC settings? */
979 rdev->config.cayman.shader_engine_tile_size = 32;
980 rdev->config.cayman.num_gpus = 1;
981 rdev->config.cayman.multi_gpu_tile_size = 64;
982
983 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
984 rdev->config.cayman.num_tile_pipes = (1 << tmp);
985 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
986 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
987 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
988 rdev->config.cayman.num_shader_engines = tmp + 1;
989 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
990 rdev->config.cayman.num_gpus = tmp + 1;
991 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
992 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
993 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
994 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
995
996
997 /* setup tiling info dword. gb_addr_config is not adequate since it does
998 * not have bank info, so create a custom tiling dword.
999 * bits 3:0 num_pipes
1000 * bits 7:4 num_banks
1001 * bits 11:8 group_size
1002 * bits 15:12 row_size
1003 */
1004 rdev->config.cayman.tile_config = 0;
1005 switch (rdev->config.cayman.num_tile_pipes) {
1006 case 1:
1007 default:
1008 rdev->config.cayman.tile_config |= (0 << 0);
1009 break;
1010 case 2:
1011 rdev->config.cayman.tile_config |= (1 << 0);
1012 break;
1013 case 4:
1014 rdev->config.cayman.tile_config |= (2 << 0);
1015 break;
1016 case 8:
1017 rdev->config.cayman.tile_config |= (3 << 0);
1018 break;
1019 }
1020
1021 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1022 if (rdev->flags & RADEON_IS_IGP)
1023 rdev->config.cayman.tile_config |= 1 << 4;
1024 else {
1025 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1026 case 0: /* four banks */
1027 rdev->config.cayman.tile_config |= 0 << 4;
1028 break;
1029 case 1: /* eight banks */
1030 rdev->config.cayman.tile_config |= 1 << 4;
1031 break;
1032 case 2: /* sixteen banks */
1033 default:
1034 rdev->config.cayman.tile_config |= 2 << 4;
1035 break;
1036 }
1037 }
1038 rdev->config.cayman.tile_config |=
1039 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1040 rdev->config.cayman.tile_config |=
1041 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1042
1043 tmp = 0;
1044 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1045 u32 rb_disable_bitmap;
1046
1047 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1048 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1049 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1050 tmp <<= 4;
1051 tmp |= rb_disable_bitmap;
1052 }
1053 /* enabled rb are just the one not disabled :) */
1054 disabled_rb_mask = tmp;
1055 tmp = 0;
1056 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1057 tmp |= (1 << i);
1058 /* if all the backends are disabled, fix it up here */
1059 if ((disabled_rb_mask & tmp) == tmp) {
1060 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1061 disabled_rb_mask &= ~(1 << i);
1062 }
1063
1064 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1065 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1066
1067 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1068 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1069 if (ASIC_IS_DCE6(rdev))
1070 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1071 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1072 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1073 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1074 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1075 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1076 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1077
1078 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1079 (rdev->flags & RADEON_IS_IGP)) {
1080 if ((disabled_rb_mask & 3) == 1) {
1081 /* RB0 disabled, RB1 enabled */
1082 tmp = 0x11111111;
1083 } else {
1084 /* RB1 disabled, RB0 enabled */
1085 tmp = 0x00000000;
1086 }
1087 } else {
1088 tmp = gb_addr_config & NUM_PIPES_MASK;
1089 tmp = r6xx_remap_render_backend(rdev, tmp,
1090 rdev->config.cayman.max_backends_per_se *
1091 rdev->config.cayman.max_shader_engines,
1092 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1093 }
1094 WREG32(GB_BACKEND_MAP, tmp);
1095
1096 cgts_tcc_disable = 0xffff0000;
1097 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1098 cgts_tcc_disable &= ~(1 << (16 + i));
1099 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1100 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1101 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1102 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1103
1104 /* reprogram the shader complex */
1105 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1106 for (i = 0; i < 16; i++)
1107 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1108 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1109
1110 /* set HW defaults for 3D engine */
1111 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1112
1113 sx_debug_1 = RREG32(SX_DEBUG_1);
1114 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1115 WREG32(SX_DEBUG_1, sx_debug_1);
1116
1117 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1118 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1119 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1120 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1121
1122 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1123
1124 /* need to be explicitly zero-ed */
1125 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1126 WREG32(SQ_LSTMP_RING_BASE, 0);
1127 WREG32(SQ_HSTMP_RING_BASE, 0);
1128 WREG32(SQ_ESTMP_RING_BASE, 0);
1129 WREG32(SQ_GSTMP_RING_BASE, 0);
1130 WREG32(SQ_VSTMP_RING_BASE, 0);
1131 WREG32(SQ_PSTMP_RING_BASE, 0);
1132
1133 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1134
1135 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1136 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1137 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1138
1139 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1140 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1141 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1142
1143
1144 WREG32(VGT_NUM_INSTANCES, 1);
1145
1146 WREG32(CP_PERFMON_CNTL, 0);
1147
1148 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1149 FETCH_FIFO_HIWATER(0x4) |
1150 DONE_FIFO_HIWATER(0xe0) |
1151 ALU_UPDATE_FIFO_HIWATER(0x8)));
1152
1153 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1154 WREG32(SQ_CONFIG, (VC_ENABLE |
1155 EXPORT_SRC_C |
1156 GFX_PRIO(0) |
1157 CS1_PRIO(0) |
1158 CS2_PRIO(1)));
1159 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1160
1161 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1162 FORCE_EOV_MAX_REZ_CNT(255)));
1163
1164 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1165 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1166
1167 WREG32(VGT_GS_VERTEX_REUSE, 16);
1168 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1169
1170 WREG32(CB_PERF_CTR0_SEL_0, 0);
1171 WREG32(CB_PERF_CTR0_SEL_1, 0);
1172 WREG32(CB_PERF_CTR1_SEL_0, 0);
1173 WREG32(CB_PERF_CTR1_SEL_1, 0);
1174 WREG32(CB_PERF_CTR2_SEL_0, 0);
1175 WREG32(CB_PERF_CTR2_SEL_1, 0);
1176 WREG32(CB_PERF_CTR3_SEL_0, 0);
1177 WREG32(CB_PERF_CTR3_SEL_1, 0);
1178
1179 tmp = RREG32(HDP_MISC_CNTL);
1180 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1181 WREG32(HDP_MISC_CNTL, tmp);
1182
1183 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1184 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1185
1186 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1187
1188 udelay(50);
1189
1190 /* set clockgating golden values on TN */
1191 if (rdev->family == CHIP_ARUBA) {
1192 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1193 tmp &= ~0x00380000;
1194 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1195 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1196 tmp &= ~0x0e000000;
1197 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1198 }
1199 }
1200
1201 /*
1202 * GART
1203 */
1204 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1205 {
1206 /* flush hdp cache */
1207 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1208
1209 /* bits 0-7 are the VM contexts0-7 */
1210 WREG32(VM_INVALIDATE_REQUEST, 1);
1211 }
1212
1213 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1214 {
1215 int i, r;
1216
1217 if (rdev->gart.robj == NULL) {
1218 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1219 return -EINVAL;
1220 }
1221 r = radeon_gart_table_vram_pin(rdev);
1222 if (r)
1223 return r;
1224 radeon_gart_restore(rdev);
1225 /* Setup TLB control */
1226 WREG32(MC_VM_MX_L1_TLB_CNTL,
1227 (0xA << 7) |
1228 ENABLE_L1_TLB |
1229 ENABLE_L1_FRAGMENT_PROCESSING |
1230 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1231 ENABLE_ADVANCED_DRIVER_MODEL |
1232 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1233 /* Setup L2 cache */
1234 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1235 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1236 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1237 EFFECTIVE_L2_QUEUE_SIZE(7) |
1238 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1239 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1240 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1241 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1242 /* setup context0 */
1243 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1244 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1245 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1246 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1247 (u32)(rdev->dummy_page.addr >> 12));
1248 WREG32(VM_CONTEXT0_CNTL2, 0);
1249 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1250 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1251
1252 WREG32(0x15D4, 0);
1253 WREG32(0x15D8, 0);
1254 WREG32(0x15DC, 0);
1255
1256 /* empty context1-7 */
1257 /* Assign the pt base to something valid for now; the pts used for
1258 * the VMs are determined by the application and setup and assigned
1259 * on the fly in the vm part of radeon_gart.c
1260 */
1261 for (i = 1; i < 8; i++) {
1262 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1263 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1264 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1265 rdev->gart.table_addr >> 12);
1266 }
1267
1268 /* enable context1-7 */
1269 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1270 (u32)(rdev->dummy_page.addr >> 12));
1271 WREG32(VM_CONTEXT1_CNTL2, 4);
1272 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1273 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1274 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1275 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1276 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1277 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1278 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1279 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1280 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1281 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1282 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1283 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1284 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1285
1286 cayman_pcie_gart_tlb_flush(rdev);
1287 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1288 (unsigned)(rdev->mc.gtt_size >> 20),
1289 (unsigned long long)rdev->gart.table_addr);
1290 rdev->gart.ready = true;
1291 return 0;
1292 }
1293
1294 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1295 {
1296 /* Disable all tables */
1297 WREG32(VM_CONTEXT0_CNTL, 0);
1298 WREG32(VM_CONTEXT1_CNTL, 0);
1299 /* Setup TLB control */
1300 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1301 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1302 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1303 /* Setup L2 cache */
1304 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1305 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1306 EFFECTIVE_L2_QUEUE_SIZE(7) |
1307 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1308 WREG32(VM_L2_CNTL2, 0);
1309 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1310 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1311 radeon_gart_table_vram_unpin(rdev);
1312 }
1313
1314 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1315 {
1316 cayman_pcie_gart_disable(rdev);
1317 radeon_gart_table_vram_free(rdev);
1318 radeon_gart_fini(rdev);
1319 }
1320
1321 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1322 int ring, u32 cp_int_cntl)
1323 {
1324 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1325
1326 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1327 WREG32(CP_INT_CNTL, cp_int_cntl);
1328 }
1329
1330 /*
1331 * CP.
1332 */
1333 void cayman_fence_ring_emit(struct radeon_device *rdev,
1334 struct radeon_fence *fence)
1335 {
1336 struct radeon_ring *ring = &rdev->ring[fence->ring];
1337 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1338 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1339 PACKET3_SH_ACTION_ENA;
1340
1341 /* flush read cache over gart for this vmid */
1342 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1343 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1344 radeon_ring_write(ring, 0xFFFFFFFF);
1345 radeon_ring_write(ring, 0);
1346 radeon_ring_write(ring, 10); /* poll interval */
1347 /* EVENT_WRITE_EOP - flush caches, send int */
1348 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1349 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1350 radeon_ring_write(ring, addr & 0xffffffff);
1351 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1352 radeon_ring_write(ring, fence->seq);
1353 radeon_ring_write(ring, 0);
1354 }
1355
1356 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1357 {
1358 struct radeon_ring *ring = &rdev->ring[ib->ring];
1359 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1360 PACKET3_SH_ACTION_ENA;
1361
1362 /* set to DX10/11 mode */
1363 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1364 radeon_ring_write(ring, 1);
1365
1366 if (ring->rptr_save_reg) {
1367 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1368 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1369 radeon_ring_write(ring, ((ring->rptr_save_reg -
1370 PACKET3_SET_CONFIG_REG_START) >> 2));
1371 radeon_ring_write(ring, next_rptr);
1372 }
1373
1374 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1375 radeon_ring_write(ring,
1376 #ifdef __BIG_ENDIAN
1377 (2 << 0) |
1378 #endif
1379 (ib->gpu_addr & 0xFFFFFFFC));
1380 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1381 radeon_ring_write(ring, ib->length_dw |
1382 (ib->vm ? (ib->vm->id << 24) : 0));
1383
1384 /* flush read cache over gart for this vmid */
1385 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1386 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1387 radeon_ring_write(ring, 0xFFFFFFFF);
1388 radeon_ring_write(ring, 0);
1389 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
1390 }
1391
1392 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1393 {
1394 if (enable)
1395 WREG32(CP_ME_CNTL, 0);
1396 else {
1397 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1398 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1399 WREG32(SCRATCH_UMSK, 0);
1400 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1401 }
1402 }
1403
1404 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1405 {
1406 const __be32 *fw_data;
1407 int i;
1408
1409 if (!rdev->me_fw || !rdev->pfp_fw)
1410 return -EINVAL;
1411
1412 cayman_cp_enable(rdev, false);
1413
1414 fw_data = (const __be32 *)rdev->pfp_fw->data;
1415 WREG32(CP_PFP_UCODE_ADDR, 0);
1416 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1417 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1418 WREG32(CP_PFP_UCODE_ADDR, 0);
1419
1420 fw_data = (const __be32 *)rdev->me_fw->data;
1421 WREG32(CP_ME_RAM_WADDR, 0);
1422 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1423 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1424
1425 WREG32(CP_PFP_UCODE_ADDR, 0);
1426 WREG32(CP_ME_RAM_WADDR, 0);
1427 WREG32(CP_ME_RAM_RADDR, 0);
1428 return 0;
1429 }
1430
1431 static int cayman_cp_start(struct radeon_device *rdev)
1432 {
1433 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1434 int r, i;
1435
1436 r = radeon_ring_lock(rdev, ring, 7);
1437 if (r) {
1438 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1439 return r;
1440 }
1441 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1442 radeon_ring_write(ring, 0x1);
1443 radeon_ring_write(ring, 0x0);
1444 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1445 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1446 radeon_ring_write(ring, 0);
1447 radeon_ring_write(ring, 0);
1448 radeon_ring_unlock_commit(rdev, ring);
1449
1450 cayman_cp_enable(rdev, true);
1451
1452 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1453 if (r) {
1454 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1455 return r;
1456 }
1457
1458 /* setup clear context state */
1459 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1460 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1461
1462 for (i = 0; i < cayman_default_size; i++)
1463 radeon_ring_write(ring, cayman_default_state[i]);
1464
1465 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1466 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1467
1468 /* set clear context state */
1469 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1470 radeon_ring_write(ring, 0);
1471
1472 /* SQ_VTX_BASE_VTX_LOC */
1473 radeon_ring_write(ring, 0xc0026f00);
1474 radeon_ring_write(ring, 0x00000000);
1475 radeon_ring_write(ring, 0x00000000);
1476 radeon_ring_write(ring, 0x00000000);
1477
1478 /* Clear consts */
1479 radeon_ring_write(ring, 0xc0036f00);
1480 radeon_ring_write(ring, 0x00000bc4);
1481 radeon_ring_write(ring, 0xffffffff);
1482 radeon_ring_write(ring, 0xffffffff);
1483 radeon_ring_write(ring, 0xffffffff);
1484
1485 radeon_ring_write(ring, 0xc0026900);
1486 radeon_ring_write(ring, 0x00000316);
1487 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1488 radeon_ring_write(ring, 0x00000010); /* */
1489
1490 radeon_ring_unlock_commit(rdev, ring);
1491
1492 /* XXX init other rings */
1493
1494 return 0;
1495 }
1496
1497 static void cayman_cp_fini(struct radeon_device *rdev)
1498 {
1499 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1500 cayman_cp_enable(rdev, false);
1501 radeon_ring_fini(rdev, ring);
1502 radeon_scratch_free(rdev, ring->rptr_save_reg);
1503 }
1504
1505 static int cayman_cp_resume(struct radeon_device *rdev)
1506 {
1507 static const int ridx[] = {
1508 RADEON_RING_TYPE_GFX_INDEX,
1509 CAYMAN_RING_TYPE_CP1_INDEX,
1510 CAYMAN_RING_TYPE_CP2_INDEX
1511 };
1512 static const unsigned cp_rb_cntl[] = {
1513 CP_RB0_CNTL,
1514 CP_RB1_CNTL,
1515 CP_RB2_CNTL,
1516 };
1517 static const unsigned cp_rb_rptr_addr[] = {
1518 CP_RB0_RPTR_ADDR,
1519 CP_RB1_RPTR_ADDR,
1520 CP_RB2_RPTR_ADDR
1521 };
1522 static const unsigned cp_rb_rptr_addr_hi[] = {
1523 CP_RB0_RPTR_ADDR_HI,
1524 CP_RB1_RPTR_ADDR_HI,
1525 CP_RB2_RPTR_ADDR_HI
1526 };
1527 static const unsigned cp_rb_base[] = {
1528 CP_RB0_BASE,
1529 CP_RB1_BASE,
1530 CP_RB2_BASE
1531 };
1532 struct radeon_ring *ring;
1533 int i, r;
1534
1535 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1536 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1537 SOFT_RESET_PA |
1538 SOFT_RESET_SH |
1539 SOFT_RESET_VGT |
1540 SOFT_RESET_SPI |
1541 SOFT_RESET_SX));
1542 RREG32(GRBM_SOFT_RESET);
1543 mdelay(15);
1544 WREG32(GRBM_SOFT_RESET, 0);
1545 RREG32(GRBM_SOFT_RESET);
1546
1547 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1548 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1549
1550 /* Set the write pointer delay */
1551 WREG32(CP_RB_WPTR_DELAY, 0);
1552
1553 WREG32(CP_DEBUG, (1 << 27));
1554
1555 /* set the wb address whether it's enabled or not */
1556 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1557 WREG32(SCRATCH_UMSK, 0xff);
1558
1559 for (i = 0; i < 3; ++i) {
1560 uint32_t rb_cntl;
1561 uint64_t addr;
1562
1563 /* Set ring buffer size */
1564 ring = &rdev->ring[ridx[i]];
1565 rb_cntl = order_base_2(ring->ring_size / 8);
1566 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1567 #ifdef __BIG_ENDIAN
1568 rb_cntl |= BUF_SWAP_32BIT;
1569 #endif
1570 WREG32(cp_rb_cntl[i], rb_cntl);
1571
1572 /* set the wb address whether it's enabled or not */
1573 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1574 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1575 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1576 }
1577
1578 /* set the rb base addr, this causes an internal reset of ALL rings */
1579 for (i = 0; i < 3; ++i) {
1580 ring = &rdev->ring[ridx[i]];
1581 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1582 }
1583
1584 for (i = 0; i < 3; ++i) {
1585 /* Initialize the ring buffer's read and write pointers */
1586 ring = &rdev->ring[ridx[i]];
1587 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1588
1589 ring->rptr = ring->wptr = 0;
1590 WREG32(ring->rptr_reg, ring->rptr);
1591 WREG32(ring->wptr_reg, ring->wptr);
1592
1593 mdelay(1);
1594 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1595 }
1596
1597 /* start the rings */
1598 cayman_cp_start(rdev);
1599 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1600 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1601 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1602 /* this only test cp0 */
1603 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1604 if (r) {
1605 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1606 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1607 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1608 return r;
1609 }
1610
1611 return 0;
1612 }
1613
1614 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1615 {
1616 u32 reset_mask = 0;
1617 u32 tmp;
1618
1619 /* GRBM_STATUS */
1620 tmp = RREG32(GRBM_STATUS);
1621 if (tmp & (PA_BUSY | SC_BUSY |
1622 SH_BUSY | SX_BUSY |
1623 TA_BUSY | VGT_BUSY |
1624 DB_BUSY | CB_BUSY |
1625 GDS_BUSY | SPI_BUSY |
1626 IA_BUSY | IA_BUSY_NO_DMA))
1627 reset_mask |= RADEON_RESET_GFX;
1628
1629 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1630 CP_BUSY | CP_COHERENCY_BUSY))
1631 reset_mask |= RADEON_RESET_CP;
1632
1633 if (tmp & GRBM_EE_BUSY)
1634 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1635
1636 /* DMA_STATUS_REG 0 */
1637 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1638 if (!(tmp & DMA_IDLE))
1639 reset_mask |= RADEON_RESET_DMA;
1640
1641 /* DMA_STATUS_REG 1 */
1642 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1643 if (!(tmp & DMA_IDLE))
1644 reset_mask |= RADEON_RESET_DMA1;
1645
1646 /* SRBM_STATUS2 */
1647 tmp = RREG32(SRBM_STATUS2);
1648 if (tmp & DMA_BUSY)
1649 reset_mask |= RADEON_RESET_DMA;
1650
1651 if (tmp & DMA1_BUSY)
1652 reset_mask |= RADEON_RESET_DMA1;
1653
1654 /* SRBM_STATUS */
1655 tmp = RREG32(SRBM_STATUS);
1656 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1657 reset_mask |= RADEON_RESET_RLC;
1658
1659 if (tmp & IH_BUSY)
1660 reset_mask |= RADEON_RESET_IH;
1661
1662 if (tmp & SEM_BUSY)
1663 reset_mask |= RADEON_RESET_SEM;
1664
1665 if (tmp & GRBM_RQ_PENDING)
1666 reset_mask |= RADEON_RESET_GRBM;
1667
1668 if (tmp & VMC_BUSY)
1669 reset_mask |= RADEON_RESET_VMC;
1670
1671 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1672 MCC_BUSY | MCD_BUSY))
1673 reset_mask |= RADEON_RESET_MC;
1674
1675 if (evergreen_is_display_hung(rdev))
1676 reset_mask |= RADEON_RESET_DISPLAY;
1677
1678 /* VM_L2_STATUS */
1679 tmp = RREG32(VM_L2_STATUS);
1680 if (tmp & L2_BUSY)
1681 reset_mask |= RADEON_RESET_VMC;
1682
1683 /* Skip MC reset as it's mostly likely not hung, just busy */
1684 if (reset_mask & RADEON_RESET_MC) {
1685 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1686 reset_mask &= ~RADEON_RESET_MC;
1687 }
1688
1689 return reset_mask;
1690 }
1691
1692 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1693 {
1694 struct evergreen_mc_save save;
1695 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1696 u32 tmp;
1697
1698 if (reset_mask == 0)
1699 return;
1700
1701 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1702
1703 evergreen_print_gpu_status_regs(rdev);
1704 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1705 RREG32(0x14F8));
1706 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1707 RREG32(0x14D8));
1708 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1709 RREG32(0x14FC));
1710 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1711 RREG32(0x14DC));
1712
1713 /* Disable CP parsing/prefetching */
1714 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1715
1716 if (reset_mask & RADEON_RESET_DMA) {
1717 /* dma0 */
1718 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1719 tmp &= ~DMA_RB_ENABLE;
1720 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1721 }
1722
1723 if (reset_mask & RADEON_RESET_DMA1) {
1724 /* dma1 */
1725 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1726 tmp &= ~DMA_RB_ENABLE;
1727 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1728 }
1729
1730 udelay(50);
1731
1732 evergreen_mc_stop(rdev, &save);
1733 if (evergreen_mc_wait_for_idle(rdev)) {
1734 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1735 }
1736
1737 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1738 grbm_soft_reset = SOFT_RESET_CB |
1739 SOFT_RESET_DB |
1740 SOFT_RESET_GDS |
1741 SOFT_RESET_PA |
1742 SOFT_RESET_SC |
1743 SOFT_RESET_SPI |
1744 SOFT_RESET_SH |
1745 SOFT_RESET_SX |
1746 SOFT_RESET_TC |
1747 SOFT_RESET_TA |
1748 SOFT_RESET_VGT |
1749 SOFT_RESET_IA;
1750 }
1751
1752 if (reset_mask & RADEON_RESET_CP) {
1753 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1754
1755 srbm_soft_reset |= SOFT_RESET_GRBM;
1756 }
1757
1758 if (reset_mask & RADEON_RESET_DMA)
1759 srbm_soft_reset |= SOFT_RESET_DMA;
1760
1761 if (reset_mask & RADEON_RESET_DMA1)
1762 srbm_soft_reset |= SOFT_RESET_DMA1;
1763
1764 if (reset_mask & RADEON_RESET_DISPLAY)
1765 srbm_soft_reset |= SOFT_RESET_DC;
1766
1767 if (reset_mask & RADEON_RESET_RLC)
1768 srbm_soft_reset |= SOFT_RESET_RLC;
1769
1770 if (reset_mask & RADEON_RESET_SEM)
1771 srbm_soft_reset |= SOFT_RESET_SEM;
1772
1773 if (reset_mask & RADEON_RESET_IH)
1774 srbm_soft_reset |= SOFT_RESET_IH;
1775
1776 if (reset_mask & RADEON_RESET_GRBM)
1777 srbm_soft_reset |= SOFT_RESET_GRBM;
1778
1779 if (reset_mask & RADEON_RESET_VMC)
1780 srbm_soft_reset |= SOFT_RESET_VMC;
1781
1782 if (!(rdev->flags & RADEON_IS_IGP)) {
1783 if (reset_mask & RADEON_RESET_MC)
1784 srbm_soft_reset |= SOFT_RESET_MC;
1785 }
1786
1787 if (grbm_soft_reset) {
1788 tmp = RREG32(GRBM_SOFT_RESET);
1789 tmp |= grbm_soft_reset;
1790 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1791 WREG32(GRBM_SOFT_RESET, tmp);
1792 tmp = RREG32(GRBM_SOFT_RESET);
1793
1794 udelay(50);
1795
1796 tmp &= ~grbm_soft_reset;
1797 WREG32(GRBM_SOFT_RESET, tmp);
1798 tmp = RREG32(GRBM_SOFT_RESET);
1799 }
1800
1801 if (srbm_soft_reset) {
1802 tmp = RREG32(SRBM_SOFT_RESET);
1803 tmp |= srbm_soft_reset;
1804 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1805 WREG32(SRBM_SOFT_RESET, tmp);
1806 tmp = RREG32(SRBM_SOFT_RESET);
1807
1808 udelay(50);
1809
1810 tmp &= ~srbm_soft_reset;
1811 WREG32(SRBM_SOFT_RESET, tmp);
1812 tmp = RREG32(SRBM_SOFT_RESET);
1813 }
1814
1815 /* Wait a little for things to settle down */
1816 udelay(50);
1817
1818 evergreen_mc_resume(rdev, &save);
1819 udelay(50);
1820
1821 evergreen_print_gpu_status_regs(rdev);
1822 }
1823
1824 int cayman_asic_reset(struct radeon_device *rdev)
1825 {
1826 u32 reset_mask;
1827
1828 reset_mask = cayman_gpu_check_soft_reset(rdev);
1829
1830 if (reset_mask)
1831 r600_set_bios_scratch_engine_hung(rdev, true);
1832
1833 cayman_gpu_soft_reset(rdev, reset_mask);
1834
1835 reset_mask = cayman_gpu_check_soft_reset(rdev);
1836
1837 if (!reset_mask)
1838 r600_set_bios_scratch_engine_hung(rdev, false);
1839
1840 return 0;
1841 }
1842
1843 /**
1844 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1845 *
1846 * @rdev: radeon_device pointer
1847 * @ring: radeon_ring structure holding ring information
1848 *
1849 * Check if the GFX engine is locked up.
1850 * Returns true if the engine appears to be locked up, false if not.
1851 */
1852 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1853 {
1854 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1855
1856 if (!(reset_mask & (RADEON_RESET_GFX |
1857 RADEON_RESET_COMPUTE |
1858 RADEON_RESET_CP))) {
1859 radeon_ring_lockup_update(ring);
1860 return false;
1861 }
1862 /* force CP activities */
1863 radeon_ring_force_activity(rdev, ring);
1864 return radeon_ring_test_lockup(rdev, ring);
1865 }
1866
1867 static int cayman_startup(struct radeon_device *rdev)
1868 {
1869 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1870 int r;
1871
1872 /* enable pcie gen2 link */
1873 evergreen_pcie_gen2_enable(rdev);
1874 /* enable aspm */
1875 evergreen_program_aspm(rdev);
1876
1877 /* scratch needs to be initialized before MC */
1878 r = r600_vram_scratch_init(rdev);
1879 if (r)
1880 return r;
1881
1882 evergreen_mc_program(rdev);
1883
1884 if (!(rdev->flags & RADEON_IS_IGP)) {
1885 r = ni_mc_load_microcode(rdev);
1886 if (r) {
1887 DRM_ERROR("Failed to load MC firmware!\n");
1888 return r;
1889 }
1890 }
1891
1892 r = cayman_pcie_gart_enable(rdev);
1893 if (r)
1894 return r;
1895 cayman_gpu_init(rdev);
1896
1897 /* allocate rlc buffers */
1898 if (rdev->flags & RADEON_IS_IGP) {
1899 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1900 rdev->rlc.reg_list_size =
1901 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
1902 rdev->rlc.cs_data = cayman_cs_data;
1903 r = sumo_rlc_init(rdev);
1904 if (r) {
1905 DRM_ERROR("Failed to init rlc BOs!\n");
1906 return r;
1907 }
1908 }
1909
1910 /* allocate wb buffer */
1911 r = radeon_wb_init(rdev);
1912 if (r)
1913 return r;
1914
1915 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1916 if (r) {
1917 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1918 return r;
1919 }
1920
1921 r = uvd_v2_2_resume(rdev);
1922 if (!r) {
1923 r = radeon_fence_driver_start_ring(rdev,
1924 R600_RING_TYPE_UVD_INDEX);
1925 if (r)
1926 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1927 }
1928 if (r)
1929 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1930
1931 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1932 if (r) {
1933 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1934 return r;
1935 }
1936
1937 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1938 if (r) {
1939 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1940 return r;
1941 }
1942
1943 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1944 if (r) {
1945 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1946 return r;
1947 }
1948
1949 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1950 if (r) {
1951 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1952 return r;
1953 }
1954
1955 /* Enable IRQ */
1956 if (!rdev->irq.installed) {
1957 r = radeon_irq_kms_init(rdev);
1958 if (r)
1959 return r;
1960 }
1961
1962 r = r600_irq_init(rdev);
1963 if (r) {
1964 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1965 radeon_irq_kms_fini(rdev);
1966 return r;
1967 }
1968 evergreen_irq_set(rdev);
1969
1970 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1971 CP_RB0_RPTR, CP_RB0_WPTR,
1972 RADEON_CP_PACKET2);
1973 if (r)
1974 return r;
1975
1976 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1977 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1978 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1979 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1980 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1981 if (r)
1982 return r;
1983
1984 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1985 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1986 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1987 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1988 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1989 if (r)
1990 return r;
1991
1992 r = cayman_cp_load_microcode(rdev);
1993 if (r)
1994 return r;
1995 r = cayman_cp_resume(rdev);
1996 if (r)
1997 return r;
1998
1999 r = cayman_dma_resume(rdev);
2000 if (r)
2001 return r;
2002
2003 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2004 if (ring->ring_size) {
2005 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2006 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
2007 RADEON_CP_PACKET2);
2008 if (!r)
2009 r = uvd_v1_0_init(rdev);
2010 if (r)
2011 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2012 }
2013
2014 r = radeon_ib_pool_init(rdev);
2015 if (r) {
2016 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2017 return r;
2018 }
2019
2020 r = radeon_vm_manager_init(rdev);
2021 if (r) {
2022 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2023 return r;
2024 }
2025
2026 if (ASIC_IS_DCE6(rdev)) {
2027 r = dce6_audio_init(rdev);
2028 if (r)
2029 return r;
2030 } else {
2031 r = r600_audio_init(rdev);
2032 if (r)
2033 return r;
2034 }
2035
2036 return 0;
2037 }
2038
2039 int cayman_resume(struct radeon_device *rdev)
2040 {
2041 int r;
2042
2043 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2044 * posting will perform necessary task to bring back GPU into good
2045 * shape.
2046 */
2047 /* post card */
2048 atom_asic_init(rdev->mode_info.atom_context);
2049
2050 /* init golden registers */
2051 ni_init_golden_registers(rdev);
2052
2053 rdev->accel_working = true;
2054 r = cayman_startup(rdev);
2055 if (r) {
2056 DRM_ERROR("cayman startup failed on resume\n");
2057 rdev->accel_working = false;
2058 return r;
2059 }
2060 return r;
2061 }
2062
2063 int cayman_suspend(struct radeon_device *rdev)
2064 {
2065 if (ASIC_IS_DCE6(rdev))
2066 dce6_audio_fini(rdev);
2067 else
2068 r600_audio_fini(rdev);
2069 radeon_vm_manager_fini(rdev);
2070 cayman_cp_enable(rdev, false);
2071 cayman_dma_stop(rdev);
2072 uvd_v1_0_fini(rdev);
2073 radeon_uvd_suspend(rdev);
2074 evergreen_irq_suspend(rdev);
2075 radeon_wb_disable(rdev);
2076 cayman_pcie_gart_disable(rdev);
2077 return 0;
2078 }
2079
2080 /* Plan is to move initialization in that function and use
2081 * helper function so that radeon_device_init pretty much
2082 * do nothing more than calling asic specific function. This
2083 * should also allow to remove a bunch of callback function
2084 * like vram_info.
2085 */
2086 int cayman_init(struct radeon_device *rdev)
2087 {
2088 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2089 int r;
2090
2091 /* Read BIOS */
2092 if (!radeon_get_bios(rdev)) {
2093 if (ASIC_IS_AVIVO(rdev))
2094 return -EINVAL;
2095 }
2096 /* Must be an ATOMBIOS */
2097 if (!rdev->is_atom_bios) {
2098 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2099 return -EINVAL;
2100 }
2101 r = radeon_atombios_init(rdev);
2102 if (r)
2103 return r;
2104
2105 /* Post card if necessary */
2106 if (!radeon_card_posted(rdev)) {
2107 if (!rdev->bios) {
2108 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2109 return -EINVAL;
2110 }
2111 DRM_INFO("GPU not posted. posting now...\n");
2112 atom_asic_init(rdev->mode_info.atom_context);
2113 }
2114 /* init golden registers */
2115 ni_init_golden_registers(rdev);
2116 /* Initialize scratch registers */
2117 r600_scratch_init(rdev);
2118 /* Initialize surface registers */
2119 radeon_surface_init(rdev);
2120 /* Initialize clocks */
2121 radeon_get_clock_info(rdev->ddev);
2122 /* Fence driver */
2123 r = radeon_fence_driver_init(rdev);
2124 if (r)
2125 return r;
2126 /* initialize memory controller */
2127 r = evergreen_mc_init(rdev);
2128 if (r)
2129 return r;
2130 /* Memory manager */
2131 r = radeon_bo_init(rdev);
2132 if (r)
2133 return r;
2134
2135 if (rdev->flags & RADEON_IS_IGP) {
2136 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2137 r = ni_init_microcode(rdev);
2138 if (r) {
2139 DRM_ERROR("Failed to load firmware!\n");
2140 return r;
2141 }
2142 }
2143 } else {
2144 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2145 r = ni_init_microcode(rdev);
2146 if (r) {
2147 DRM_ERROR("Failed to load firmware!\n");
2148 return r;
2149 }
2150 }
2151 }
2152
2153 ring->ring_obj = NULL;
2154 r600_ring_init(rdev, ring, 1024 * 1024);
2155
2156 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2157 ring->ring_obj = NULL;
2158 r600_ring_init(rdev, ring, 64 * 1024);
2159
2160 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2161 ring->ring_obj = NULL;
2162 r600_ring_init(rdev, ring, 64 * 1024);
2163
2164 r = radeon_uvd_init(rdev);
2165 if (!r) {
2166 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2167 ring->ring_obj = NULL;
2168 r600_ring_init(rdev, ring, 4096);
2169 }
2170
2171 rdev->ih.ring_obj = NULL;
2172 r600_ih_ring_init(rdev, 64 * 1024);
2173
2174 r = r600_pcie_gart_init(rdev);
2175 if (r)
2176 return r;
2177
2178 rdev->accel_working = true;
2179 r = cayman_startup(rdev);
2180 if (r) {
2181 dev_err(rdev->dev, "disabling GPU acceleration\n");
2182 cayman_cp_fini(rdev);
2183 cayman_dma_fini(rdev);
2184 r600_irq_fini(rdev);
2185 if (rdev->flags & RADEON_IS_IGP)
2186 sumo_rlc_fini(rdev);
2187 radeon_wb_fini(rdev);
2188 radeon_ib_pool_fini(rdev);
2189 radeon_vm_manager_fini(rdev);
2190 radeon_irq_kms_fini(rdev);
2191 cayman_pcie_gart_fini(rdev);
2192 rdev->accel_working = false;
2193 }
2194
2195 /* Don't start up if the MC ucode is missing.
2196 * The default clocks and voltages before the MC ucode
2197 * is loaded are not suffient for advanced operations.
2198 *
2199 * We can skip this check for TN, because there is no MC
2200 * ucode.
2201 */
2202 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2203 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2204 return -EINVAL;
2205 }
2206
2207 return 0;
2208 }
2209
2210 void cayman_fini(struct radeon_device *rdev)
2211 {
2212 cayman_cp_fini(rdev);
2213 cayman_dma_fini(rdev);
2214 r600_irq_fini(rdev);
2215 if (rdev->flags & RADEON_IS_IGP)
2216 sumo_rlc_fini(rdev);
2217 radeon_wb_fini(rdev);
2218 radeon_vm_manager_fini(rdev);
2219 radeon_ib_pool_fini(rdev);
2220 radeon_irq_kms_fini(rdev);
2221 uvd_v1_0_fini(rdev);
2222 radeon_uvd_fini(rdev);
2223 cayman_pcie_gart_fini(rdev);
2224 r600_vram_scratch_fini(rdev);
2225 radeon_gem_fini(rdev);
2226 radeon_fence_driver_fini(rdev);
2227 radeon_bo_fini(rdev);
2228 radeon_atombios_fini(rdev);
2229 kfree(rdev->bios);
2230 rdev->bios = NULL;
2231 }
2232
2233 /*
2234 * vm
2235 */
2236 int cayman_vm_init(struct radeon_device *rdev)
2237 {
2238 /* number of VMs */
2239 rdev->vm_manager.nvm = 8;
2240 /* base offset of vram pages */
2241 if (rdev->flags & RADEON_IS_IGP) {
2242 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2243 tmp <<= 22;
2244 rdev->vm_manager.vram_base_offset = tmp;
2245 } else
2246 rdev->vm_manager.vram_base_offset = 0;
2247 return 0;
2248 }
2249
2250 void cayman_vm_fini(struct radeon_device *rdev)
2251 {
2252 }
2253
2254 /**
2255 * cayman_vm_decode_fault - print human readable fault info
2256 *
2257 * @rdev: radeon_device pointer
2258 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2259 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2260 *
2261 * Print human readable fault information (cayman/TN).
2262 */
2263 void cayman_vm_decode_fault(struct radeon_device *rdev,
2264 u32 status, u32 addr)
2265 {
2266 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2267 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2268 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2269 char *block;
2270
2271 switch (mc_id) {
2272 case 32:
2273 case 16:
2274 case 96:
2275 case 80:
2276 case 160:
2277 case 144:
2278 case 224:
2279 case 208:
2280 block = "CB";
2281 break;
2282 case 33:
2283 case 17:
2284 case 97:
2285 case 81:
2286 case 161:
2287 case 145:
2288 case 225:
2289 case 209:
2290 block = "CB_FMASK";
2291 break;
2292 case 34:
2293 case 18:
2294 case 98:
2295 case 82:
2296 case 162:
2297 case 146:
2298 case 226:
2299 case 210:
2300 block = "CB_CMASK";
2301 break;
2302 case 35:
2303 case 19:
2304 case 99:
2305 case 83:
2306 case 163:
2307 case 147:
2308 case 227:
2309 case 211:
2310 block = "CB_IMMED";
2311 break;
2312 case 36:
2313 case 20:
2314 case 100:
2315 case 84:
2316 case 164:
2317 case 148:
2318 case 228:
2319 case 212:
2320 block = "DB";
2321 break;
2322 case 37:
2323 case 21:
2324 case 101:
2325 case 85:
2326 case 165:
2327 case 149:
2328 case 229:
2329 case 213:
2330 block = "DB_HTILE";
2331 break;
2332 case 38:
2333 case 22:
2334 case 102:
2335 case 86:
2336 case 166:
2337 case 150:
2338 case 230:
2339 case 214:
2340 block = "SX";
2341 break;
2342 case 39:
2343 case 23:
2344 case 103:
2345 case 87:
2346 case 167:
2347 case 151:
2348 case 231:
2349 case 215:
2350 block = "DB_STEN";
2351 break;
2352 case 40:
2353 case 24:
2354 case 104:
2355 case 88:
2356 case 232:
2357 case 216:
2358 case 168:
2359 case 152:
2360 block = "TC_TFETCH";
2361 break;
2362 case 41:
2363 case 25:
2364 case 105:
2365 case 89:
2366 case 233:
2367 case 217:
2368 case 169:
2369 case 153:
2370 block = "TC_VFETCH";
2371 break;
2372 case 42:
2373 case 26:
2374 case 106:
2375 case 90:
2376 case 234:
2377 case 218:
2378 case 170:
2379 case 154:
2380 block = "VC";
2381 break;
2382 case 112:
2383 block = "CP";
2384 break;
2385 case 113:
2386 case 114:
2387 block = "SH";
2388 break;
2389 case 115:
2390 block = "VGT";
2391 break;
2392 case 178:
2393 block = "IH";
2394 break;
2395 case 51:
2396 block = "RLC";
2397 break;
2398 case 55:
2399 block = "DMA";
2400 break;
2401 case 56:
2402 block = "HDP";
2403 break;
2404 default:
2405 block = "unknown";
2406 break;
2407 }
2408
2409 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2410 protections, vmid, addr,
2411 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2412 block, mc_id);
2413 }
2414
2415 #define R600_ENTRY_VALID (1 << 0)
2416 #define R600_PTE_SYSTEM (1 << 1)
2417 #define R600_PTE_SNOOPED (1 << 2)
2418 #define R600_PTE_READABLE (1 << 5)
2419 #define R600_PTE_WRITEABLE (1 << 6)
2420
2421 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
2422 {
2423 uint32_t r600_flags = 0;
2424 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
2425 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
2426 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
2427 if (flags & RADEON_VM_PAGE_SYSTEM) {
2428 r600_flags |= R600_PTE_SYSTEM;
2429 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
2430 }
2431 return r600_flags;
2432 }
2433
2434 /**
2435 * cayman_vm_set_page - update the page tables using the CP
2436 *
2437 * @rdev: radeon_device pointer
2438 * @ib: indirect buffer to fill with commands
2439 * @pe: addr of the page entry
2440 * @addr: dst addr to write into pe
2441 * @count: number of page entries to update
2442 * @incr: increase next addr by incr bytes
2443 * @flags: access flags
2444 *
2445 * Update the page tables using the CP (cayman/TN).
2446 */
2447 void cayman_vm_set_page(struct radeon_device *rdev,
2448 struct radeon_ib *ib,
2449 uint64_t pe,
2450 uint64_t addr, unsigned count,
2451 uint32_t incr, uint32_t flags)
2452 {
2453 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2454 uint64_t value;
2455 unsigned ndw;
2456
2457 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2458 while (count) {
2459 ndw = 1 + count * 2;
2460 if (ndw > 0x3FFF)
2461 ndw = 0x3FFF;
2462
2463 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
2464 ib->ptr[ib->length_dw++] = pe;
2465 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2466 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
2467 if (flags & RADEON_VM_PAGE_SYSTEM) {
2468 value = radeon_vm_map_gart(rdev, addr);
2469 value &= 0xFFFFFFFFFFFFF000ULL;
2470 } else if (flags & RADEON_VM_PAGE_VALID) {
2471 value = addr;
2472 } else {
2473 value = 0;
2474 }
2475 addr += incr;
2476 value |= r600_flags;
2477 ib->ptr[ib->length_dw++] = value;
2478 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2479 }
2480 }
2481 } else {
2482 cayman_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
2483 }
2484 }
2485
2486 /**
2487 * cayman_vm_flush - vm flush using the CP
2488 *
2489 * @rdev: radeon_device pointer
2490 *
2491 * Update the page table base and flush the VM TLB
2492 * using the CP (cayman-si).
2493 */
2494 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2495 {
2496 struct radeon_ring *ring = &rdev->ring[ridx];
2497
2498 if (vm == NULL)
2499 return;
2500
2501 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2502 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2503
2504 /* flush hdp cache */
2505 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2506 radeon_ring_write(ring, 0x1);
2507
2508 /* bits 0-7 are the VM contexts0-7 */
2509 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2510 radeon_ring_write(ring, 1 << vm->id);
2511
2512 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2513 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2514 radeon_ring_write(ring, 0x0);
2515 }
Linux with added FPC-III support