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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r600_hdmi.c
blobd38b725563e44827bc9cb57d6cff3dbd7c1cd362
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26 #include <linux/hdmi.h>
27 #include <linux/gcd.h>
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "r600d.h"
33 #include "atom.h"
34
35 /*
36 * HDMI color format
37 */
38 enum r600_hdmi_color_format {
39 RGB = 0,
40 YCC_422 = 1,
41 YCC_444 = 2
42 };
43
44 /*
45 * IEC60958 status bits
46 */
47 enum r600_hdmi_iec_status_bits {
48 AUDIO_STATUS_DIG_ENABLE = 0x01,
49 AUDIO_STATUS_V = 0x02,
50 AUDIO_STATUS_VCFG = 0x04,
51 AUDIO_STATUS_EMPHASIS = 0x08,
52 AUDIO_STATUS_COPYRIGHT = 0x10,
53 AUDIO_STATUS_NONAUDIO = 0x20,
54 AUDIO_STATUS_PROFESSIONAL = 0x40,
55 AUDIO_STATUS_LEVEL = 0x80
56 };
57
58 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
59 /* 32kHz 44.1kHz 48kHz */
60 /* Clock N CTS N CTS N CTS */
61 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
62 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
63 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
64 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
65 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
66 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
67 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
68 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
69 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
70 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
71 };
72
73
74 /*
75 * calculate CTS and N values if they are not found in the table
76 */
77 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
78 {
79 int n, cts;
80 unsigned long div, mul;
81
82 /* Safe, but overly large values */
83 n = 128 * freq;
84 cts = clock * 1000;
85
86 /* Smallest valid fraction */
87 div = gcd(n, cts);
88
89 n /= div;
90 cts /= div;
91
92 /*
93 * The optimal N is 128*freq/1000. Calculate the closest larger
94 * value that doesn't truncate any bits.
95 */
96 mul = ((128*freq/1000) + (n-1))/n;
97
98 n *= mul;
99 cts *= mul;
100
101 /* Check that we are in spec (not always possible) */
102 if (n < (128*freq/1500))
103 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
104 if (n > (128*freq/300))
105 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
106
107 *N = n;
108 *CTS = cts;
109
110 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
111 *N, *CTS, freq);
112 }
113
114 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
115 {
116 struct radeon_hdmi_acr res;
117 u8 i;
118
119 /* Precalculated values for common clocks */
120 for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
121 if (r600_hdmi_predefined_acr[i].clock == clock)
122 return r600_hdmi_predefined_acr[i];
123 }
124
125 /* And odd clocks get manually calculated */
126 r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
127 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
128 r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
129
130 return res;
131 }
132
133 /*
134 * update the N and CTS parameters for a given pixel clock rate
135 */
136 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
137 {
138 struct drm_device *dev = encoder->dev;
139 struct radeon_device *rdev = dev->dev_private;
140 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
141 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
142 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
143 uint32_t offset = dig->afmt->offset;
144
145 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
146 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
147
148 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
149 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
150
151 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
152 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
153 }
154
155 /*
156 * build a HDMI Video Info Frame
157 */
158 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
159 void *buffer, size_t size)
160 {
161 struct drm_device *dev = encoder->dev;
162 struct radeon_device *rdev = dev->dev_private;
163 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
164 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
165 uint32_t offset = dig->afmt->offset;
166 uint8_t *frame = buffer + 3;
167 uint8_t *header = buffer;
168
169 WREG32(HDMI0_AVI_INFO0 + offset,
170 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
171 WREG32(HDMI0_AVI_INFO1 + offset,
172 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
173 WREG32(HDMI0_AVI_INFO2 + offset,
174 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
175 WREG32(HDMI0_AVI_INFO3 + offset,
176 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
177 }
178
179 /*
180 * build a Audio Info Frame
181 */
182 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
183 const void *buffer, size_t size)
184 {
185 struct drm_device *dev = encoder->dev;
186 struct radeon_device *rdev = dev->dev_private;
187 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
188 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
189 uint32_t offset = dig->afmt->offset;
190 const u8 *frame = buffer + 3;
191
192 WREG32(HDMI0_AUDIO_INFO0 + offset,
193 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
194 WREG32(HDMI0_AUDIO_INFO1 + offset,
195 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
196 }
197
198 /*
199 * test if audio buffer is filled enough to start playing
200 */
201 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
202 {
203 struct drm_device *dev = encoder->dev;
204 struct radeon_device *rdev = dev->dev_private;
205 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
206 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
207 uint32_t offset = dig->afmt->offset;
208
209 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
210 }
211
212 /*
213 * have buffer status changed since last call?
214 */
215 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
216 {
217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
218 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
219 int status, result;
220
221 if (!dig->afmt || !dig->afmt->enabled)
222 return 0;
223
224 status = r600_hdmi_is_audio_buffer_filled(encoder);
225 result = dig->afmt->last_buffer_filled_status != status;
226 dig->afmt->last_buffer_filled_status = status;
227
228 return result;
229 }
230
231 /*
232 * write the audio workaround status to the hardware
233 */
234 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
235 {
236 struct drm_device *dev = encoder->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
239 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
240 uint32_t offset = dig->afmt->offset;
241 bool hdmi_audio_workaround = false; /* FIXME */
242 u32 value;
243
244 if (!hdmi_audio_workaround ||
245 r600_hdmi_is_audio_buffer_filled(encoder))
246 value = 0; /* disable workaround */
247 else
248 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
249 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
250 value, ~HDMI0_AUDIO_TEST_EN);
251 }
252
253 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
254 {
255 struct drm_device *dev = encoder->dev;
256 struct radeon_device *rdev = dev->dev_private;
257 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
258 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
259 u32 base_rate = 24000;
260 u32 max_ratio = clock / base_rate;
261 u32 dto_phase;
262 u32 dto_modulo = clock;
263 u32 wallclock_ratio;
264 u32 dto_cntl;
265
266 if (!dig || !dig->afmt)
267 return;
268
269 if (max_ratio >= 8) {
270 dto_phase = 192 * 1000;
271 wallclock_ratio = 3;
272 } else if (max_ratio >= 4) {
273 dto_phase = 96 * 1000;
274 wallclock_ratio = 2;
275 } else if (max_ratio >= 2) {
276 dto_phase = 48 * 1000;
277 wallclock_ratio = 1;
278 } else {
279 dto_phase = 24 * 1000;
280 wallclock_ratio = 0;
281 }
282
283 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
284 * doesn't matter which one you use. Just use the first one.
285 */
286 /* XXX two dtos; generally use dto0 for hdmi */
287 /* Express [24MHz / target pixel clock] as an exact rational
288 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
289 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
290 */
291 if (ASIC_IS_DCE32(rdev)) {
292 if (dig->dig_encoder == 0) {
293 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
294 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
295 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
296 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
297 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
298 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
299 } else {
300 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
301 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
302 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
303 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
304 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
305 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
306 }
307 } else {
308 /* according to the reg specs, this should DCE3.2 only, but in
309 * practice it seems to cover DCE2.0/3.0/3.1 as well.
310 */
311 if (dig->dig_encoder == 0) {
312 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
313 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
314 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
315 } else {
316 WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
317 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
318 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
319 }
320 }
321 }
322
323 static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
324 {
325 struct radeon_device *rdev = encoder->dev->dev_private;
326 struct drm_connector *connector;
327 struct radeon_connector *radeon_connector = NULL;
328 u32 tmp;
329 u8 *sadb;
330 int sad_count;
331
332 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
333 if (connector->encoder == encoder)
334 radeon_connector = to_radeon_connector(connector);
335 }
336
337 if (!radeon_connector) {
338 DRM_ERROR("Couldn't find encoder's connector\n");
339 return;
340 }
341
342 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
343 if (sad_count < 0) {
344 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
345 return;
346 }
347
348 /* program the speaker allocation */
349 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
350 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
351 /* set HDMI mode */
352 tmp |= HDMI_CONNECTION;
353 if (sad_count)
354 tmp |= SPEAKER_ALLOCATION(sadb[0]);
355 else
356 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
357 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
358
359 kfree(sadb);
360 }
361
362 static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder)
363 {
364 struct radeon_device *rdev = encoder->dev->dev_private;
365 struct drm_connector *connector;
366 struct radeon_connector *radeon_connector = NULL;
367 struct cea_sad *sads;
368 int i, sad_count;
369
370 static const u16 eld_reg_to_type[][2] = {
371 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
372 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
373 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
374 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
375 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
376 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
377 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
378 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
379 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
380 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
381 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
382 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
383 };
384
385 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
386 if (connector->encoder == encoder)
387 radeon_connector = to_radeon_connector(connector);
388 }
389
390 if (!radeon_connector) {
391 DRM_ERROR("Couldn't find encoder's connector\n");
392 return;
393 }
394
395 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
396 if (sad_count < 0) {
397 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
398 return;
399 }
400 BUG_ON(!sads);
401
402 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
403 u32 value = 0;
404 int j;
405
406 for (j = 0; j < sad_count; j++) {
407 struct cea_sad *sad = &sads[j];
408
409 if (sad->format == eld_reg_to_type[i][1]) {
410 value = MAX_CHANNELS(sad->channels) |
411 DESCRIPTOR_BYTE_2(sad->byte2) |
412 SUPPORTED_FREQUENCIES(sad->freq);
413 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
414 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
415 break;
416 }
417 }
418 WREG32(eld_reg_to_type[i][0], value);
419 }
420
421 kfree(sads);
422 }
423
424 /*
425 * update the info frames with the data from the current display mode
426 */
427 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
428 {
429 struct drm_device *dev = encoder->dev;
430 struct radeon_device *rdev = dev->dev_private;
431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
432 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
433 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
434 struct hdmi_avi_infoframe frame;
435 uint32_t offset;
436 ssize_t err;
437
438 if (!dig || !dig->afmt)
439 return;
440
441 /* Silent, r600_hdmi_enable will raise WARN for us */
442 if (!dig->afmt->enabled)
443 return;
444 offset = dig->afmt->offset;
445
446 /* disable audio prior to setting up hw */
447 dig->afmt->pin = r600_audio_get_pin(rdev);
448 r600_audio_enable(rdev, dig->afmt->pin, false);
449
450 r600_audio_set_dto(encoder, mode->clock);
451
452 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
453 HDMI0_NULL_SEND); /* send null packets when required */
454
455 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
456
457 if (ASIC_IS_DCE32(rdev)) {
458 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
459 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
460 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
461 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
462 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
463 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
464 } else {
465 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
466 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
467 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
468 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
469 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
470 }
471
472 if (ASIC_IS_DCE32(rdev)) {
473 dce3_2_afmt_write_speaker_allocation(encoder);
474 dce3_2_afmt_write_sad_regs(encoder);
475 }
476
477 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
478 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
479 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
480
481 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
482 HDMI0_NULL_SEND | /* send null packets when required */
483 HDMI0_GC_SEND | /* send general control packets */
484 HDMI0_GC_CONT); /* send general control packets every frame */
485
486 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
487 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
488 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
489 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
490 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
491 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
492
493 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
494 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
495 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
496
497 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
498
499 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
500 if (err < 0) {
501 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
502 return;
503 }
504
505 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
506 if (err < 0) {
507 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
508 return;
509 }
510
511 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
512 r600_hdmi_update_ACR(encoder, mode->clock);
513
514 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
515 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
516 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
517 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
518 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
519
520 r600_hdmi_audio_workaround(encoder);
521
522 /* enable audio after to setting up hw */
523 r600_audio_enable(rdev, dig->afmt->pin, true);
524 }
525
526 /*
527 * update settings with current parameters from audio engine
528 */
529 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
530 {
531 struct drm_device *dev = encoder->dev;
532 struct radeon_device *rdev = dev->dev_private;
533 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
534 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
535 struct r600_audio_pin audio = r600_audio_status(rdev);
536 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
537 struct hdmi_audio_infoframe frame;
538 uint32_t offset;
539 uint32_t iec;
540 ssize_t err;
541
542 if (!dig->afmt || !dig->afmt->enabled)
543 return;
544 offset = dig->afmt->offset;
545
546 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
547 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
548 audio.channels, audio.rate, audio.bits_per_sample);
549 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
550 (int)audio.status_bits, (int)audio.category_code);
551
552 iec = 0;
553 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
554 iec |= 1 << 0;
555 if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
556 iec |= 1 << 1;
557 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
558 iec |= 1 << 2;
559 if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
560 iec |= 1 << 3;
561
562 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
563
564 switch (audio.rate) {
565 case 32000:
566 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
567 break;
568 case 44100:
569 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
570 break;
571 case 48000:
572 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
573 break;
574 case 88200:
575 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
576 break;
577 case 96000:
578 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
579 break;
580 case 176400:
581 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
582 break;
583 case 192000:
584 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
585 break;
586 }
587
588 WREG32(HDMI0_60958_0 + offset, iec);
589
590 iec = 0;
591 switch (audio.bits_per_sample) {
592 case 16:
593 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
594 break;
595 case 20:
596 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
597 break;
598 case 24:
599 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
600 break;
601 }
602 if (audio.status_bits & AUDIO_STATUS_V)
603 iec |= 0x5 << 16;
604 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
605
606 err = hdmi_audio_infoframe_init(&frame);
607 if (err < 0) {
608 DRM_ERROR("failed to setup audio infoframe\n");
609 return;
610 }
611
612 frame.channels = audio.channels;
613
614 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
615 if (err < 0) {
616 DRM_ERROR("failed to pack audio infoframe\n");
617 return;
618 }
619
620 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
621 r600_hdmi_audio_workaround(encoder);
622 }
623
624 /*
625 * enable the HDMI engine
626 */
627 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
628 {
629 struct drm_device *dev = encoder->dev;
630 struct radeon_device *rdev = dev->dev_private;
631 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
633 u32 hdmi = HDMI0_ERROR_ACK;
634
635 if (!dig || !dig->afmt)
636 return;
637
638 /* Silent, r600_hdmi_enable will raise WARN for us */
639 if (enable && dig->afmt->enabled)
640 return;
641 if (!enable && !dig->afmt->enabled)
642 return;
643
644 /* Older chipsets require setting HDMI and routing manually */
645 if (!ASIC_IS_DCE3(rdev)) {
646 if (enable)
647 hdmi |= HDMI0_ENABLE;
648 switch (radeon_encoder->encoder_id) {
649 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
650 if (enable) {
651 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
652 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
653 } else {
654 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
655 }
656 break;
657 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
658 if (enable) {
659 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
660 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
661 } else {
662 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
663 }
664 break;
665 case ENCODER_OBJECT_ID_INTERNAL_DDI:
666 if (enable) {
667 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
668 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
669 } else {
670 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
671 }
672 break;
673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
674 if (enable)
675 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
676 break;
677 default:
678 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
679 radeon_encoder->encoder_id);
680 break;
681 }
682 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
683 }
684
685 if (rdev->irq.installed) {
686 /* if irq is available use it */
687 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
688 if (enable)
689 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
690 else
691 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
692 }
693
694 dig->afmt->enabled = enable;
695
696 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
697 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
698 }
699
Linux with added FPC-III support