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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon.h
blob5c903a884bb809aa59806b5d198a58a29ba3fe1f
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101
102 /*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
106 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108 /* RADEON_IB_POOL_SIZE must be a power of 2 */
109 #define RADEON_IB_POOL_SIZE 16
110 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
111 #define RADEONFB_CONN_LIMIT 4
112 #define RADEON_BIOS_NUM_SCRATCH 8
113
114 /* max number of rings */
115 #define RADEON_NUM_RINGS 6
116
117 /* fence seq are set to this number when signaled */
118 #define RADEON_FENCE_SIGNALED_SEQ 0LL
119
120 /* internal ring indices */
121 /* r1xx+ has gfx CP ring */
122 #define RADEON_RING_TYPE_GFX_INDEX 0
123
124 /* cayman has 2 compute CP rings */
125 #define CAYMAN_RING_TYPE_CP1_INDEX 1
126 #define CAYMAN_RING_TYPE_CP2_INDEX 2
127
128 /* R600+ has an async dma ring */
129 #define R600_RING_TYPE_DMA_INDEX 3
130 /* cayman add a second async dma ring */
131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
132
133 /* R600+ */
134 #define R600_RING_TYPE_UVD_INDEX 5
135
136 /* hardcode those limit for now */
137 #define RADEON_VA_IB_OFFSET (1 << 20)
138 #define RADEON_VA_RESERVED_SIZE (8 << 20)
139 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
140
141 /* reset flags */
142 #define RADEON_RESET_GFX (1 << 0)
143 #define RADEON_RESET_COMPUTE (1 << 1)
144 #define RADEON_RESET_DMA (1 << 2)
145 #define RADEON_RESET_CP (1 << 3)
146 #define RADEON_RESET_GRBM (1 << 4)
147 #define RADEON_RESET_DMA1 (1 << 5)
148 #define RADEON_RESET_RLC (1 << 6)
149 #define RADEON_RESET_SEM (1 << 7)
150 #define RADEON_RESET_IH (1 << 8)
151 #define RADEON_RESET_VMC (1 << 9)
152 #define RADEON_RESET_MC (1 << 10)
153 #define RADEON_RESET_DISPLAY (1 << 11)
154
155 /* CG block flags */
156 #define RADEON_CG_BLOCK_GFX (1 << 0)
157 #define RADEON_CG_BLOCK_MC (1 << 1)
158 #define RADEON_CG_BLOCK_SDMA (1 << 2)
159 #define RADEON_CG_BLOCK_UVD (1 << 3)
160 #define RADEON_CG_BLOCK_VCE (1 << 4)
161 #define RADEON_CG_BLOCK_HDP (1 << 5)
162 #define RADEON_CG_BLOCK_BIF (1 << 6)
163
164 /* CG flags */
165 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
166 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
167 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
168 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
169 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
170 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
171 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
172 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
173 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
174 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
175 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
176 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
177 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
178 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
179 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
180 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
181 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
182
183 /* PG flags */
184 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
185 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
186 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
187 #define RADEON_PG_SUPPORT_UVD (1 << 3)
188 #define RADEON_PG_SUPPORT_VCE (1 << 4)
189 #define RADEON_PG_SUPPORT_CP (1 << 5)
190 #define RADEON_PG_SUPPORT_GDS (1 << 6)
191 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
192 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
193 #define RADEON_PG_SUPPORT_ACP (1 << 9)
194 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
195
196 /* max cursor sizes (in pixels) */
197 #define CURSOR_WIDTH 64
198 #define CURSOR_HEIGHT 64
199
200 #define CIK_CURSOR_WIDTH 128
201 #define CIK_CURSOR_HEIGHT 128
202
203 /*
204 * Errata workarounds.
205 */
206 enum radeon_pll_errata {
207 CHIP_ERRATA_R300_CG = 0x00000001,
208 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
209 CHIP_ERRATA_PLL_DELAY = 0x00000004
210 };
211
212
213 struct radeon_device;
214
215
216 /*
217 * BIOS.
218 */
219 bool radeon_get_bios(struct radeon_device *rdev);
220
221 /*
222 * Dummy page
223 */
224 struct radeon_dummy_page {
225 struct page *page;
226 dma_addr_t addr;
227 };
228 int radeon_dummy_page_init(struct radeon_device *rdev);
229 void radeon_dummy_page_fini(struct radeon_device *rdev);
230
231
232 /*
233 * Clocks
234 */
235 struct radeon_clock {
236 struct radeon_pll p1pll;
237 struct radeon_pll p2pll;
238 struct radeon_pll dcpll;
239 struct radeon_pll spll;
240 struct radeon_pll mpll;
241 /* 10 Khz units */
242 uint32_t default_mclk;
243 uint32_t default_sclk;
244 uint32_t default_dispclk;
245 uint32_t current_dispclk;
246 uint32_t dp_extclk;
247 uint32_t max_pixel_clock;
248 };
249
250 /*
251 * Power management
252 */
253 int radeon_pm_init(struct radeon_device *rdev);
254 void radeon_pm_fini(struct radeon_device *rdev);
255 void radeon_pm_compute_clocks(struct radeon_device *rdev);
256 void radeon_pm_suspend(struct radeon_device *rdev);
257 void radeon_pm_resume(struct radeon_device *rdev);
258 void radeon_combios_get_power_modes(struct radeon_device *rdev);
259 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
260 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
261 u8 clock_type,
262 u32 clock,
263 bool strobe_mode,
264 struct atom_clock_dividers *dividers);
265 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
266 u32 clock,
267 bool strobe_mode,
268 struct atom_mpll_param *mpll_param);
269 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
270 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
271 u16 voltage_level, u8 voltage_type,
272 u32 *gpio_value, u32 *gpio_mask);
273 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
274 u32 eng_clock, u32 mem_clock);
275 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
276 u8 voltage_type, u16 *voltage_step);
277 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
278 u16 voltage_id, u16 *voltage);
279 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
280 u16 *voltage,
281 u16 leakage_idx);
282 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
283 u16 *leakage_id);
284 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
285 u16 *vddc, u16 *vddci,
286 u16 virtual_voltage_id,
287 u16 vbios_voltage_id);
288 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
289 u8 voltage_type,
290 u16 nominal_voltage,
291 u16 *true_voltage);
292 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
293 u8 voltage_type, u16 *min_voltage);
294 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
295 u8 voltage_type, u16 *max_voltage);
296 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
297 u8 voltage_type, u8 voltage_mode,
298 struct atom_voltage_table *voltage_table);
299 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
300 u8 voltage_type, u8 voltage_mode);
301 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
302 u32 mem_clock);
303 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
304 u32 mem_clock);
305 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
306 u8 module_index,
307 struct atom_mc_reg_table *reg_table);
308 int radeon_atom_get_memory_info(struct radeon_device *rdev,
309 u8 module_index, struct atom_memory_info *mem_info);
310 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
311 bool gddr5, u8 module_index,
312 struct atom_memory_clock_range_table *mclk_range_table);
313 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
314 u16 voltage_id, u16 *voltage);
315 void rs690_pm_info(struct radeon_device *rdev);
316 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
317 unsigned *bankh, unsigned *mtaspect,
318 unsigned *tile_split);
319
320 /*
321 * Fences.
322 */
323 struct radeon_fence_driver {
324 uint32_t scratch_reg;
325 uint64_t gpu_addr;
326 volatile uint32_t *cpu_addr;
327 /* sync_seq is protected by ring emission lock */
328 uint64_t sync_seq[RADEON_NUM_RINGS];
329 atomic64_t last_seq;
330 unsigned long last_activity;
331 bool initialized;
332 };
333
334 struct radeon_fence {
335 struct radeon_device *rdev;
336 struct kref kref;
337 /* protected by radeon_fence.lock */
338 uint64_t seq;
339 /* RB, DMA, etc. */
340 unsigned ring;
341 };
342
343 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344 int radeon_fence_driver_init(struct radeon_device *rdev);
345 void radeon_fence_driver_fini(struct radeon_device *rdev);
346 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
347 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
348 void radeon_fence_process(struct radeon_device *rdev, int ring);
349 bool radeon_fence_signaled(struct radeon_fence *fence);
350 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
351 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
352 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
353 int radeon_fence_wait_any(struct radeon_device *rdev,
354 struct radeon_fence **fences,
355 bool intr);
356 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
357 void radeon_fence_unref(struct radeon_fence **fence);
358 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
359 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
360 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
361 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
362 struct radeon_fence *b)
363 {
364 if (!a) {
365 return b;
366 }
367
368 if (!b) {
369 return a;
370 }
371
372 BUG_ON(a->ring != b->ring);
373
374 if (a->seq > b->seq) {
375 return a;
376 } else {
377 return b;
378 }
379 }
380
381 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
382 struct radeon_fence *b)
383 {
384 if (!a) {
385 return false;
386 }
387
388 if (!b) {
389 return true;
390 }
391
392 BUG_ON(a->ring != b->ring);
393
394 return a->seq < b->seq;
395 }
396
397 /*
398 * Tiling registers
399 */
400 struct radeon_surface_reg {
401 struct radeon_bo *bo;
402 };
403
404 #define RADEON_GEM_MAX_SURFACES 8
405
406 /*
407 * TTM.
408 */
409 struct radeon_mman {
410 struct ttm_bo_global_ref bo_global_ref;
411 struct drm_global_reference mem_global_ref;
412 struct ttm_bo_device bdev;
413 bool mem_global_referenced;
414 bool initialized;
415 };
416
417 /* bo virtual address in a specific vm */
418 struct radeon_bo_va {
419 /* protected by bo being reserved */
420 struct list_head bo_list;
421 uint64_t soffset;
422 uint64_t eoffset;
423 uint32_t flags;
424 bool valid;
425 unsigned ref_count;
426
427 /* protected by vm mutex */
428 struct list_head vm_list;
429
430 /* constant after initialization */
431 struct radeon_vm *vm;
432 struct radeon_bo *bo;
433 };
434
435 struct radeon_bo {
436 /* Protected by gem.mutex */
437 struct list_head list;
438 /* Protected by tbo.reserved */
439 u32 placements[3];
440 struct ttm_placement placement;
441 struct ttm_buffer_object tbo;
442 struct ttm_bo_kmap_obj kmap;
443 unsigned pin_count;
444 void *kptr;
445 u32 tiling_flags;
446 u32 pitch;
447 int surface_reg;
448 /* list of all virtual address to which this bo
449 * is associated to
450 */
451 struct list_head va;
452 /* Constant after initialization */
453 struct radeon_device *rdev;
454 struct drm_gem_object gem_base;
455
456 struct ttm_bo_kmap_obj dma_buf_vmap;
457 pid_t pid;
458 };
459 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
460
461 struct radeon_bo_list {
462 struct ttm_validate_buffer tv;
463 struct radeon_bo *bo;
464 uint64_t gpu_offset;
465 bool written;
466 unsigned domain;
467 unsigned alt_domain;
468 u32 tiling_flags;
469 };
470
471 int radeon_gem_debugfs_init(struct radeon_device *rdev);
472
473 /* sub-allocation manager, it has to be protected by another lock.
474 * By conception this is an helper for other part of the driver
475 * like the indirect buffer or semaphore, which both have their
476 * locking.
477 *
478 * Principe is simple, we keep a list of sub allocation in offset
479 * order (first entry has offset == 0, last entry has the highest
480 * offset).
481 *
482 * When allocating new object we first check if there is room at
483 * the end total_size - (last_object_offset + last_object_size) >=
484 * alloc_size. If so we allocate new object there.
485 *
486 * When there is not enough room at the end, we start waiting for
487 * each sub object until we reach object_offset+object_size >=
488 * alloc_size, this object then become the sub object we return.
489 *
490 * Alignment can't be bigger than page size.
491 *
492 * Hole are not considered for allocation to keep things simple.
493 * Assumption is that there won't be hole (all object on same
494 * alignment).
495 */
496 struct radeon_sa_manager {
497 wait_queue_head_t wq;
498 struct radeon_bo *bo;
499 struct list_head *hole;
500 struct list_head flist[RADEON_NUM_RINGS];
501 struct list_head olist;
502 unsigned size;
503 uint64_t gpu_addr;
504 void *cpu_ptr;
505 uint32_t domain;
506 uint32_t align;
507 };
508
509 struct radeon_sa_bo;
510
511 /* sub-allocation buffer */
512 struct radeon_sa_bo {
513 struct list_head olist;
514 struct list_head flist;
515 struct radeon_sa_manager *manager;
516 unsigned soffset;
517 unsigned eoffset;
518 struct radeon_fence *fence;
519 };
520
521 /*
522 * GEM objects.
523 */
524 struct radeon_gem {
525 struct mutex mutex;
526 struct list_head objects;
527 };
528
529 int radeon_gem_init(struct radeon_device *rdev);
530 void radeon_gem_fini(struct radeon_device *rdev);
531 int radeon_gem_object_create(struct radeon_device *rdev, int size,
532 int alignment, int initial_domain,
533 bool discardable, bool kernel,
534 struct drm_gem_object **obj);
535
536 int radeon_mode_dumb_create(struct drm_file *file_priv,
537 struct drm_device *dev,
538 struct drm_mode_create_dumb *args);
539 int radeon_mode_dumb_mmap(struct drm_file *filp,
540 struct drm_device *dev,
541 uint32_t handle, uint64_t *offset_p);
542
543 /*
544 * Semaphores.
545 */
546 /* everything here is constant */
547 struct radeon_semaphore {
548 struct radeon_sa_bo *sa_bo;
549 signed waiters;
550 uint64_t gpu_addr;
551 };
552
553 int radeon_semaphore_create(struct radeon_device *rdev,
554 struct radeon_semaphore **semaphore);
555 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
556 struct radeon_semaphore *semaphore);
557 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
558 struct radeon_semaphore *semaphore);
559 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
560 struct radeon_semaphore *semaphore,
561 int signaler, int waiter);
562 void radeon_semaphore_free(struct radeon_device *rdev,
563 struct radeon_semaphore **semaphore,
564 struct radeon_fence *fence);
565
566 /*
567 * GART structures, functions & helpers
568 */
569 struct radeon_mc;
570
571 #define RADEON_GPU_PAGE_SIZE 4096
572 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
573 #define RADEON_GPU_PAGE_SHIFT 12
574 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
575
576 struct radeon_gart {
577 dma_addr_t table_addr;
578 struct radeon_bo *robj;
579 void *ptr;
580 unsigned num_gpu_pages;
581 unsigned num_cpu_pages;
582 unsigned table_size;
583 struct page **pages;
584 dma_addr_t *pages_addr;
585 bool ready;
586 };
587
588 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
589 void radeon_gart_table_ram_free(struct radeon_device *rdev);
590 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
591 void radeon_gart_table_vram_free(struct radeon_device *rdev);
592 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
593 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
594 int radeon_gart_init(struct radeon_device *rdev);
595 void radeon_gart_fini(struct radeon_device *rdev);
596 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
597 int pages);
598 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
599 int pages, struct page **pagelist,
600 dma_addr_t *dma_addr);
601 void radeon_gart_restore(struct radeon_device *rdev);
602
603
604 /*
605 * GPU MC structures, functions & helpers
606 */
607 struct radeon_mc {
608 resource_size_t aper_size;
609 resource_size_t aper_base;
610 resource_size_t agp_base;
611 /* for some chips with <= 32MB we need to lie
612 * about vram size near mc fb location */
613 u64 mc_vram_size;
614 u64 visible_vram_size;
615 u64 gtt_size;
616 u64 gtt_start;
617 u64 gtt_end;
618 u64 vram_start;
619 u64 vram_end;
620 unsigned vram_width;
621 u64 real_vram_size;
622 int vram_mtrr;
623 bool vram_is_ddr;
624 bool igp_sideport_enabled;
625 u64 gtt_base_align;
626 u64 mc_mask;
627 };
628
629 bool radeon_combios_sideport_present(struct radeon_device *rdev);
630 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
631
632 /*
633 * GPU scratch registers structures, functions & helpers
634 */
635 struct radeon_scratch {
636 unsigned num_reg;
637 uint32_t reg_base;
638 bool free[32];
639 uint32_t reg[32];
640 };
641
642 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
643 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
644
645 /*
646 * GPU doorbell structures, functions & helpers
647 */
648 struct radeon_doorbell {
649 u32 num_pages;
650 bool free[1024];
651 /* doorbell mmio */
652 resource_size_t base;
653 resource_size_t size;
654 void __iomem *ptr;
655 };
656
657 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
658 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
659
660 /*
661 * IRQS.
662 */
663
664 struct radeon_unpin_work {
665 struct work_struct work;
666 struct radeon_device *rdev;
667 int crtc_id;
668 struct radeon_fence *fence;
669 struct drm_pending_vblank_event *event;
670 struct radeon_bo *old_rbo;
671 u64 new_crtc_base;
672 };
673
674 struct r500_irq_stat_regs {
675 u32 disp_int;
676 u32 hdmi0_status;
677 };
678
679 struct r600_irq_stat_regs {
680 u32 disp_int;
681 u32 disp_int_cont;
682 u32 disp_int_cont2;
683 u32 d1grph_int;
684 u32 d2grph_int;
685 u32 hdmi0_status;
686 u32 hdmi1_status;
687 };
688
689 struct evergreen_irq_stat_regs {
690 u32 disp_int;
691 u32 disp_int_cont;
692 u32 disp_int_cont2;
693 u32 disp_int_cont3;
694 u32 disp_int_cont4;
695 u32 disp_int_cont5;
696 u32 d1grph_int;
697 u32 d2grph_int;
698 u32 d3grph_int;
699 u32 d4grph_int;
700 u32 d5grph_int;
701 u32 d6grph_int;
702 u32 afmt_status1;
703 u32 afmt_status2;
704 u32 afmt_status3;
705 u32 afmt_status4;
706 u32 afmt_status5;
707 u32 afmt_status6;
708 };
709
710 struct cik_irq_stat_regs {
711 u32 disp_int;
712 u32 disp_int_cont;
713 u32 disp_int_cont2;
714 u32 disp_int_cont3;
715 u32 disp_int_cont4;
716 u32 disp_int_cont5;
717 u32 disp_int_cont6;
718 u32 d1grph_int;
719 u32 d2grph_int;
720 u32 d3grph_int;
721 u32 d4grph_int;
722 u32 d5grph_int;
723 u32 d6grph_int;
724 };
725
726 union radeon_irq_stat_regs {
727 struct r500_irq_stat_regs r500;
728 struct r600_irq_stat_regs r600;
729 struct evergreen_irq_stat_regs evergreen;
730 struct cik_irq_stat_regs cik;
731 };
732
733 #define RADEON_MAX_HPD_PINS 6
734 #define RADEON_MAX_CRTCS 6
735 #define RADEON_MAX_AFMT_BLOCKS 7
736
737 struct radeon_irq {
738 bool installed;
739 spinlock_t lock;
740 atomic_t ring_int[RADEON_NUM_RINGS];
741 bool crtc_vblank_int[RADEON_MAX_CRTCS];
742 atomic_t pflip[RADEON_MAX_CRTCS];
743 wait_queue_head_t vblank_queue;
744 bool hpd[RADEON_MAX_HPD_PINS];
745 bool afmt[RADEON_MAX_AFMT_BLOCKS];
746 union radeon_irq_stat_regs stat_regs;
747 bool dpm_thermal;
748 };
749
750 int radeon_irq_kms_init(struct radeon_device *rdev);
751 void radeon_irq_kms_fini(struct radeon_device *rdev);
752 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
753 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
754 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
755 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
756 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
757 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
758 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
759 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
760
761 /*
762 * CP & rings.
763 */
764
765 struct radeon_ib {
766 struct radeon_sa_bo *sa_bo;
767 uint32_t length_dw;
768 uint64_t gpu_addr;
769 uint32_t *ptr;
770 int ring;
771 struct radeon_fence *fence;
772 struct radeon_vm *vm;
773 bool is_const_ib;
774 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
775 struct radeon_semaphore *semaphore;
776 };
777
778 struct radeon_ring {
779 struct radeon_bo *ring_obj;
780 volatile uint32_t *ring;
781 unsigned rptr;
782 unsigned rptr_offs;
783 unsigned rptr_reg;
784 unsigned rptr_save_reg;
785 u64 next_rptr_gpu_addr;
786 volatile u32 *next_rptr_cpu_addr;
787 unsigned wptr;
788 unsigned wptr_old;
789 unsigned wptr_reg;
790 unsigned ring_size;
791 unsigned ring_free_dw;
792 int count_dw;
793 unsigned long last_activity;
794 unsigned last_rptr;
795 uint64_t gpu_addr;
796 uint32_t align_mask;
797 uint32_t ptr_mask;
798 bool ready;
799 u32 nop;
800 u32 idx;
801 u64 last_semaphore_signal_addr;
802 u64 last_semaphore_wait_addr;
803 /* for CIK queues */
804 u32 me;
805 u32 pipe;
806 u32 queue;
807 struct radeon_bo *mqd_obj;
808 u32 doorbell_page_num;
809 u32 doorbell_offset;
810 unsigned wptr_offs;
811 };
812
813 struct radeon_mec {
814 struct radeon_bo *hpd_eop_obj;
815 u64 hpd_eop_gpu_addr;
816 u32 num_pipe;
817 u32 num_mec;
818 u32 num_queue;
819 };
820
821 /*
822 * VM
823 */
824
825 /* maximum number of VMIDs */
826 #define RADEON_NUM_VM 16
827
828 /* defines number of bits in page table versus page directory,
829 * a page is 4KB so we have 12 bits offset, 9 bits in the page
830 * table and the remaining 19 bits are in the page directory */
831 #define RADEON_VM_BLOCK_SIZE 9
832
833 /* number of entries in page table */
834 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
835
836 /* PTBs (Page Table Blocks) need to be aligned to 32K */
837 #define RADEON_VM_PTB_ALIGN_SIZE 32768
838 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
839 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
840
841 struct radeon_vm {
842 struct list_head list;
843 struct list_head va;
844 unsigned id;
845
846 /* contains the page directory */
847 struct radeon_sa_bo *page_directory;
848 uint64_t pd_gpu_addr;
849
850 /* array of page tables, one for each page directory entry */
851 struct radeon_sa_bo **page_tables;
852
853 struct mutex mutex;
854 /* last fence for cs using this vm */
855 struct radeon_fence *fence;
856 /* last flush or NULL if we still need to flush */
857 struct radeon_fence *last_flush;
858 };
859
860 struct radeon_vm_manager {
861 struct mutex lock;
862 struct list_head lru_vm;
863 struct radeon_fence *active[RADEON_NUM_VM];
864 struct radeon_sa_manager sa_manager;
865 uint32_t max_pfn;
866 /* number of VMIDs */
867 unsigned nvm;
868 /* vram base address for page table entry */
869 u64 vram_base_offset;
870 /* is vm enabled? */
871 bool enabled;
872 };
873
874 /*
875 * file private structure
876 */
877 struct radeon_fpriv {
878 struct radeon_vm vm;
879 };
880
881 /*
882 * R6xx+ IH ring
883 */
884 struct r600_ih {
885 struct radeon_bo *ring_obj;
886 volatile uint32_t *ring;
887 unsigned rptr;
888 unsigned ring_size;
889 uint64_t gpu_addr;
890 uint32_t ptr_mask;
891 atomic_t lock;
892 bool enabled;
893 };
894
895 /*
896 * RLC stuff
897 */
898 #include "clearstate_defs.h"
899
900 struct radeon_rlc {
901 /* for power gating */
902 struct radeon_bo *save_restore_obj;
903 uint64_t save_restore_gpu_addr;
904 volatile uint32_t *sr_ptr;
905 const u32 *reg_list;
906 u32 reg_list_size;
907 /* for clear state */
908 struct radeon_bo *clear_state_obj;
909 uint64_t clear_state_gpu_addr;
910 volatile uint32_t *cs_ptr;
911 const struct cs_section_def *cs_data;
912 u32 clear_state_size;
913 /* for cp tables */
914 struct radeon_bo *cp_table_obj;
915 uint64_t cp_table_gpu_addr;
916 volatile uint32_t *cp_table_ptr;
917 u32 cp_table_size;
918 };
919
920 int radeon_ib_get(struct radeon_device *rdev, int ring,
921 struct radeon_ib *ib, struct radeon_vm *vm,
922 unsigned size);
923 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
924 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
925 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
926 struct radeon_ib *const_ib);
927 int radeon_ib_pool_init(struct radeon_device *rdev);
928 void radeon_ib_pool_fini(struct radeon_device *rdev);
929 int radeon_ib_ring_tests(struct radeon_device *rdev);
930 /* Ring access between begin & end cannot sleep */
931 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
932 struct radeon_ring *ring);
933 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
934 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
935 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
936 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
937 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
938 void radeon_ring_undo(struct radeon_ring *ring);
939 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
940 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
941 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
942 void radeon_ring_lockup_update(struct radeon_ring *ring);
943 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
944 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
945 uint32_t **data);
946 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
947 unsigned size, uint32_t *data);
948 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
949 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
950 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
951
952
953 /* r600 async dma */
954 void r600_dma_stop(struct radeon_device *rdev);
955 int r600_dma_resume(struct radeon_device *rdev);
956 void r600_dma_fini(struct radeon_device *rdev);
957
958 void cayman_dma_stop(struct radeon_device *rdev);
959 int cayman_dma_resume(struct radeon_device *rdev);
960 void cayman_dma_fini(struct radeon_device *rdev);
961
962 /*
963 * CS.
964 */
965 struct radeon_cs_reloc {
966 struct drm_gem_object *gobj;
967 struct radeon_bo *robj;
968 struct radeon_bo_list lobj;
969 uint32_t handle;
970 uint32_t flags;
971 };
972
973 struct radeon_cs_chunk {
974 uint32_t chunk_id;
975 uint32_t length_dw;
976 int kpage_idx[2];
977 uint32_t *kpage[2];
978 uint32_t *kdata;
979 void __user *user_ptr;
980 int last_copied_page;
981 int last_page_index;
982 };
983
984 struct radeon_cs_parser {
985 struct device *dev;
986 struct radeon_device *rdev;
987 struct drm_file *filp;
988 /* chunks */
989 unsigned nchunks;
990 struct radeon_cs_chunk *chunks;
991 uint64_t *chunks_array;
992 /* IB */
993 unsigned idx;
994 /* relocations */
995 unsigned nrelocs;
996 struct radeon_cs_reloc *relocs;
997 struct radeon_cs_reloc **relocs_ptr;
998 struct list_head validated;
999 unsigned dma_reloc_idx;
1000 /* indices of various chunks */
1001 int chunk_ib_idx;
1002 int chunk_relocs_idx;
1003 int chunk_flags_idx;
1004 int chunk_const_ib_idx;
1005 struct radeon_ib ib;
1006 struct radeon_ib const_ib;
1007 void *track;
1008 unsigned family;
1009 int parser_error;
1010 u32 cs_flags;
1011 u32 ring;
1012 s32 priority;
1013 struct ww_acquire_ctx ticket;
1014 };
1015
1016 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
1017 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
1018
1019 struct radeon_cs_packet {
1020 unsigned idx;
1021 unsigned type;
1022 unsigned reg;
1023 unsigned opcode;
1024 int count;
1025 unsigned one_reg_wr;
1026 };
1027
1028 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1029 struct radeon_cs_packet *pkt,
1030 unsigned idx, unsigned reg);
1031 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1032 struct radeon_cs_packet *pkt);
1033
1034
1035 /*
1036 * AGP
1037 */
1038 int radeon_agp_init(struct radeon_device *rdev);
1039 void radeon_agp_resume(struct radeon_device *rdev);
1040 void radeon_agp_suspend(struct radeon_device *rdev);
1041 void radeon_agp_fini(struct radeon_device *rdev);
1042
1043
1044 /*
1045 * Writeback
1046 */
1047 struct radeon_wb {
1048 struct radeon_bo *wb_obj;
1049 volatile uint32_t *wb;
1050 uint64_t gpu_addr;
1051 bool enabled;
1052 bool use_event;
1053 };
1054
1055 #define RADEON_WB_SCRATCH_OFFSET 0
1056 #define RADEON_WB_RING0_NEXT_RPTR 256
1057 #define RADEON_WB_CP_RPTR_OFFSET 1024
1058 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1059 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1060 #define R600_WB_DMA_RPTR_OFFSET 1792
1061 #define R600_WB_IH_WPTR_OFFSET 2048
1062 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1063 #define R600_WB_EVENT_OFFSET 3072
1064 #define CIK_WB_CP1_WPTR_OFFSET 3328
1065 #define CIK_WB_CP2_WPTR_OFFSET 3584
1066
1067 /**
1068 * struct radeon_pm - power management datas
1069 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1070 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1071 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1072 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1073 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1074 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1075 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1076 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1077 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1078 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1079 * @needed_bandwidth: current bandwidth needs
1080 *
1081 * It keeps track of various data needed to take powermanagement decision.
1082 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1083 * Equation between gpu/memory clock and available bandwidth is hw dependent
1084 * (type of memory, bus size, efficiency, ...)
1085 */
1086
1087 enum radeon_pm_method {
1088 PM_METHOD_PROFILE,
1089 PM_METHOD_DYNPM,
1090 PM_METHOD_DPM,
1091 };
1092
1093 enum radeon_dynpm_state {
1094 DYNPM_STATE_DISABLED,
1095 DYNPM_STATE_MINIMUM,
1096 DYNPM_STATE_PAUSED,
1097 DYNPM_STATE_ACTIVE,
1098 DYNPM_STATE_SUSPENDED,
1099 };
1100 enum radeon_dynpm_action {
1101 DYNPM_ACTION_NONE,
1102 DYNPM_ACTION_MINIMUM,
1103 DYNPM_ACTION_DOWNCLOCK,
1104 DYNPM_ACTION_UPCLOCK,
1105 DYNPM_ACTION_DEFAULT
1106 };
1107
1108 enum radeon_voltage_type {
1109 VOLTAGE_NONE = 0,
1110 VOLTAGE_GPIO,
1111 VOLTAGE_VDDC,
1112 VOLTAGE_SW
1113 };
1114
1115 enum radeon_pm_state_type {
1116 /* not used for dpm */
1117 POWER_STATE_TYPE_DEFAULT,
1118 POWER_STATE_TYPE_POWERSAVE,
1119 /* user selectable states */
1120 POWER_STATE_TYPE_BATTERY,
1121 POWER_STATE_TYPE_BALANCED,
1122 POWER_STATE_TYPE_PERFORMANCE,
1123 /* internal states */
1124 POWER_STATE_TYPE_INTERNAL_UVD,
1125 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1126 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1127 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1128 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1129 POWER_STATE_TYPE_INTERNAL_BOOT,
1130 POWER_STATE_TYPE_INTERNAL_THERMAL,
1131 POWER_STATE_TYPE_INTERNAL_ACPI,
1132 POWER_STATE_TYPE_INTERNAL_ULV,
1133 POWER_STATE_TYPE_INTERNAL_3DPERF,
1134 };
1135
1136 enum radeon_pm_profile_type {
1137 PM_PROFILE_DEFAULT,
1138 PM_PROFILE_AUTO,
1139 PM_PROFILE_LOW,
1140 PM_PROFILE_MID,
1141 PM_PROFILE_HIGH,
1142 };
1143
1144 #define PM_PROFILE_DEFAULT_IDX 0
1145 #define PM_PROFILE_LOW_SH_IDX 1
1146 #define PM_PROFILE_MID_SH_IDX 2
1147 #define PM_PROFILE_HIGH_SH_IDX 3
1148 #define PM_PROFILE_LOW_MH_IDX 4
1149 #define PM_PROFILE_MID_MH_IDX 5
1150 #define PM_PROFILE_HIGH_MH_IDX 6
1151 #define PM_PROFILE_MAX 7
1152
1153 struct radeon_pm_profile {
1154 int dpms_off_ps_idx;
1155 int dpms_on_ps_idx;
1156 int dpms_off_cm_idx;
1157 int dpms_on_cm_idx;
1158 };
1159
1160 enum radeon_int_thermal_type {
1161 THERMAL_TYPE_NONE,
1162 THERMAL_TYPE_EXTERNAL,
1163 THERMAL_TYPE_EXTERNAL_GPIO,
1164 THERMAL_TYPE_RV6XX,
1165 THERMAL_TYPE_RV770,
1166 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1167 THERMAL_TYPE_EVERGREEN,
1168 THERMAL_TYPE_SUMO,
1169 THERMAL_TYPE_NI,
1170 THERMAL_TYPE_SI,
1171 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1172 THERMAL_TYPE_CI,
1173 THERMAL_TYPE_KV,
1174 };
1175
1176 struct radeon_voltage {
1177 enum radeon_voltage_type type;
1178 /* gpio voltage */
1179 struct radeon_gpio_rec gpio;
1180 u32 delay; /* delay in usec from voltage drop to sclk change */
1181 bool active_high; /* voltage drop is active when bit is high */
1182 /* VDDC voltage */
1183 u8 vddc_id; /* index into vddc voltage table */
1184 u8 vddci_id; /* index into vddci voltage table */
1185 bool vddci_enabled;
1186 /* r6xx+ sw */
1187 u16 voltage;
1188 /* evergreen+ vddci */
1189 u16 vddci;
1190 };
1191
1192 /* clock mode flags */
1193 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1194
1195 struct radeon_pm_clock_info {
1196 /* memory clock */
1197 u32 mclk;
1198 /* engine clock */
1199 u32 sclk;
1200 /* voltage info */
1201 struct radeon_voltage voltage;
1202 /* standardized clock flags */
1203 u32 flags;
1204 };
1205
1206 /* state flags */
1207 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1208
1209 struct radeon_power_state {
1210 enum radeon_pm_state_type type;
1211 struct radeon_pm_clock_info *clock_info;
1212 /* number of valid clock modes in this power state */
1213 int num_clock_modes;
1214 struct radeon_pm_clock_info *default_clock_mode;
1215 /* standardized state flags */
1216 u32 flags;
1217 u32 misc; /* vbios specific flags */
1218 u32 misc2; /* vbios specific flags */
1219 int pcie_lanes; /* pcie lanes */
1220 };
1221
1222 /*
1223 * Some modes are overclocked by very low value, accept them
1224 */
1225 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1226
1227 enum radeon_dpm_auto_throttle_src {
1228 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1229 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1230 };
1231
1232 enum radeon_dpm_event_src {
1233 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1234 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1235 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1236 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1237 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1238 };
1239
1240 struct radeon_ps {
1241 u32 caps; /* vbios flags */
1242 u32 class; /* vbios flags */
1243 u32 class2; /* vbios flags */
1244 /* UVD clocks */
1245 u32 vclk;
1246 u32 dclk;
1247 /* VCE clocks */
1248 u32 evclk;
1249 u32 ecclk;
1250 /* asic priv */
1251 void *ps_priv;
1252 };
1253
1254 struct radeon_dpm_thermal {
1255 /* thermal interrupt work */
1256 struct work_struct work;
1257 /* low temperature threshold */
1258 int min_temp;
1259 /* high temperature threshold */
1260 int max_temp;
1261 /* was interrupt low to high or high to low */
1262 bool high_to_low;
1263 };
1264
1265 enum radeon_clk_action
1266 {
1267 RADEON_SCLK_UP = 1,
1268 RADEON_SCLK_DOWN
1269 };
1270
1271 struct radeon_blacklist_clocks
1272 {
1273 u32 sclk;
1274 u32 mclk;
1275 enum radeon_clk_action action;
1276 };
1277
1278 struct radeon_clock_and_voltage_limits {
1279 u32 sclk;
1280 u32 mclk;
1281 u16 vddc;
1282 u16 vddci;
1283 };
1284
1285 struct radeon_clock_array {
1286 u32 count;
1287 u32 *values;
1288 };
1289
1290 struct radeon_clock_voltage_dependency_entry {
1291 u32 clk;
1292 u16 v;
1293 };
1294
1295 struct radeon_clock_voltage_dependency_table {
1296 u32 count;
1297 struct radeon_clock_voltage_dependency_entry *entries;
1298 };
1299
1300 union radeon_cac_leakage_entry {
1301 struct {
1302 u16 vddc;
1303 u32 leakage;
1304 };
1305 struct {
1306 u16 vddc1;
1307 u16 vddc2;
1308 u16 vddc3;
1309 };
1310 };
1311
1312 struct radeon_cac_leakage_table {
1313 u32 count;
1314 union radeon_cac_leakage_entry *entries;
1315 };
1316
1317 struct radeon_phase_shedding_limits_entry {
1318 u16 voltage;
1319 u32 sclk;
1320 u32 mclk;
1321 };
1322
1323 struct radeon_phase_shedding_limits_table {
1324 u32 count;
1325 struct radeon_phase_shedding_limits_entry *entries;
1326 };
1327
1328 struct radeon_uvd_clock_voltage_dependency_entry {
1329 u32 vclk;
1330 u32 dclk;
1331 u16 v;
1332 };
1333
1334 struct radeon_uvd_clock_voltage_dependency_table {
1335 u8 count;
1336 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1337 };
1338
1339 struct radeon_vce_clock_voltage_dependency_entry {
1340 u32 ecclk;
1341 u32 evclk;
1342 u16 v;
1343 };
1344
1345 struct radeon_vce_clock_voltage_dependency_table {
1346 u8 count;
1347 struct radeon_vce_clock_voltage_dependency_entry *entries;
1348 };
1349
1350 struct radeon_ppm_table {
1351 u8 ppm_design;
1352 u16 cpu_core_number;
1353 u32 platform_tdp;
1354 u32 small_ac_platform_tdp;
1355 u32 platform_tdc;
1356 u32 small_ac_platform_tdc;
1357 u32 apu_tdp;
1358 u32 dgpu_tdp;
1359 u32 dgpu_ulv_power;
1360 u32 tj_max;
1361 };
1362
1363 struct radeon_cac_tdp_table {
1364 u16 tdp;
1365 u16 configurable_tdp;
1366 u16 tdc;
1367 u16 battery_power_limit;
1368 u16 small_power_limit;
1369 u16 low_cac_leakage;
1370 u16 high_cac_leakage;
1371 u16 maximum_power_delivery_limit;
1372 };
1373
1374 struct radeon_dpm_dynamic_state {
1375 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1376 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1377 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1378 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1379 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1380 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1381 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1382 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1383 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1384 struct radeon_clock_array valid_sclk_values;
1385 struct radeon_clock_array valid_mclk_values;
1386 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1387 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1388 u32 mclk_sclk_ratio;
1389 u32 sclk_mclk_delta;
1390 u16 vddc_vddci_delta;
1391 u16 min_vddc_for_pcie_gen2;
1392 struct radeon_cac_leakage_table cac_leakage_table;
1393 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1394 struct radeon_ppm_table *ppm_table;
1395 struct radeon_cac_tdp_table *cac_tdp_table;
1396 };
1397
1398 struct radeon_dpm_fan {
1399 u16 t_min;
1400 u16 t_med;
1401 u16 t_high;
1402 u16 pwm_min;
1403 u16 pwm_med;
1404 u16 pwm_high;
1405 u8 t_hyst;
1406 u32 cycle_delay;
1407 u16 t_max;
1408 bool ucode_fan_control;
1409 };
1410
1411 enum radeon_pcie_gen {
1412 RADEON_PCIE_GEN1 = 0,
1413 RADEON_PCIE_GEN2 = 1,
1414 RADEON_PCIE_GEN3 = 2,
1415 RADEON_PCIE_GEN_INVALID = 0xffff
1416 };
1417
1418 enum radeon_dpm_forced_level {
1419 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1420 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1421 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1422 };
1423
1424 struct radeon_dpm {
1425 struct radeon_ps *ps;
1426 /* number of valid power states */
1427 int num_ps;
1428 /* current power state that is active */
1429 struct radeon_ps *current_ps;
1430 /* requested power state */
1431 struct radeon_ps *requested_ps;
1432 /* boot up power state */
1433 struct radeon_ps *boot_ps;
1434 /* default uvd power state */
1435 struct radeon_ps *uvd_ps;
1436 enum radeon_pm_state_type state;
1437 enum radeon_pm_state_type user_state;
1438 u32 platform_caps;
1439 u32 voltage_response_time;
1440 u32 backbias_response_time;
1441 void *priv;
1442 u32 new_active_crtcs;
1443 int new_active_crtc_count;
1444 u32 current_active_crtcs;
1445 int current_active_crtc_count;
1446 struct radeon_dpm_dynamic_state dyn_state;
1447 struct radeon_dpm_fan fan;
1448 u32 tdp_limit;
1449 u32 near_tdp_limit;
1450 u32 near_tdp_limit_adjusted;
1451 u32 sq_ramping_threshold;
1452 u32 cac_leakage;
1453 u16 tdp_od_limit;
1454 u32 tdp_adjustment;
1455 u16 load_line_slope;
1456 bool power_control;
1457 bool ac_power;
1458 /* special states active */
1459 bool thermal_active;
1460 bool uvd_active;
1461 /* thermal handling */
1462 struct radeon_dpm_thermal thermal;
1463 /* forced levels */
1464 enum radeon_dpm_forced_level forced_level;
1465 /* track UVD streams */
1466 unsigned sd;
1467 unsigned hd;
1468 };
1469
1470 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1471
1472 struct radeon_pm {
1473 struct mutex mutex;
1474 /* write locked while reprogramming mclk */
1475 struct rw_semaphore mclk_lock;
1476 u32 active_crtcs;
1477 int active_crtc_count;
1478 int req_vblank;
1479 bool vblank_sync;
1480 fixed20_12 max_bandwidth;
1481 fixed20_12 igp_sideport_mclk;
1482 fixed20_12 igp_system_mclk;
1483 fixed20_12 igp_ht_link_clk;
1484 fixed20_12 igp_ht_link_width;
1485 fixed20_12 k8_bandwidth;
1486 fixed20_12 sideport_bandwidth;
1487 fixed20_12 ht_bandwidth;
1488 fixed20_12 core_bandwidth;
1489 fixed20_12 sclk;
1490 fixed20_12 mclk;
1491 fixed20_12 needed_bandwidth;
1492 struct radeon_power_state *power_state;
1493 /* number of valid power states */
1494 int num_power_states;
1495 int current_power_state_index;
1496 int current_clock_mode_index;
1497 int requested_power_state_index;
1498 int requested_clock_mode_index;
1499 int default_power_state_index;
1500 u32 current_sclk;
1501 u32 current_mclk;
1502 u16 current_vddc;
1503 u16 current_vddci;
1504 u32 default_sclk;
1505 u32 default_mclk;
1506 u16 default_vddc;
1507 u16 default_vddci;
1508 struct radeon_i2c_chan *i2c_bus;
1509 /* selected pm method */
1510 enum radeon_pm_method pm_method;
1511 /* dynpm power management */
1512 struct delayed_work dynpm_idle_work;
1513 enum radeon_dynpm_state dynpm_state;
1514 enum radeon_dynpm_action dynpm_planned_action;
1515 unsigned long dynpm_action_timeout;
1516 bool dynpm_can_upclock;
1517 bool dynpm_can_downclock;
1518 /* profile-based power management */
1519 enum radeon_pm_profile_type profile;
1520 int profile_index;
1521 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1522 /* internal thermal controller on rv6xx+ */
1523 enum radeon_int_thermal_type int_thermal_type;
1524 struct device *int_hwmon_dev;
1525 /* dpm */
1526 bool dpm_enabled;
1527 struct radeon_dpm dpm;
1528 };
1529
1530 int radeon_pm_get_type_index(struct radeon_device *rdev,
1531 enum radeon_pm_state_type ps_type,
1532 int instance);
1533 /*
1534 * UVD
1535 */
1536 #define RADEON_MAX_UVD_HANDLES 10
1537 #define RADEON_UVD_STACK_SIZE (1024*1024)
1538 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1539
1540 struct radeon_uvd {
1541 struct radeon_bo *vcpu_bo;
1542 void *cpu_addr;
1543 uint64_t gpu_addr;
1544 void *saved_bo;
1545 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1546 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1547 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1548 struct delayed_work idle_work;
1549 };
1550
1551 int radeon_uvd_init(struct radeon_device *rdev);
1552 void radeon_uvd_fini(struct radeon_device *rdev);
1553 int radeon_uvd_suspend(struct radeon_device *rdev);
1554 int radeon_uvd_resume(struct radeon_device *rdev);
1555 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1556 uint32_t handle, struct radeon_fence **fence);
1557 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1558 uint32_t handle, struct radeon_fence **fence);
1559 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1560 void radeon_uvd_free_handles(struct radeon_device *rdev,
1561 struct drm_file *filp);
1562 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1563 void radeon_uvd_note_usage(struct radeon_device *rdev);
1564 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1565 unsigned vclk, unsigned dclk,
1566 unsigned vco_min, unsigned vco_max,
1567 unsigned fb_factor, unsigned fb_mask,
1568 unsigned pd_min, unsigned pd_max,
1569 unsigned pd_even,
1570 unsigned *optimal_fb_div,
1571 unsigned *optimal_vclk_div,
1572 unsigned *optimal_dclk_div);
1573 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1574 unsigned cg_upll_func_cntl);
1575
1576 struct r600_audio_pin {
1577 int channels;
1578 int rate;
1579 int bits_per_sample;
1580 u8 status_bits;
1581 u8 category_code;
1582 u32 offset;
1583 bool connected;
1584 u32 id;
1585 };
1586
1587 struct r600_audio {
1588 bool enabled;
1589 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1590 int num_pins;
1591 };
1592
1593 /*
1594 * Benchmarking
1595 */
1596 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1597
1598
1599 /*
1600 * Testing
1601 */
1602 void radeon_test_moves(struct radeon_device *rdev);
1603 void radeon_test_ring_sync(struct radeon_device *rdev,
1604 struct radeon_ring *cpA,
1605 struct radeon_ring *cpB);
1606 void radeon_test_syncing(struct radeon_device *rdev);
1607
1608
1609 /*
1610 * Debugfs
1611 */
1612 struct radeon_debugfs {
1613 struct drm_info_list *files;
1614 unsigned num_files;
1615 };
1616
1617 int radeon_debugfs_add_files(struct radeon_device *rdev,
1618 struct drm_info_list *files,
1619 unsigned nfiles);
1620 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1621
1622 /*
1623 * ASIC ring specific functions.
1624 */
1625 struct radeon_asic_ring {
1626 /* ring read/write ptr handling */
1627 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1628 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1629 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1630
1631 /* validating and patching of IBs */
1632 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1633 int (*cs_parse)(struct radeon_cs_parser *p);
1634
1635 /* command emmit functions */
1636 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1637 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1638 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1639 struct radeon_semaphore *semaphore, bool emit_wait);
1640 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1641
1642 /* testing functions */
1643 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1644 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1645 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1646
1647 /* deprecated */
1648 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1649 };
1650
1651 /*
1652 * ASIC specific functions.
1653 */
1654 struct radeon_asic {
1655 int (*init)(struct radeon_device *rdev);
1656 void (*fini)(struct radeon_device *rdev);
1657 int (*resume)(struct radeon_device *rdev);
1658 int (*suspend)(struct radeon_device *rdev);
1659 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1660 int (*asic_reset)(struct radeon_device *rdev);
1661 /* ioctl hw specific callback. Some hw might want to perform special
1662 * operation on specific ioctl. For instance on wait idle some hw
1663 * might want to perform and HDP flush through MMIO as it seems that
1664 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1665 * through ring.
1666 */
1667 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1668 /* check if 3D engine is idle */
1669 bool (*gui_idle)(struct radeon_device *rdev);
1670 /* wait for mc_idle */
1671 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1672 /* get the reference clock */
1673 u32 (*get_xclk)(struct radeon_device *rdev);
1674 /* get the gpu clock counter */
1675 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1676 /* gart */
1677 struct {
1678 void (*tlb_flush)(struct radeon_device *rdev);
1679 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1680 } gart;
1681 struct {
1682 int (*init)(struct radeon_device *rdev);
1683 void (*fini)(struct radeon_device *rdev);
1684
1685 u32 pt_ring_index;
1686 void (*set_page)(struct radeon_device *rdev,
1687 struct radeon_ib *ib,
1688 uint64_t pe,
1689 uint64_t addr, unsigned count,
1690 uint32_t incr, uint32_t flags);
1691 } vm;
1692 /* ring specific callbacks */
1693 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1694 /* irqs */
1695 struct {
1696 int (*set)(struct radeon_device *rdev);
1697 int (*process)(struct radeon_device *rdev);
1698 } irq;
1699 /* displays */
1700 struct {
1701 /* display watermarks */
1702 void (*bandwidth_update)(struct radeon_device *rdev);
1703 /* get frame count */
1704 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1705 /* wait for vblank */
1706 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1707 /* set backlight level */
1708 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1709 /* get backlight level */
1710 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1711 /* audio callbacks */
1712 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1713 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1714 } display;
1715 /* copy functions for bo handling */
1716 struct {
1717 int (*blit)(struct radeon_device *rdev,
1718 uint64_t src_offset,
1719 uint64_t dst_offset,
1720 unsigned num_gpu_pages,
1721 struct radeon_fence **fence);
1722 u32 blit_ring_index;
1723 int (*dma)(struct radeon_device *rdev,
1724 uint64_t src_offset,
1725 uint64_t dst_offset,
1726 unsigned num_gpu_pages,
1727 struct radeon_fence **fence);
1728 u32 dma_ring_index;
1729 /* method used for bo copy */
1730 int (*copy)(struct radeon_device *rdev,
1731 uint64_t src_offset,
1732 uint64_t dst_offset,
1733 unsigned num_gpu_pages,
1734 struct radeon_fence **fence);
1735 /* ring used for bo copies */
1736 u32 copy_ring_index;
1737 } copy;
1738 /* surfaces */
1739 struct {
1740 int (*set_reg)(struct radeon_device *rdev, int reg,
1741 uint32_t tiling_flags, uint32_t pitch,
1742 uint32_t offset, uint32_t obj_size);
1743 void (*clear_reg)(struct radeon_device *rdev, int reg);
1744 } surface;
1745 /* hotplug detect */
1746 struct {
1747 void (*init)(struct radeon_device *rdev);
1748 void (*fini)(struct radeon_device *rdev);
1749 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1750 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1751 } hpd;
1752 /* static power management */
1753 struct {
1754 void (*misc)(struct radeon_device *rdev);
1755 void (*prepare)(struct radeon_device *rdev);
1756 void (*finish)(struct radeon_device *rdev);
1757 void (*init_profile)(struct radeon_device *rdev);
1758 void (*get_dynpm_state)(struct radeon_device *rdev);
1759 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1760 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1761 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1762 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1763 int (*get_pcie_lanes)(struct radeon_device *rdev);
1764 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1765 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1766 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1767 int (*get_temperature)(struct radeon_device *rdev);
1768 } pm;
1769 /* dynamic power management */
1770 struct {
1771 int (*init)(struct radeon_device *rdev);
1772 void (*setup_asic)(struct radeon_device *rdev);
1773 int (*enable)(struct radeon_device *rdev);
1774 void (*disable)(struct radeon_device *rdev);
1775 int (*pre_set_power_state)(struct radeon_device *rdev);
1776 int (*set_power_state)(struct radeon_device *rdev);
1777 void (*post_set_power_state)(struct radeon_device *rdev);
1778 void (*display_configuration_changed)(struct radeon_device *rdev);
1779 void (*fini)(struct radeon_device *rdev);
1780 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1781 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1782 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1783 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1784 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1785 bool (*vblank_too_short)(struct radeon_device *rdev);
1786 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1787 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1788 } dpm;
1789 /* pageflipping */
1790 struct {
1791 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1792 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1793 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1794 } pflip;
1795 };
1796
1797 /*
1798 * Asic structures
1799 */
1800 struct r100_asic {
1801 const unsigned *reg_safe_bm;
1802 unsigned reg_safe_bm_size;
1803 u32 hdp_cntl;
1804 };
1805
1806 struct r300_asic {
1807 const unsigned *reg_safe_bm;
1808 unsigned reg_safe_bm_size;
1809 u32 resync_scratch;
1810 u32 hdp_cntl;
1811 };
1812
1813 struct r600_asic {
1814 unsigned max_pipes;
1815 unsigned max_tile_pipes;
1816 unsigned max_simds;
1817 unsigned max_backends;
1818 unsigned max_gprs;
1819 unsigned max_threads;
1820 unsigned max_stack_entries;
1821 unsigned max_hw_contexts;
1822 unsigned max_gs_threads;
1823 unsigned sx_max_export_size;
1824 unsigned sx_max_export_pos_size;
1825 unsigned sx_max_export_smx_size;
1826 unsigned sq_num_cf_insts;
1827 unsigned tiling_nbanks;
1828 unsigned tiling_npipes;
1829 unsigned tiling_group_size;
1830 unsigned tile_config;
1831 unsigned backend_map;
1832 };
1833
1834 struct rv770_asic {
1835 unsigned max_pipes;
1836 unsigned max_tile_pipes;
1837 unsigned max_simds;
1838 unsigned max_backends;
1839 unsigned max_gprs;
1840 unsigned max_threads;
1841 unsigned max_stack_entries;
1842 unsigned max_hw_contexts;
1843 unsigned max_gs_threads;
1844 unsigned sx_max_export_size;
1845 unsigned sx_max_export_pos_size;
1846 unsigned sx_max_export_smx_size;
1847 unsigned sq_num_cf_insts;
1848 unsigned sx_num_of_sets;
1849 unsigned sc_prim_fifo_size;
1850 unsigned sc_hiz_tile_fifo_size;
1851 unsigned sc_earlyz_tile_fifo_fize;
1852 unsigned tiling_nbanks;
1853 unsigned tiling_npipes;
1854 unsigned tiling_group_size;
1855 unsigned tile_config;
1856 unsigned backend_map;
1857 };
1858
1859 struct evergreen_asic {
1860 unsigned num_ses;
1861 unsigned max_pipes;
1862 unsigned max_tile_pipes;
1863 unsigned max_simds;
1864 unsigned max_backends;
1865 unsigned max_gprs;
1866 unsigned max_threads;
1867 unsigned max_stack_entries;
1868 unsigned max_hw_contexts;
1869 unsigned max_gs_threads;
1870 unsigned sx_max_export_size;
1871 unsigned sx_max_export_pos_size;
1872 unsigned sx_max_export_smx_size;
1873 unsigned sq_num_cf_insts;
1874 unsigned sx_num_of_sets;
1875 unsigned sc_prim_fifo_size;
1876 unsigned sc_hiz_tile_fifo_size;
1877 unsigned sc_earlyz_tile_fifo_size;
1878 unsigned tiling_nbanks;
1879 unsigned tiling_npipes;
1880 unsigned tiling_group_size;
1881 unsigned tile_config;
1882 unsigned backend_map;
1883 };
1884
1885 struct cayman_asic {
1886 unsigned max_shader_engines;
1887 unsigned max_pipes_per_simd;
1888 unsigned max_tile_pipes;
1889 unsigned max_simds_per_se;
1890 unsigned max_backends_per_se;
1891 unsigned max_texture_channel_caches;
1892 unsigned max_gprs;
1893 unsigned max_threads;
1894 unsigned max_gs_threads;
1895 unsigned max_stack_entries;
1896 unsigned sx_num_of_sets;
1897 unsigned sx_max_export_size;
1898 unsigned sx_max_export_pos_size;
1899 unsigned sx_max_export_smx_size;
1900 unsigned max_hw_contexts;
1901 unsigned sq_num_cf_insts;
1902 unsigned sc_prim_fifo_size;
1903 unsigned sc_hiz_tile_fifo_size;
1904 unsigned sc_earlyz_tile_fifo_size;
1905
1906 unsigned num_shader_engines;
1907 unsigned num_shader_pipes_per_simd;
1908 unsigned num_tile_pipes;
1909 unsigned num_simds_per_se;
1910 unsigned num_backends_per_se;
1911 unsigned backend_disable_mask_per_asic;
1912 unsigned backend_map;
1913 unsigned num_texture_channel_caches;
1914 unsigned mem_max_burst_length_bytes;
1915 unsigned mem_row_size_in_kb;
1916 unsigned shader_engine_tile_size;
1917 unsigned num_gpus;
1918 unsigned multi_gpu_tile_size;
1919
1920 unsigned tile_config;
1921 };
1922
1923 struct si_asic {
1924 unsigned max_shader_engines;
1925 unsigned max_tile_pipes;
1926 unsigned max_cu_per_sh;
1927 unsigned max_sh_per_se;
1928 unsigned max_backends_per_se;
1929 unsigned max_texture_channel_caches;
1930 unsigned max_gprs;
1931 unsigned max_gs_threads;
1932 unsigned max_hw_contexts;
1933 unsigned sc_prim_fifo_size_frontend;
1934 unsigned sc_prim_fifo_size_backend;
1935 unsigned sc_hiz_tile_fifo_size;
1936 unsigned sc_earlyz_tile_fifo_size;
1937
1938 unsigned num_tile_pipes;
1939 unsigned backend_enable_mask;
1940 unsigned backend_disable_mask_per_asic;
1941 unsigned backend_map;
1942 unsigned num_texture_channel_caches;
1943 unsigned mem_max_burst_length_bytes;
1944 unsigned mem_row_size_in_kb;
1945 unsigned shader_engine_tile_size;
1946 unsigned num_gpus;
1947 unsigned multi_gpu_tile_size;
1948
1949 unsigned tile_config;
1950 uint32_t tile_mode_array[32];
1951 };
1952
1953 struct cik_asic {
1954 unsigned max_shader_engines;
1955 unsigned max_tile_pipes;
1956 unsigned max_cu_per_sh;
1957 unsigned max_sh_per_se;
1958 unsigned max_backends_per_se;
1959 unsigned max_texture_channel_caches;
1960 unsigned max_gprs;
1961 unsigned max_gs_threads;
1962 unsigned max_hw_contexts;
1963 unsigned sc_prim_fifo_size_frontend;
1964 unsigned sc_prim_fifo_size_backend;
1965 unsigned sc_hiz_tile_fifo_size;
1966 unsigned sc_earlyz_tile_fifo_size;
1967
1968 unsigned num_tile_pipes;
1969 unsigned backend_enable_mask;
1970 unsigned backend_disable_mask_per_asic;
1971 unsigned backend_map;
1972 unsigned num_texture_channel_caches;
1973 unsigned mem_max_burst_length_bytes;
1974 unsigned mem_row_size_in_kb;
1975 unsigned shader_engine_tile_size;
1976 unsigned num_gpus;
1977 unsigned multi_gpu_tile_size;
1978
1979 unsigned tile_config;
1980 uint32_t tile_mode_array[32];
1981 };
1982
1983 union radeon_asic_config {
1984 struct r300_asic r300;
1985 struct r100_asic r100;
1986 struct r600_asic r600;
1987 struct rv770_asic rv770;
1988 struct evergreen_asic evergreen;
1989 struct cayman_asic cayman;
1990 struct si_asic si;
1991 struct cik_asic cik;
1992 };
1993
1994 /*
1995 * asic initizalization from radeon_asic.c
1996 */
1997 void radeon_agp_disable(struct radeon_device *rdev);
1998 int radeon_asic_init(struct radeon_device *rdev);
1999
2000
2001 /*
2002 * IOCTL.
2003 */
2004 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2005 struct drm_file *filp);
2006 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2007 struct drm_file *filp);
2008 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2009 struct drm_file *file_priv);
2010 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2011 struct drm_file *file_priv);
2012 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2013 struct drm_file *file_priv);
2014 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2015 struct drm_file *file_priv);
2016 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *filp);
2018 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2019 struct drm_file *filp);
2020 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2021 struct drm_file *filp);
2022 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2023 struct drm_file *filp);
2024 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2025 struct drm_file *filp);
2026 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2027 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2028 struct drm_file *filp);
2029 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2030 struct drm_file *filp);
2031
2032 /* VRAM scratch page for HDP bug, default vram page */
2033 struct r600_vram_scratch {
2034 struct radeon_bo *robj;
2035 volatile uint32_t *ptr;
2036 u64 gpu_addr;
2037 };
2038
2039 /*
2040 * ACPI
2041 */
2042 struct radeon_atif_notification_cfg {
2043 bool enabled;
2044 int command_code;
2045 };
2046
2047 struct radeon_atif_notifications {
2048 bool display_switch;
2049 bool expansion_mode_change;
2050 bool thermal_state;
2051 bool forced_power_state;
2052 bool system_power_state;
2053 bool display_conf_change;
2054 bool px_gfx_switch;
2055 bool brightness_change;
2056 bool dgpu_display_event;
2057 };
2058
2059 struct radeon_atif_functions {
2060 bool system_params;
2061 bool sbios_requests;
2062 bool select_active_disp;
2063 bool lid_state;
2064 bool get_tv_standard;
2065 bool set_tv_standard;
2066 bool get_panel_expansion_mode;
2067 bool set_panel_expansion_mode;
2068 bool temperature_change;
2069 bool graphics_device_types;
2070 };
2071
2072 struct radeon_atif {
2073 struct radeon_atif_notifications notifications;
2074 struct radeon_atif_functions functions;
2075 struct radeon_atif_notification_cfg notification_cfg;
2076 struct radeon_encoder *encoder_for_bl;
2077 };
2078
2079 struct radeon_atcs_functions {
2080 bool get_ext_state;
2081 bool pcie_perf_req;
2082 bool pcie_dev_rdy;
2083 bool pcie_bus_width;
2084 };
2085
2086 struct radeon_atcs {
2087 struct radeon_atcs_functions functions;
2088 };
2089
2090 /*
2091 * Core structure, functions and helpers.
2092 */
2093 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2094 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2095
2096 struct radeon_device {
2097 struct device *dev;
2098 struct drm_device *ddev;
2099 struct pci_dev *pdev;
2100 struct rw_semaphore exclusive_lock;
2101 /* ASIC */
2102 union radeon_asic_config config;
2103 enum radeon_family family;
2104 unsigned long flags;
2105 int usec_timeout;
2106 enum radeon_pll_errata pll_errata;
2107 int num_gb_pipes;
2108 int num_z_pipes;
2109 int disp_priority;
2110 /* BIOS */
2111 uint8_t *bios;
2112 bool is_atom_bios;
2113 uint16_t bios_header_start;
2114 struct radeon_bo *stollen_vga_memory;
2115 /* Register mmio */
2116 resource_size_t rmmio_base;
2117 resource_size_t rmmio_size;
2118 /* protects concurrent MM_INDEX/DATA based register access */
2119 spinlock_t mmio_idx_lock;
2120 /* protects concurrent SMC based register access */
2121 spinlock_t smc_idx_lock;
2122 /* protects concurrent PLL register access */
2123 spinlock_t pll_idx_lock;
2124 /* protects concurrent MC register access */
2125 spinlock_t mc_idx_lock;
2126 /* protects concurrent PCIE register access */
2127 spinlock_t pcie_idx_lock;
2128 /* protects concurrent PCIE_PORT register access */
2129 spinlock_t pciep_idx_lock;
2130 /* protects concurrent PIF register access */
2131 spinlock_t pif_idx_lock;
2132 /* protects concurrent CG register access */
2133 spinlock_t cg_idx_lock;
2134 /* protects concurrent UVD register access */
2135 spinlock_t uvd_idx_lock;
2136 /* protects concurrent RCU register access */
2137 spinlock_t rcu_idx_lock;
2138 /* protects concurrent DIDT register access */
2139 spinlock_t didt_idx_lock;
2140 /* protects concurrent ENDPOINT (audio) register access */
2141 spinlock_t end_idx_lock;
2142 void __iomem *rmmio;
2143 radeon_rreg_t mc_rreg;
2144 radeon_wreg_t mc_wreg;
2145 radeon_rreg_t pll_rreg;
2146 radeon_wreg_t pll_wreg;
2147 uint32_t pcie_reg_mask;
2148 radeon_rreg_t pciep_rreg;
2149 radeon_wreg_t pciep_wreg;
2150 /* io port */
2151 void __iomem *rio_mem;
2152 resource_size_t rio_mem_size;
2153 struct radeon_clock clock;
2154 struct radeon_mc mc;
2155 struct radeon_gart gart;
2156 struct radeon_mode_info mode_info;
2157 struct radeon_scratch scratch;
2158 struct radeon_doorbell doorbell;
2159 struct radeon_mman mman;
2160 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2161 wait_queue_head_t fence_queue;
2162 struct mutex ring_lock;
2163 struct radeon_ring ring[RADEON_NUM_RINGS];
2164 bool ib_pool_ready;
2165 struct radeon_sa_manager ring_tmp_bo;
2166 struct radeon_irq irq;
2167 struct radeon_asic *asic;
2168 struct radeon_gem gem;
2169 struct radeon_pm pm;
2170 struct radeon_uvd uvd;
2171 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2172 struct radeon_wb wb;
2173 struct radeon_dummy_page dummy_page;
2174 bool shutdown;
2175 bool suspend;
2176 bool need_dma32;
2177 bool accel_working;
2178 bool fastfb_working; /* IGP feature*/
2179 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2180 const struct firmware *me_fw; /* all family ME firmware */
2181 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2182 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2183 const struct firmware *mc_fw; /* NI MC firmware */
2184 const struct firmware *ce_fw; /* SI CE firmware */
2185 const struct firmware *mec_fw; /* CIK MEC firmware */
2186 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2187 const struct firmware *smc_fw; /* SMC firmware */
2188 const struct firmware *uvd_fw; /* UVD firmware */
2189 struct r600_vram_scratch vram_scratch;
2190 int msi_enabled; /* msi enabled */
2191 struct r600_ih ih; /* r6/700 interrupt ring */
2192 struct radeon_rlc rlc;
2193 struct radeon_mec mec;
2194 struct work_struct hotplug_work;
2195 struct work_struct audio_work;
2196 struct work_struct reset_work;
2197 int num_crtc; /* number of crtcs */
2198 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2199 bool has_uvd;
2200 struct r600_audio audio; /* audio stuff */
2201 struct notifier_block acpi_nb;
2202 /* only one userspace can use Hyperz features or CMASK at a time */
2203 struct drm_file *hyperz_filp;
2204 struct drm_file *cmask_filp;
2205 /* i2c buses */
2206 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2207 /* debugfs */
2208 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2209 unsigned debugfs_count;
2210 /* virtual memory */
2211 struct radeon_vm_manager vm_manager;
2212 struct mutex gpu_clock_mutex;
2213 /* ACPI interface */
2214 struct radeon_atif atif;
2215 struct radeon_atcs atcs;
2216 /* srbm instance registers */
2217 struct mutex srbm_mutex;
2218 /* clock, powergating flags */
2219 u32 cg_flags;
2220 u32 pg_flags;
2221 };
2222
2223 int radeon_device_init(struct radeon_device *rdev,
2224 struct drm_device *ddev,
2225 struct pci_dev *pdev,
2226 uint32_t flags);
2227 void radeon_device_fini(struct radeon_device *rdev);
2228 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2229
2230 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2231 bool always_indirect);
2232 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2233 bool always_indirect);
2234 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2235 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2236
2237 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2238 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2239
2240 /*
2241 * Cast helper
2242 */
2243 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2244
2245 /*
2246 * Registers read & write functions.
2247 */
2248 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2249 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2250 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2251 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2252 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2253 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2254 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2255 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2256 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2257 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2258 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2259 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2260 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2261 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2262 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2263 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2264 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2265 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2266 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2267 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2268 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2269 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2270 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2271 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2272 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2273 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2274 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2275 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2276 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2277 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2278 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2279 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2280 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2281 #define WREG32_P(reg, val, mask) \
2282 do { \
2283 uint32_t tmp_ = RREG32(reg); \
2284 tmp_ &= (mask); \
2285 tmp_ |= ((val) & ~(mask)); \
2286 WREG32(reg, tmp_); \
2287 } while (0)
2288 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2289 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2290 #define WREG32_PLL_P(reg, val, mask) \
2291 do { \
2292 uint32_t tmp_ = RREG32_PLL(reg); \
2293 tmp_ &= (mask); \
2294 tmp_ |= ((val) & ~(mask)); \
2295 WREG32_PLL(reg, tmp_); \
2296 } while (0)
2297 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2298 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2299 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2300
2301 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2302 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2303
2304 /*
2305 * Indirect registers accessor
2306 */
2307 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2308 {
2309 unsigned long flags;
2310 uint32_t r;
2311
2312 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2313 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2314 r = RREG32(RADEON_PCIE_DATA);
2315 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2316 return r;
2317 }
2318
2319 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2320 {
2321 unsigned long flags;
2322
2323 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2324 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2325 WREG32(RADEON_PCIE_DATA, (v));
2326 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2327 }
2328
2329 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2330 {
2331 unsigned long flags;
2332 u32 r;
2333
2334 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2335 WREG32(TN_SMC_IND_INDEX_0, (reg));
2336 r = RREG32(TN_SMC_IND_DATA_0);
2337 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2338 return r;
2339 }
2340
2341 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2342 {
2343 unsigned long flags;
2344
2345 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2346 WREG32(TN_SMC_IND_INDEX_0, (reg));
2347 WREG32(TN_SMC_IND_DATA_0, (v));
2348 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2349 }
2350
2351 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2352 {
2353 unsigned long flags;
2354 u32 r;
2355
2356 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2357 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2358 r = RREG32(R600_RCU_DATA);
2359 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2360 return r;
2361 }
2362
2363 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2364 {
2365 unsigned long flags;
2366
2367 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2368 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2369 WREG32(R600_RCU_DATA, (v));
2370 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2371 }
2372
2373 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2374 {
2375 unsigned long flags;
2376 u32 r;
2377
2378 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2379 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2380 r = RREG32(EVERGREEN_CG_IND_DATA);
2381 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2382 return r;
2383 }
2384
2385 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2386 {
2387 unsigned long flags;
2388
2389 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2390 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2391 WREG32(EVERGREEN_CG_IND_DATA, (v));
2392 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2393 }
2394
2395 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2396 {
2397 unsigned long flags;
2398 u32 r;
2399
2400 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2401 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2402 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2403 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2404 return r;
2405 }
2406
2407 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2408 {
2409 unsigned long flags;
2410
2411 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2412 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2413 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2414 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2415 }
2416
2417 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2418 {
2419 unsigned long flags;
2420 u32 r;
2421
2422 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2423 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2424 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2425 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2426 return r;
2427 }
2428
2429 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2430 {
2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2434 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2435 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2436 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2437 }
2438
2439 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2440 {
2441 unsigned long flags;
2442 u32 r;
2443
2444 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2445 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2446 r = RREG32(R600_UVD_CTX_DATA);
2447 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2448 return r;
2449 }
2450
2451 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2452 {
2453 unsigned long flags;
2454
2455 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2456 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2457 WREG32(R600_UVD_CTX_DATA, (v));
2458 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2459 }
2460
2461
2462 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2463 {
2464 unsigned long flags;
2465 u32 r;
2466
2467 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2468 WREG32(CIK_DIDT_IND_INDEX, (reg));
2469 r = RREG32(CIK_DIDT_IND_DATA);
2470 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2471 return r;
2472 }
2473
2474 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2475 {
2476 unsigned long flags;
2477
2478 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2479 WREG32(CIK_DIDT_IND_INDEX, (reg));
2480 WREG32(CIK_DIDT_IND_DATA, (v));
2481 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2482 }
2483
2484 void r100_pll_errata_after_index(struct radeon_device *rdev);
2485
2486
2487 /*
2488 * ASICs helpers.
2489 */
2490 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2491 (rdev->pdev->device == 0x5969))
2492 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2493 (rdev->family == CHIP_RV200) || \
2494 (rdev->family == CHIP_RS100) || \
2495 (rdev->family == CHIP_RS200) || \
2496 (rdev->family == CHIP_RV250) || \
2497 (rdev->family == CHIP_RV280) || \
2498 (rdev->family == CHIP_RS300))
2499 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2500 (rdev->family == CHIP_RV350) || \
2501 (rdev->family == CHIP_R350) || \
2502 (rdev->family == CHIP_RV380) || \
2503 (rdev->family == CHIP_R420) || \
2504 (rdev->family == CHIP_R423) || \
2505 (rdev->family == CHIP_RV410) || \
2506 (rdev->family == CHIP_RS400) || \
2507 (rdev->family == CHIP_RS480))
2508 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2509 (rdev->ddev->pdev->device == 0x9443) || \
2510 (rdev->ddev->pdev->device == 0x944B) || \
2511 (rdev->ddev->pdev->device == 0x9506) || \
2512 (rdev->ddev->pdev->device == 0x9509) || \
2513 (rdev->ddev->pdev->device == 0x950F) || \
2514 (rdev->ddev->pdev->device == 0x689C) || \
2515 (rdev->ddev->pdev->device == 0x689D))
2516 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2517 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2518 (rdev->family == CHIP_RS690) || \
2519 (rdev->family == CHIP_RS740) || \
2520 (rdev->family >= CHIP_R600))
2521 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2522 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2523 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2524 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2525 (rdev->flags & RADEON_IS_IGP))
2526 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2527 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2528 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2529 (rdev->flags & RADEON_IS_IGP))
2530 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2531 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2532 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2533
2534 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2535 (rdev->ddev->pdev->device == 0x6850) || \
2536 (rdev->ddev->pdev->device == 0x6858) || \
2537 (rdev->ddev->pdev->device == 0x6859) || \
2538 (rdev->ddev->pdev->device == 0x6840) || \
2539 (rdev->ddev->pdev->device == 0x6841) || \
2540 (rdev->ddev->pdev->device == 0x6842) || \
2541 (rdev->ddev->pdev->device == 0x6843))
2542
2543 /*
2544 * BIOS helpers.
2545 */
2546 #define RBIOS8(i) (rdev->bios[i])
2547 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2548 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2549
2550 int radeon_combios_init(struct radeon_device *rdev);
2551 void radeon_combios_fini(struct radeon_device *rdev);
2552 int radeon_atombios_init(struct radeon_device *rdev);
2553 void radeon_atombios_fini(struct radeon_device *rdev);
2554
2555
2556 /*
2557 * RING helpers.
2558 */
2559 #if DRM_DEBUG_CODE == 0
2560 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2561 {
2562 ring->ring[ring->wptr++] = v;
2563 ring->wptr &= ring->ptr_mask;
2564 ring->count_dw--;
2565 ring->ring_free_dw--;
2566 }
2567 #else
2568 /* With debugging this is just too big to inline */
2569 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2570 #endif
2571
2572 /*
2573 * ASICs macro.
2574 */
2575 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2576 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2577 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2578 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2579 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2580 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2581 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2582 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2583 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2584 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2585 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2586 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2587 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2588 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2589 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2590 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2591 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2592 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2593 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2594 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2595 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2596 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2597 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2598 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2599 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2600 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2601 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2602 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2603 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2604 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2605 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2606 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2607 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2608 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2609 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2610 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2611 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2612 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2613 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2614 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2615 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2616 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2617 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2618 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2619 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2620 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2621 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2622 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2623 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2624 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2625 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2626 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2627 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2628 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2629 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2630 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2631 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2632 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2633 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2634 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2635 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2636 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2637 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2638 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2639 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2640 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2641 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2642 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2643 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2644 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2645 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2646 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2647 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2648 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2649 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2650 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2651 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2652 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2653 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2654 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2655 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2656 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2657 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2658
2659 /* Common functions */
2660 /* AGP */
2661 extern int radeon_gpu_reset(struct radeon_device *rdev);
2662 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2663 extern void radeon_agp_disable(struct radeon_device *rdev);
2664 extern int radeon_modeset_init(struct radeon_device *rdev);
2665 extern void radeon_modeset_fini(struct radeon_device *rdev);
2666 extern bool radeon_card_posted(struct radeon_device *rdev);
2667 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2668 extern void radeon_update_display_priority(struct radeon_device *rdev);
2669 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2670 extern void radeon_scratch_init(struct radeon_device *rdev);
2671 extern void radeon_wb_fini(struct radeon_device *rdev);
2672 extern int radeon_wb_init(struct radeon_device *rdev);
2673 extern void radeon_wb_disable(struct radeon_device *rdev);
2674 extern void radeon_surface_init(struct radeon_device *rdev);
2675 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2676 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2677 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2678 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2679 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2680 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2681 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2682 extern int radeon_resume_kms(struct drm_device *dev);
2683 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2684 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2685 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2686 const u32 *registers,
2687 const u32 array_size);
2688
2689 /*
2690 * vm
2691 */
2692 int radeon_vm_manager_init(struct radeon_device *rdev);
2693 void radeon_vm_manager_fini(struct radeon_device *rdev);
2694 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2695 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2696 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2697 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2698 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2699 struct radeon_vm *vm, int ring);
2700 void radeon_vm_fence(struct radeon_device *rdev,
2701 struct radeon_vm *vm,
2702 struct radeon_fence *fence);
2703 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2704 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2705 struct radeon_vm *vm,
2706 struct radeon_bo *bo,
2707 struct ttm_mem_reg *mem);
2708 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2709 struct radeon_bo *bo);
2710 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2711 struct radeon_bo *bo);
2712 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2713 struct radeon_vm *vm,
2714 struct radeon_bo *bo);
2715 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2716 struct radeon_bo_va *bo_va,
2717 uint64_t offset,
2718 uint32_t flags);
2719 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2720 struct radeon_bo_va *bo_va);
2721
2722 /* audio */
2723 void r600_audio_update_hdmi(struct work_struct *work);
2724 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2725 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2726 void r600_audio_enable(struct radeon_device *rdev,
2727 struct r600_audio_pin *pin,
2728 bool enable);
2729 void dce6_audio_enable(struct radeon_device *rdev,
2730 struct r600_audio_pin *pin,
2731 bool enable);
2732
2733 /*
2734 * R600 vram scratch functions
2735 */
2736 int r600_vram_scratch_init(struct radeon_device *rdev);
2737 void r600_vram_scratch_fini(struct radeon_device *rdev);
2738
2739 /*
2740 * r600 cs checking helper
2741 */
2742 unsigned r600_mip_minify(unsigned size, unsigned level);
2743 bool r600_fmt_is_valid_color(u32 format);
2744 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2745 int r600_fmt_get_blocksize(u32 format);
2746 int r600_fmt_get_nblocksx(u32 format, u32 w);
2747 int r600_fmt_get_nblocksy(u32 format, u32 h);
2748
2749 /*
2750 * r600 functions used by radeon_encoder.c
2751 */
2752 struct radeon_hdmi_acr {
2753 u32 clock;
2754
2755 int n_32khz;
2756 int cts_32khz;
2757
2758 int n_44_1khz;
2759 int cts_44_1khz;
2760
2761 int n_48khz;
2762 int cts_48khz;
2763
2764 };
2765
2766 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2767
2768 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2769 u32 tiling_pipe_num,
2770 u32 max_rb_num,
2771 u32 total_max_rb_num,
2772 u32 enabled_rb_mask);
2773
2774 /*
2775 * evergreen functions used by radeon_encoder.c
2776 */
2777
2778 extern int ni_init_microcode(struct radeon_device *rdev);
2779 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2780
2781 /* radeon_acpi.c */
2782 #if defined(CONFIG_ACPI)
2783 extern int radeon_acpi_init(struct radeon_device *rdev);
2784 extern void radeon_acpi_fini(struct radeon_device *rdev);
2785 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2786 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2787 u8 perf_req, bool advertise);
2788 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2789 #else
2790 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2791 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2792 #endif
2793
2794 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2795 struct radeon_cs_packet *pkt,
2796 unsigned idx);
2797 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2798 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2799 struct radeon_cs_packet *pkt);
2800 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2801 struct radeon_cs_reloc **cs_reloc,
2802 int nomm);
2803 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2804 uint32_t *vline_start_end,
2805 uint32_t *vline_status);
2806
2807 #include "radeon_object.h"
2808
2809 #endif
Linux with added FPC-III support