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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_pm.c
blob10fc97749a81c587fa1d763eb2a8426d1a3a30c7
1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23 #include <drm/drmP.h>
24 #include "radeon.h"
25 #include "avivod.h"
26 #include "atom.h"
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
30
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34
35 static const char *radeon_pm_state_type_name[5] = {
36 "",
37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41 };
42
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53 {
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66 }
67
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
69 {
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->asic->dpm.enable_bapm)
77 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 mutex_unlock(&rdev->pm.mutex);
79 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80 if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 mutex_lock(&rdev->pm.mutex);
82 radeon_pm_update_profile(rdev);
83 radeon_pm_set_clocks(rdev);
84 mutex_unlock(&rdev->pm.mutex);
85 }
86 }
87 }
88
89 static void radeon_pm_update_profile(struct radeon_device *rdev)
90 {
91 switch (rdev->pm.profile) {
92 case PM_PROFILE_DEFAULT:
93 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
94 break;
95 case PM_PROFILE_AUTO:
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
99 else
100 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
101 } else {
102 if (rdev->pm.active_crtc_count > 1)
103 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
104 else
105 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
106 }
107 break;
108 case PM_PROFILE_LOW:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
113 break;
114 case PM_PROFILE_MID:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
119 break;
120 case PM_PROFILE_HIGH:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
123 else
124 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
125 break;
126 }
127
128 if (rdev->pm.active_crtc_count == 0) {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
133 } else {
134 rdev->pm.requested_power_state_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 rdev->pm.requested_clock_mode_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
138 }
139 }
140
141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
142 {
143 struct radeon_bo *bo, *n;
144
145 if (list_empty(&rdev->gem.objects))
146 return;
147
148 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 ttm_bo_unmap_virtual(&bo->tbo);
151 }
152 }
153
154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
155 {
156 if (rdev->pm.active_crtcs) {
157 rdev->pm.vblank_sync = false;
158 wait_event_timeout(
159 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
161 }
162 }
163
164 static void radeon_set_power_state(struct radeon_device *rdev)
165 {
166 u32 sclk, mclk;
167 bool misc_after = false;
168
169 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
171 return;
172
173 if (radeon_gui_idle(rdev)) {
174 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].sclk;
176 if (sclk > rdev->pm.default_sclk)
177 sclk = rdev->pm.default_sclk;
178
179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
181 * mclk and vddci.
182 */
183 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 (rdev->family >= CHIP_BARTS) &&
185 rdev->pm.active_crtc_count &&
186 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
190 else
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
193
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
196
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
200
201 radeon_sync_with_vblank(rdev);
202
203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 if (!radeon_pm_in_vbl(rdev))
205 return;
206 }
207
208 radeon_pm_prepare(rdev);
209
210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
221 }
222
223 /* set memory clock */
224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
230 }
231
232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
242 }
243
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
245 {
246 int i, r;
247
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
253 mutex_lock(&rdev->ddev->struct_mutex);
254 down_write(&rdev->pm.mclk_lock);
255 mutex_lock(&rdev->ring_lock);
256
257 /* wait for the rings to drain */
258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 struct radeon_ring *ring = &rdev->ring[i];
260 if (!ring->ready) {
261 continue;
262 }
263 r = radeon_fence_wait_empty_locked(rdev, i);
264 if (r) {
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev->ring_lock);
267 up_write(&rdev->pm.mclk_lock);
268 mutex_unlock(&rdev->ddev->struct_mutex);
269 return;
270 }
271 }
272
273 radeon_unmap_vram_bos(rdev);
274
275 if (rdev->irq.installed) {
276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.active_crtcs & (1 << i)) {
278 rdev->pm.req_vblank |= (1 << i);
279 drm_vblank_get(rdev->ddev, i);
280 }
281 }
282 }
283
284 radeon_set_power_state(rdev);
285
286 if (rdev->irq.installed) {
287 for (i = 0; i < rdev->num_crtc; i++) {
288 if (rdev->pm.req_vblank & (1 << i)) {
289 rdev->pm.req_vblank &= ~(1 << i);
290 drm_vblank_put(rdev->ddev, i);
291 }
292 }
293 }
294
295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev);
297 if (rdev->pm.active_crtc_count)
298 radeon_bandwidth_update(rdev);
299
300 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
301
302 mutex_unlock(&rdev->ring_lock);
303 up_write(&rdev->pm.mclk_lock);
304 mutex_unlock(&rdev->ddev->struct_mutex);
305 }
306
307 static void radeon_pm_print_states(struct radeon_device *rdev)
308 {
309 int i, j;
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
312
313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
319 DRM_DEBUG_DRIVER("\tDefault");
320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
329 j,
330 clock_info->sclk * 10);
331 else
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
333 j,
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
337 }
338 }
339 }
340
341 static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
343 char *buf)
344 {
345 struct drm_device *ddev = dev_get_drvdata(dev);
346 struct radeon_device *rdev = ddev->dev_private;
347 int cp = rdev->pm.profile;
348
349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
352 (cp == PM_PROFILE_MID) ? "mid" :
353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
354 }
355
356 static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 const char *buf,
359 size_t count)
360 {
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct radeon_device *rdev = ddev->dev_private;
363
364 mutex_lock(&rdev->pm.mutex);
365 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
366 if (strncmp("default", buf, strlen("default")) == 0)
367 rdev->pm.profile = PM_PROFILE_DEFAULT;
368 else if (strncmp("auto", buf, strlen("auto")) == 0)
369 rdev->pm.profile = PM_PROFILE_AUTO;
370 else if (strncmp("low", buf, strlen("low")) == 0)
371 rdev->pm.profile = PM_PROFILE_LOW;
372 else if (strncmp("mid", buf, strlen("mid")) == 0)
373 rdev->pm.profile = PM_PROFILE_MID;
374 else if (strncmp("high", buf, strlen("high")) == 0)
375 rdev->pm.profile = PM_PROFILE_HIGH;
376 else {
377 count = -EINVAL;
378 goto fail;
379 }
380 radeon_pm_update_profile(rdev);
381 radeon_pm_set_clocks(rdev);
382 } else
383 count = -EINVAL;
384
385 fail:
386 mutex_unlock(&rdev->pm.mutex);
387
388 return count;
389 }
390
391 static ssize_t radeon_get_pm_method(struct device *dev,
392 struct device_attribute *attr,
393 char *buf)
394 {
395 struct drm_device *ddev = dev_get_drvdata(dev);
396 struct radeon_device *rdev = ddev->dev_private;
397 int pm = rdev->pm.pm_method;
398
399 return snprintf(buf, PAGE_SIZE, "%s\n",
400 (pm == PM_METHOD_DYNPM) ? "dynpm" :
401 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
402 }
403
404 static ssize_t radeon_set_pm_method(struct device *dev,
405 struct device_attribute *attr,
406 const char *buf,
407 size_t count)
408 {
409 struct drm_device *ddev = dev_get_drvdata(dev);
410 struct radeon_device *rdev = ddev->dev_private;
411
412 /* we don't support the legacy modes with dpm */
413 if (rdev->pm.pm_method == PM_METHOD_DPM) {
414 count = -EINVAL;
415 goto fail;
416 }
417
418 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
419 mutex_lock(&rdev->pm.mutex);
420 rdev->pm.pm_method = PM_METHOD_DYNPM;
421 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
422 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
423 mutex_unlock(&rdev->pm.mutex);
424 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
425 mutex_lock(&rdev->pm.mutex);
426 /* disable dynpm */
427 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
428 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
429 rdev->pm.pm_method = PM_METHOD_PROFILE;
430 mutex_unlock(&rdev->pm.mutex);
431 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
432 } else {
433 count = -EINVAL;
434 goto fail;
435 }
436 radeon_pm_compute_clocks(rdev);
437 fail:
438 return count;
439 }
440
441 static ssize_t radeon_get_dpm_state(struct device *dev,
442 struct device_attribute *attr,
443 char *buf)
444 {
445 struct drm_device *ddev = dev_get_drvdata(dev);
446 struct radeon_device *rdev = ddev->dev_private;
447 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
448
449 return snprintf(buf, PAGE_SIZE, "%s\n",
450 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
451 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
452 }
453
454 static ssize_t radeon_set_dpm_state(struct device *dev,
455 struct device_attribute *attr,
456 const char *buf,
457 size_t count)
458 {
459 struct drm_device *ddev = dev_get_drvdata(dev);
460 struct radeon_device *rdev = ddev->dev_private;
461
462 mutex_lock(&rdev->pm.mutex);
463 if (strncmp("battery", buf, strlen("battery")) == 0)
464 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
465 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
466 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
467 else if (strncmp("performance", buf, strlen("performance")) == 0)
468 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
469 else {
470 mutex_unlock(&rdev->pm.mutex);
471 count = -EINVAL;
472 goto fail;
473 }
474 mutex_unlock(&rdev->pm.mutex);
475 radeon_pm_compute_clocks(rdev);
476 fail:
477 return count;
478 }
479
480 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
481 struct device_attribute *attr,
482 char *buf)
483 {
484 struct drm_device *ddev = dev_get_drvdata(dev);
485 struct radeon_device *rdev = ddev->dev_private;
486 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
487
488 return snprintf(buf, PAGE_SIZE, "%s\n",
489 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
490 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
491 }
492
493 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
494 struct device_attribute *attr,
495 const char *buf,
496 size_t count)
497 {
498 struct drm_device *ddev = dev_get_drvdata(dev);
499 struct radeon_device *rdev = ddev->dev_private;
500 enum radeon_dpm_forced_level level;
501 int ret = 0;
502
503 mutex_lock(&rdev->pm.mutex);
504 if (strncmp("low", buf, strlen("low")) == 0) {
505 level = RADEON_DPM_FORCED_LEVEL_LOW;
506 } else if (strncmp("high", buf, strlen("high")) == 0) {
507 level = RADEON_DPM_FORCED_LEVEL_HIGH;
508 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
509 level = RADEON_DPM_FORCED_LEVEL_AUTO;
510 } else {
511 mutex_unlock(&rdev->pm.mutex);
512 count = -EINVAL;
513 goto fail;
514 }
515 if (rdev->asic->dpm.force_performance_level) {
516 ret = radeon_dpm_force_performance_level(rdev, level);
517 if (ret)
518 count = -EINVAL;
519 }
520 mutex_unlock(&rdev->pm.mutex);
521 fail:
522 return count;
523 }
524
525 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
526 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
527 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
528 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
529 radeon_get_dpm_forced_performance_level,
530 radeon_set_dpm_forced_performance_level);
531
532 static ssize_t radeon_hwmon_show_temp(struct device *dev,
533 struct device_attribute *attr,
534 char *buf)
535 {
536 struct drm_device *ddev = dev_get_drvdata(dev);
537 struct radeon_device *rdev = ddev->dev_private;
538 int temp;
539
540 if (rdev->asic->pm.get_temperature)
541 temp = radeon_get_temperature(rdev);
542 else
543 temp = 0;
544
545 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
546 }
547
548 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
549 struct device_attribute *attr,
550 char *buf)
551 {
552 struct drm_device *ddev = dev_get_drvdata(dev);
553 struct radeon_device *rdev = ddev->dev_private;
554 int hyst = to_sensor_dev_attr(attr)->index;
555 int temp;
556
557 if (hyst)
558 temp = rdev->pm.dpm.thermal.min_temp;
559 else
560 temp = rdev->pm.dpm.thermal.max_temp;
561
562 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
563 }
564
565 static ssize_t radeon_hwmon_show_name(struct device *dev,
566 struct device_attribute *attr,
567 char *buf)
568 {
569 return sprintf(buf, "radeon\n");
570 }
571
572 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
573 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
574 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
575 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
576
577 static struct attribute *hwmon_attributes[] = {
578 &sensor_dev_attr_temp1_input.dev_attr.attr,
579 &sensor_dev_attr_temp1_crit.dev_attr.attr,
580 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
581 &sensor_dev_attr_name.dev_attr.attr,
582 NULL
583 };
584
585 static umode_t hwmon_attributes_visible(struct kobject *kobj,
586 struct attribute *attr, int index)
587 {
588 struct device *dev = container_of(kobj, struct device, kobj);
589 struct drm_device *ddev = dev_get_drvdata(dev);
590 struct radeon_device *rdev = ddev->dev_private;
591
592 /* Skip limit attributes if DPM is not enabled */
593 if (rdev->pm.pm_method != PM_METHOD_DPM &&
594 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
595 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
596 return 0;
597
598 return attr->mode;
599 }
600
601 static const struct attribute_group hwmon_attrgroup = {
602 .attrs = hwmon_attributes,
603 .is_visible = hwmon_attributes_visible,
604 };
605
606 static int radeon_hwmon_init(struct radeon_device *rdev)
607 {
608 int err = 0;
609
610 rdev->pm.int_hwmon_dev = NULL;
611
612 switch (rdev->pm.int_thermal_type) {
613 case THERMAL_TYPE_RV6XX:
614 case THERMAL_TYPE_RV770:
615 case THERMAL_TYPE_EVERGREEN:
616 case THERMAL_TYPE_NI:
617 case THERMAL_TYPE_SUMO:
618 case THERMAL_TYPE_SI:
619 case THERMAL_TYPE_CI:
620 case THERMAL_TYPE_KV:
621 if (rdev->asic->pm.get_temperature == NULL)
622 return err;
623 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
624 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
625 err = PTR_ERR(rdev->pm.int_hwmon_dev);
626 dev_err(rdev->dev,
627 "Unable to register hwmon device: %d\n", err);
628 break;
629 }
630 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
631 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
632 &hwmon_attrgroup);
633 if (err) {
634 dev_err(rdev->dev,
635 "Unable to create hwmon sysfs file: %d\n", err);
636 hwmon_device_unregister(rdev->dev);
637 }
638 break;
639 default:
640 break;
641 }
642
643 return err;
644 }
645
646 static void radeon_hwmon_fini(struct radeon_device *rdev)
647 {
648 if (rdev->pm.int_hwmon_dev) {
649 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
650 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
651 }
652 }
653
654 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
655 {
656 struct radeon_device *rdev =
657 container_of(work, struct radeon_device,
658 pm.dpm.thermal.work);
659 /* switch to the thermal state */
660 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
661
662 if (!rdev->pm.dpm_enabled)
663 return;
664
665 if (rdev->asic->pm.get_temperature) {
666 int temp = radeon_get_temperature(rdev);
667
668 if (temp < rdev->pm.dpm.thermal.min_temp)
669 /* switch back the user state */
670 dpm_state = rdev->pm.dpm.user_state;
671 } else {
672 if (rdev->pm.dpm.thermal.high_to_low)
673 /* switch back the user state */
674 dpm_state = rdev->pm.dpm.user_state;
675 }
676 mutex_lock(&rdev->pm.mutex);
677 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
678 rdev->pm.dpm.thermal_active = true;
679 else
680 rdev->pm.dpm.thermal_active = false;
681 rdev->pm.dpm.state = dpm_state;
682 mutex_unlock(&rdev->pm.mutex);
683
684 radeon_pm_compute_clocks(rdev);
685 }
686
687 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
688 enum radeon_pm_state_type dpm_state)
689 {
690 int i;
691 struct radeon_ps *ps;
692 u32 ui_class;
693 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
694 true : false;
695
696 /* check if the vblank period is too short to adjust the mclk */
697 if (single_display && rdev->asic->dpm.vblank_too_short) {
698 if (radeon_dpm_vblank_too_short(rdev))
699 single_display = false;
700 }
701
702 /* certain older asics have a separare 3D performance state,
703 * so try that first if the user selected performance
704 */
705 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
706 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
707 /* balanced states don't exist at the moment */
708 if (dpm_state == POWER_STATE_TYPE_BALANCED)
709 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
710
711 restart_search:
712 /* Pick the best power state based on current conditions */
713 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
714 ps = &rdev->pm.dpm.ps[i];
715 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
716 switch (dpm_state) {
717 /* user states */
718 case POWER_STATE_TYPE_BATTERY:
719 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
720 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
721 if (single_display)
722 return ps;
723 } else
724 return ps;
725 }
726 break;
727 case POWER_STATE_TYPE_BALANCED:
728 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
729 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
730 if (single_display)
731 return ps;
732 } else
733 return ps;
734 }
735 break;
736 case POWER_STATE_TYPE_PERFORMANCE:
737 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
738 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
739 if (single_display)
740 return ps;
741 } else
742 return ps;
743 }
744 break;
745 /* internal states */
746 case POWER_STATE_TYPE_INTERNAL_UVD:
747 if (rdev->pm.dpm.uvd_ps)
748 return rdev->pm.dpm.uvd_ps;
749 else
750 break;
751 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
752 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
753 return ps;
754 break;
755 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
756 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
757 return ps;
758 break;
759 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
760 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
761 return ps;
762 break;
763 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
764 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
765 return ps;
766 break;
767 case POWER_STATE_TYPE_INTERNAL_BOOT:
768 return rdev->pm.dpm.boot_ps;
769 case POWER_STATE_TYPE_INTERNAL_THERMAL:
770 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
771 return ps;
772 break;
773 case POWER_STATE_TYPE_INTERNAL_ACPI:
774 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
775 return ps;
776 break;
777 case POWER_STATE_TYPE_INTERNAL_ULV:
778 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
779 return ps;
780 break;
781 case POWER_STATE_TYPE_INTERNAL_3DPERF:
782 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
783 return ps;
784 break;
785 default:
786 break;
787 }
788 }
789 /* use a fallback state if we didn't match */
790 switch (dpm_state) {
791 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
792 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
793 goto restart_search;
794 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
795 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
796 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
797 if (rdev->pm.dpm.uvd_ps) {
798 return rdev->pm.dpm.uvd_ps;
799 } else {
800 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
801 goto restart_search;
802 }
803 case POWER_STATE_TYPE_INTERNAL_THERMAL:
804 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
805 goto restart_search;
806 case POWER_STATE_TYPE_INTERNAL_ACPI:
807 dpm_state = POWER_STATE_TYPE_BATTERY;
808 goto restart_search;
809 case POWER_STATE_TYPE_BATTERY:
810 case POWER_STATE_TYPE_BALANCED:
811 case POWER_STATE_TYPE_INTERNAL_3DPERF:
812 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
813 goto restart_search;
814 default:
815 break;
816 }
817
818 return NULL;
819 }
820
821 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
822 {
823 int i;
824 struct radeon_ps *ps;
825 enum radeon_pm_state_type dpm_state;
826 int ret;
827
828 /* if dpm init failed */
829 if (!rdev->pm.dpm_enabled)
830 return;
831
832 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
833 /* add other state override checks here */
834 if ((!rdev->pm.dpm.thermal_active) &&
835 (!rdev->pm.dpm.uvd_active))
836 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
837 }
838 dpm_state = rdev->pm.dpm.state;
839
840 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
841 if (ps)
842 rdev->pm.dpm.requested_ps = ps;
843 else
844 return;
845
846 /* no need to reprogram if nothing changed unless we are on BTC+ */
847 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
848 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
849 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
850 * all we need to do is update the display configuration.
851 */
852 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
853 /* update display watermarks based on new power state */
854 radeon_bandwidth_update(rdev);
855 /* update displays */
856 radeon_dpm_display_configuration_changed(rdev);
857 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
858 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
859 }
860 return;
861 } else {
862 /* for BTC+ if the num crtcs hasn't changed and state is the same,
863 * nothing to do, if the num crtcs is > 1 and state is the same,
864 * update display configuration.
865 */
866 if (rdev->pm.dpm.new_active_crtcs ==
867 rdev->pm.dpm.current_active_crtcs) {
868 return;
869 } else {
870 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
871 (rdev->pm.dpm.new_active_crtc_count > 1)) {
872 /* update display watermarks based on new power state */
873 radeon_bandwidth_update(rdev);
874 /* update displays */
875 radeon_dpm_display_configuration_changed(rdev);
876 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
877 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
878 return;
879 }
880 }
881 }
882 }
883
884 printk("switching from power state:\n");
885 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
886 printk("switching to power state:\n");
887 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
888
889 mutex_lock(&rdev->ddev->struct_mutex);
890 down_write(&rdev->pm.mclk_lock);
891 mutex_lock(&rdev->ring_lock);
892
893 ret = radeon_dpm_pre_set_power_state(rdev);
894 if (ret)
895 goto done;
896
897 /* update display watermarks based on new power state */
898 radeon_bandwidth_update(rdev);
899 /* update displays */
900 radeon_dpm_display_configuration_changed(rdev);
901
902 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
903 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
904
905 /* wait for the rings to drain */
906 for (i = 0; i < RADEON_NUM_RINGS; i++) {
907 struct radeon_ring *ring = &rdev->ring[i];
908 if (ring->ready)
909 radeon_fence_wait_empty_locked(rdev, i);
910 }
911
912 /* program the new power state */
913 radeon_dpm_set_power_state(rdev);
914
915 /* update current power state */
916 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
917
918 radeon_dpm_post_set_power_state(rdev);
919
920 if (rdev->asic->dpm.force_performance_level) {
921 if (rdev->pm.dpm.thermal_active)
922 /* force low perf level for thermal */
923 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
924 else
925 /* otherwise, enable auto */
926 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
927 }
928
929 done:
930 mutex_unlock(&rdev->ring_lock);
931 up_write(&rdev->pm.mclk_lock);
932 mutex_unlock(&rdev->ddev->struct_mutex);
933 }
934
935 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
936 {
937 enum radeon_pm_state_type dpm_state;
938
939 if (rdev->asic->dpm.powergate_uvd) {
940 mutex_lock(&rdev->pm.mutex);
941 /* enable/disable UVD */
942 radeon_dpm_powergate_uvd(rdev, !enable);
943 mutex_unlock(&rdev->pm.mutex);
944 } else {
945 if (enable) {
946 mutex_lock(&rdev->pm.mutex);
947 rdev->pm.dpm.uvd_active = true;
948 /* disable this for now */
949 #if 0
950 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
951 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
952 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
953 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
954 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
956 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
957 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
958 else
959 #endif
960 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
961 rdev->pm.dpm.state = dpm_state;
962 mutex_unlock(&rdev->pm.mutex);
963 } else {
964 mutex_lock(&rdev->pm.mutex);
965 rdev->pm.dpm.uvd_active = false;
966 mutex_unlock(&rdev->pm.mutex);
967 }
968
969 radeon_pm_compute_clocks(rdev);
970 }
971 }
972
973 static void radeon_pm_suspend_old(struct radeon_device *rdev)
974 {
975 mutex_lock(&rdev->pm.mutex);
976 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
977 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
978 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
979 }
980 mutex_unlock(&rdev->pm.mutex);
981
982 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
983 }
984
985 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
986 {
987 mutex_lock(&rdev->pm.mutex);
988 /* disable dpm */
989 radeon_dpm_disable(rdev);
990 /* reset the power state */
991 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
992 rdev->pm.dpm_enabled = false;
993 mutex_unlock(&rdev->pm.mutex);
994 }
995
996 void radeon_pm_suspend(struct radeon_device *rdev)
997 {
998 if (rdev->pm.pm_method == PM_METHOD_DPM)
999 radeon_pm_suspend_dpm(rdev);
1000 else
1001 radeon_pm_suspend_old(rdev);
1002 }
1003
1004 static void radeon_pm_resume_old(struct radeon_device *rdev)
1005 {
1006 /* set up the default clocks if the MC ucode is loaded */
1007 if ((rdev->family >= CHIP_BARTS) &&
1008 (rdev->family <= CHIP_CAYMAN) &&
1009 rdev->mc_fw) {
1010 if (rdev->pm.default_vddc)
1011 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1012 SET_VOLTAGE_TYPE_ASIC_VDDC);
1013 if (rdev->pm.default_vddci)
1014 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1015 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1016 if (rdev->pm.default_sclk)
1017 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1018 if (rdev->pm.default_mclk)
1019 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1020 }
1021 /* asic init will reset the default power state */
1022 mutex_lock(&rdev->pm.mutex);
1023 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1024 rdev->pm.current_clock_mode_index = 0;
1025 rdev->pm.current_sclk = rdev->pm.default_sclk;
1026 rdev->pm.current_mclk = rdev->pm.default_mclk;
1027 if (rdev->pm.power_state) {
1028 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1029 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1030 }
1031 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1032 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1033 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1034 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1035 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1036 }
1037 mutex_unlock(&rdev->pm.mutex);
1038 radeon_pm_compute_clocks(rdev);
1039 }
1040
1041 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1042 {
1043 int ret;
1044
1045 /* asic init will reset to the boot state */
1046 mutex_lock(&rdev->pm.mutex);
1047 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1048 radeon_dpm_setup_asic(rdev);
1049 ret = radeon_dpm_enable(rdev);
1050 mutex_unlock(&rdev->pm.mutex);
1051 if (ret) {
1052 DRM_ERROR("radeon: dpm resume failed\n");
1053 if ((rdev->family >= CHIP_BARTS) &&
1054 (rdev->family <= CHIP_CAYMAN) &&
1055 rdev->mc_fw) {
1056 if (rdev->pm.default_vddc)
1057 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1058 SET_VOLTAGE_TYPE_ASIC_VDDC);
1059 if (rdev->pm.default_vddci)
1060 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1061 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1062 if (rdev->pm.default_sclk)
1063 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1064 if (rdev->pm.default_mclk)
1065 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1066 }
1067 } else {
1068 rdev->pm.dpm_enabled = true;
1069 radeon_pm_compute_clocks(rdev);
1070 }
1071 }
1072
1073 void radeon_pm_resume(struct radeon_device *rdev)
1074 {
1075 if (rdev->pm.pm_method == PM_METHOD_DPM)
1076 radeon_pm_resume_dpm(rdev);
1077 else
1078 radeon_pm_resume_old(rdev);
1079 }
1080
1081 static int radeon_pm_init_old(struct radeon_device *rdev)
1082 {
1083 int ret;
1084
1085 rdev->pm.profile = PM_PROFILE_DEFAULT;
1086 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1087 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1088 rdev->pm.dynpm_can_upclock = true;
1089 rdev->pm.dynpm_can_downclock = true;
1090 rdev->pm.default_sclk = rdev->clock.default_sclk;
1091 rdev->pm.default_mclk = rdev->clock.default_mclk;
1092 rdev->pm.current_sclk = rdev->clock.default_sclk;
1093 rdev->pm.current_mclk = rdev->clock.default_mclk;
1094 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1095
1096 if (rdev->bios) {
1097 if (rdev->is_atom_bios)
1098 radeon_atombios_get_power_modes(rdev);
1099 else
1100 radeon_combios_get_power_modes(rdev);
1101 radeon_pm_print_states(rdev);
1102 radeon_pm_init_profile(rdev);
1103 /* set up the default clocks if the MC ucode is loaded */
1104 if ((rdev->family >= CHIP_BARTS) &&
1105 (rdev->family <= CHIP_CAYMAN) &&
1106 rdev->mc_fw) {
1107 if (rdev->pm.default_vddc)
1108 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1109 SET_VOLTAGE_TYPE_ASIC_VDDC);
1110 if (rdev->pm.default_vddci)
1111 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1112 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1113 if (rdev->pm.default_sclk)
1114 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1115 if (rdev->pm.default_mclk)
1116 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1117 }
1118 }
1119
1120 /* set up the internal thermal sensor if applicable */
1121 ret = radeon_hwmon_init(rdev);
1122 if (ret)
1123 return ret;
1124
1125 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1126
1127 if (rdev->pm.num_power_states > 1) {
1128 /* where's the best place to put these? */
1129 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1130 if (ret)
1131 DRM_ERROR("failed to create device file for power profile\n");
1132 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1133 if (ret)
1134 DRM_ERROR("failed to create device file for power method\n");
1135
1136 if (radeon_debugfs_pm_init(rdev)) {
1137 DRM_ERROR("Failed to register debugfs file for PM!\n");
1138 }
1139
1140 DRM_INFO("radeon: power management initialized\n");
1141 }
1142
1143 return 0;
1144 }
1145
1146 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1147 {
1148 int i;
1149
1150 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1151 printk("== power state %d ==\n", i);
1152 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1153 }
1154 }
1155
1156 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1157 {
1158 int ret;
1159
1160 /* default to balanced state */
1161 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1162 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1163 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1164 rdev->pm.default_sclk = rdev->clock.default_sclk;
1165 rdev->pm.default_mclk = rdev->clock.default_mclk;
1166 rdev->pm.current_sclk = rdev->clock.default_sclk;
1167 rdev->pm.current_mclk = rdev->clock.default_mclk;
1168 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1169
1170 if (rdev->bios && rdev->is_atom_bios)
1171 radeon_atombios_get_power_modes(rdev);
1172 else
1173 return -EINVAL;
1174
1175 /* set up the internal thermal sensor if applicable */
1176 ret = radeon_hwmon_init(rdev);
1177 if (ret)
1178 return ret;
1179
1180 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1181 mutex_lock(&rdev->pm.mutex);
1182 radeon_dpm_init(rdev);
1183 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1184 radeon_dpm_print_power_states(rdev);
1185 radeon_dpm_setup_asic(rdev);
1186 ret = radeon_dpm_enable(rdev);
1187 mutex_unlock(&rdev->pm.mutex);
1188 if (ret) {
1189 rdev->pm.dpm_enabled = false;
1190 if ((rdev->family >= CHIP_BARTS) &&
1191 (rdev->family <= CHIP_CAYMAN) &&
1192 rdev->mc_fw) {
1193 if (rdev->pm.default_vddc)
1194 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1195 SET_VOLTAGE_TYPE_ASIC_VDDC);
1196 if (rdev->pm.default_vddci)
1197 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1198 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1199 if (rdev->pm.default_sclk)
1200 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1201 if (rdev->pm.default_mclk)
1202 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1203 }
1204 DRM_ERROR("radeon: dpm initialization failed\n");
1205 return ret;
1206 }
1207 rdev->pm.dpm_enabled = true;
1208 radeon_pm_compute_clocks(rdev);
1209
1210 if (rdev->pm.num_power_states > 1) {
1211 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1212 if (ret)
1213 DRM_ERROR("failed to create device file for dpm state\n");
1214 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1215 if (ret)
1216 DRM_ERROR("failed to create device file for dpm state\n");
1217 /* XXX: these are noops for dpm but are here for backwards compat */
1218 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1219 if (ret)
1220 DRM_ERROR("failed to create device file for power profile\n");
1221 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1222 if (ret)
1223 DRM_ERROR("failed to create device file for power method\n");
1224
1225 if (radeon_debugfs_pm_init(rdev)) {
1226 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1227 }
1228
1229 DRM_INFO("radeon: dpm initialized\n");
1230 }
1231
1232 return 0;
1233 }
1234
1235 int radeon_pm_init(struct radeon_device *rdev)
1236 {
1237 /* enable dpm on rv6xx+ */
1238 switch (rdev->family) {
1239 case CHIP_RV610:
1240 case CHIP_RV630:
1241 case CHIP_RV620:
1242 case CHIP_RV635:
1243 case CHIP_RV670:
1244 case CHIP_RS780:
1245 case CHIP_RS880:
1246 case CHIP_RV770:
1247 case CHIP_RV730:
1248 case CHIP_RV710:
1249 case CHIP_RV740:
1250 case CHIP_CEDAR:
1251 case CHIP_REDWOOD:
1252 case CHIP_JUNIPER:
1253 case CHIP_CYPRESS:
1254 case CHIP_HEMLOCK:
1255 case CHIP_PALM:
1256 case CHIP_SUMO:
1257 case CHIP_SUMO2:
1258 case CHIP_BARTS:
1259 case CHIP_TURKS:
1260 case CHIP_CAICOS:
1261 case CHIP_CAYMAN:
1262 case CHIP_ARUBA:
1263 case CHIP_TAHITI:
1264 case CHIP_PITCAIRN:
1265 case CHIP_VERDE:
1266 case CHIP_OLAND:
1267 case CHIP_HAINAN:
1268 case CHIP_BONAIRE:
1269 case CHIP_KABINI:
1270 case CHIP_KAVERI:
1271 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1272 if (!rdev->rlc_fw)
1273 rdev->pm.pm_method = PM_METHOD_PROFILE;
1274 else if ((rdev->family >= CHIP_RV770) &&
1275 (!(rdev->flags & RADEON_IS_IGP)) &&
1276 (!rdev->smc_fw))
1277 rdev->pm.pm_method = PM_METHOD_PROFILE;
1278 else if (radeon_dpm == 1)
1279 rdev->pm.pm_method = PM_METHOD_DPM;
1280 else
1281 rdev->pm.pm_method = PM_METHOD_PROFILE;
1282 break;
1283 default:
1284 /* default to profile method */
1285 rdev->pm.pm_method = PM_METHOD_PROFILE;
1286 break;
1287 }
1288
1289 if (rdev->pm.pm_method == PM_METHOD_DPM)
1290 return radeon_pm_init_dpm(rdev);
1291 else
1292 return radeon_pm_init_old(rdev);
1293 }
1294
1295 static void radeon_pm_fini_old(struct radeon_device *rdev)
1296 {
1297 if (rdev->pm.num_power_states > 1) {
1298 mutex_lock(&rdev->pm.mutex);
1299 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1300 rdev->pm.profile = PM_PROFILE_DEFAULT;
1301 radeon_pm_update_profile(rdev);
1302 radeon_pm_set_clocks(rdev);
1303 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1304 /* reset default clocks */
1305 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1306 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1307 radeon_pm_set_clocks(rdev);
1308 }
1309 mutex_unlock(&rdev->pm.mutex);
1310
1311 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1312
1313 device_remove_file(rdev->dev, &dev_attr_power_profile);
1314 device_remove_file(rdev->dev, &dev_attr_power_method);
1315 }
1316
1317 if (rdev->pm.power_state)
1318 kfree(rdev->pm.power_state);
1319
1320 radeon_hwmon_fini(rdev);
1321 }
1322
1323 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1324 {
1325 if (rdev->pm.num_power_states > 1) {
1326 mutex_lock(&rdev->pm.mutex);
1327 radeon_dpm_disable(rdev);
1328 mutex_unlock(&rdev->pm.mutex);
1329
1330 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1331 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1332 /* XXX backwards compat */
1333 device_remove_file(rdev->dev, &dev_attr_power_profile);
1334 device_remove_file(rdev->dev, &dev_attr_power_method);
1335 }
1336 radeon_dpm_fini(rdev);
1337
1338 if (rdev->pm.power_state)
1339 kfree(rdev->pm.power_state);
1340
1341 radeon_hwmon_fini(rdev);
1342 }
1343
1344 void radeon_pm_fini(struct radeon_device *rdev)
1345 {
1346 if (rdev->pm.pm_method == PM_METHOD_DPM)
1347 radeon_pm_fini_dpm(rdev);
1348 else
1349 radeon_pm_fini_old(rdev);
1350 }
1351
1352 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1353 {
1354 struct drm_device *ddev = rdev->ddev;
1355 struct drm_crtc *crtc;
1356 struct radeon_crtc *radeon_crtc;
1357
1358 if (rdev->pm.num_power_states < 2)
1359 return;
1360
1361 mutex_lock(&rdev->pm.mutex);
1362
1363 rdev->pm.active_crtcs = 0;
1364 rdev->pm.active_crtc_count = 0;
1365 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1366 list_for_each_entry(crtc,
1367 &ddev->mode_config.crtc_list, head) {
1368 radeon_crtc = to_radeon_crtc(crtc);
1369 if (radeon_crtc->enabled) {
1370 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1371 rdev->pm.active_crtc_count++;
1372 }
1373 }
1374 }
1375
1376 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1377 radeon_pm_update_profile(rdev);
1378 radeon_pm_set_clocks(rdev);
1379 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1380 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1381 if (rdev->pm.active_crtc_count > 1) {
1382 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1383 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1384
1385 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1386 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1387 radeon_pm_get_dynpm_state(rdev);
1388 radeon_pm_set_clocks(rdev);
1389
1390 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1391 }
1392 } else if (rdev->pm.active_crtc_count == 1) {
1393 /* TODO: Increase clocks if needed for current mode */
1394
1395 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1396 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1397 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1398 radeon_pm_get_dynpm_state(rdev);
1399 radeon_pm_set_clocks(rdev);
1400
1401 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1402 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1403 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1404 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1405 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1406 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1407 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1408 }
1409 } else { /* count == 0 */
1410 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1411 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1412
1413 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1414 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1415 radeon_pm_get_dynpm_state(rdev);
1416 radeon_pm_set_clocks(rdev);
1417 }
1418 }
1419 }
1420 }
1421
1422 mutex_unlock(&rdev->pm.mutex);
1423 }
1424
1425 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1426 {
1427 struct drm_device *ddev = rdev->ddev;
1428 struct drm_crtc *crtc;
1429 struct radeon_crtc *radeon_crtc;
1430
1431 mutex_lock(&rdev->pm.mutex);
1432
1433 /* update active crtc counts */
1434 rdev->pm.dpm.new_active_crtcs = 0;
1435 rdev->pm.dpm.new_active_crtc_count = 0;
1436 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1437 list_for_each_entry(crtc,
1438 &ddev->mode_config.crtc_list, head) {
1439 radeon_crtc = to_radeon_crtc(crtc);
1440 if (crtc->enabled) {
1441 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1442 rdev->pm.dpm.new_active_crtc_count++;
1443 }
1444 }
1445 }
1446
1447 /* update battery/ac status */
1448 if (power_supply_is_system_supplied() > 0)
1449 rdev->pm.dpm.ac_power = true;
1450 else
1451 rdev->pm.dpm.ac_power = false;
1452
1453 radeon_dpm_change_power_state_locked(rdev);
1454
1455 mutex_unlock(&rdev->pm.mutex);
1456
1457 }
1458
1459 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1460 {
1461 if (rdev->pm.pm_method == PM_METHOD_DPM)
1462 radeon_pm_compute_clocks_dpm(rdev);
1463 else
1464 radeon_pm_compute_clocks_old(rdev);
1465 }
1466
1467 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1468 {
1469 int crtc, vpos, hpos, vbl_status;
1470 bool in_vbl = true;
1471
1472 /* Iterate over all active crtc's. All crtc's must be in vblank,
1473 * otherwise return in_vbl == false.
1474 */
1475 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1476 if (rdev->pm.active_crtcs & (1 << crtc)) {
1477 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1478 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1479 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1480 in_vbl = false;
1481 }
1482 }
1483
1484 return in_vbl;
1485 }
1486
1487 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1488 {
1489 u32 stat_crtc = 0;
1490 bool in_vbl = radeon_pm_in_vbl(rdev);
1491
1492 if (in_vbl == false)
1493 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1494 finish ? "exit" : "entry");
1495 return in_vbl;
1496 }
1497
1498 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1499 {
1500 struct radeon_device *rdev;
1501 int resched;
1502 rdev = container_of(work, struct radeon_device,
1503 pm.dynpm_idle_work.work);
1504
1505 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1506 mutex_lock(&rdev->pm.mutex);
1507 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1508 int not_processed = 0;
1509 int i;
1510
1511 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1512 struct radeon_ring *ring = &rdev->ring[i];
1513
1514 if (ring->ready) {
1515 not_processed += radeon_fence_count_emitted(rdev, i);
1516 if (not_processed >= 3)
1517 break;
1518 }
1519 }
1520
1521 if (not_processed >= 3) { /* should upclock */
1522 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1523 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1524 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1525 rdev->pm.dynpm_can_upclock) {
1526 rdev->pm.dynpm_planned_action =
1527 DYNPM_ACTION_UPCLOCK;
1528 rdev->pm.dynpm_action_timeout = jiffies +
1529 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1530 }
1531 } else if (not_processed == 0) { /* should downclock */
1532 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1533 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1534 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1535 rdev->pm.dynpm_can_downclock) {
1536 rdev->pm.dynpm_planned_action =
1537 DYNPM_ACTION_DOWNCLOCK;
1538 rdev->pm.dynpm_action_timeout = jiffies +
1539 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1540 }
1541 }
1542
1543 /* Note, radeon_pm_set_clocks is called with static_switch set
1544 * to false since we want to wait for vbl to avoid flicker.
1545 */
1546 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1547 jiffies > rdev->pm.dynpm_action_timeout) {
1548 radeon_pm_get_dynpm_state(rdev);
1549 radeon_pm_set_clocks(rdev);
1550 }
1551
1552 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1553 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1554 }
1555 mutex_unlock(&rdev->pm.mutex);
1556 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1557 }
1558
1559 /*
1560 * Debugfs info
1561 */
1562 #if defined(CONFIG_DEBUG_FS)
1563
1564 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1565 {
1566 struct drm_info_node *node = (struct drm_info_node *) m->private;
1567 struct drm_device *dev = node->minor->dev;
1568 struct radeon_device *rdev = dev->dev_private;
1569
1570 if (rdev->pm.dpm_enabled) {
1571 mutex_lock(&rdev->pm.mutex);
1572 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1573 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1574 else
1575 seq_printf(m, "Debugfs support not implemented for this asic\n");
1576 mutex_unlock(&rdev->pm.mutex);
1577 } else {
1578 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1579 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1580 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1581 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1582 else
1583 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1584 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1585 if (rdev->asic->pm.get_memory_clock)
1586 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1587 if (rdev->pm.current_vddc)
1588 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1589 if (rdev->asic->pm.get_pcie_lanes)
1590 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1591 }
1592
1593 return 0;
1594 }
1595
1596 static struct drm_info_list radeon_pm_info_list[] = {
1597 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1598 };
1599 #endif
1600
1601 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1602 {
1603 #if defined(CONFIG_DEBUG_FS)
1604 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1605 #else
1606 return 0;
1607 #endif
1608 }
Linux with added FPC-III support