drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "r600d.h"
  38
  39 /* 1 second timeout */
  40 #define UVD_IDLE_TIMEOUT_MS     1000
  41
  42 /* Firmware Names */
  43 #define FIRMWARE_RV710          "radeon/RV710_uvd.bin"
  44 #define FIRMWARE_CYPRESS        "radeon/CYPRESS_uvd.bin"
  45 #define FIRMWARE_SUMO           "radeon/SUMO_uvd.bin"
  46 #define FIRMWARE_TAHITI         "radeon/TAHITI_uvd.bin"
  47 #define FIRMWARE_BONAIRE        "radeon/BONAIRE_uvd.bin"
  48
  49 MODULE_FIRMWARE(FIRMWARE_RV710);
  50 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  51 MODULE_FIRMWARE(FIRMWARE_SUMO);
  52 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  53 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  54
  55 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  56
  57 int radeon_uvd_init(struct radeon_device *rdev)
  58 {
  59         unsigned long bo_size;
  60         const char *fw_name;
  61         int i, r;
  62
  63         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  64
  65         switch (rdev->family) {
  66         case CHIP_RV710:
  67         case CHIP_RV730:
  68         case CHIP_RV740:
  69                 fw_name = FIRMWARE_RV710;
  70                 break;
  71
  72         case CHIP_CYPRESS:
  73         case CHIP_HEMLOCK:
  74         case CHIP_JUNIPER:
  75         case CHIP_REDWOOD:
  76         case CHIP_CEDAR:
  77                 fw_name = FIRMWARE_CYPRESS;
  78                 break;
  79
  80         case CHIP_SUMO:
  81         case CHIP_SUMO2:
  82         case CHIP_PALM:
  83         case CHIP_CAYMAN:
  84         case CHIP_BARTS:
  85         case CHIP_TURKS:
  86         case CHIP_CAICOS:
  87                 fw_name = FIRMWARE_SUMO;
  88                 break;
  89
  90         case CHIP_TAHITI:
  91         case CHIP_VERDE:
  92         case CHIP_PITCAIRN:
  93         case CHIP_ARUBA:
  94         case CHIP_OLAND:
  95                 fw_name = FIRMWARE_TAHITI;
  96                 break;
  97
  98         case CHIP_BONAIRE:
  99         case CHIP_KABINI:
 100         case CHIP_KAVERI:
 101                 fw_name = FIRMWARE_BONAIRE;
 102                 break;
 103
 104         default:
 105                 return -EINVAL;
 106         }
 107
 108         r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 109         if (r) {
 110                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 111                         fw_name);
 112                 return r;
 113         }
 114
 115         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 116                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
 117         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 118                              RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
 119         if (r) {
 120                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 121                 return r;
 122         }
 123
 124         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 125         if (r) {
 126                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 127                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 128                 return r;
 129         }
 130
 131         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 132                           &rdev->uvd.gpu_addr);
 133         if (r) {
 134                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 135                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 136                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 137                 return r;
 138         }
 139
 140         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 141         if (r) {
 142                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 143                 return r;
 144         }
 145
 146         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 147
 148         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 149                 atomic_set(&rdev->uvd.handles[i], 0);
 150                 rdev->uvd.filp[i] = NULL;
 151                 rdev->uvd.img_size[i] = 0;
 152         }
 153
 154         return 0;
 155 }
 156
 157 void radeon_uvd_fini(struct radeon_device *rdev)
 158 {
 159         int r;
 160
 161         if (rdev->uvd.vcpu_bo == NULL)
 162                 return;
 163
 164         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 165         if (!r) {
 166                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 167                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 168                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 169         }
 170
 171         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 172
 173         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
 174
 175         release_firmware(rdev->uvd_fw);
 176 }
 177
 178 int radeon_uvd_suspend(struct radeon_device *rdev)
 179 {
 180         unsigned size;
 181         void *ptr;
 182         int i;
 183
 184         if (rdev->uvd.vcpu_bo == NULL)
 185                 return 0;
 186
 187         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 188                 if (atomic_read(&rdev->uvd.handles[i]))
 189                         break;
 190
 191         if (i == RADEON_MAX_UVD_HANDLES)
 192                 return 0;
 193
 194         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 195         size -= rdev->uvd_fw->size;
 196
 197         ptr = rdev->uvd.cpu_addr;
 198         ptr += rdev->uvd_fw->size;
 199
 200         rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 201         memcpy(rdev->uvd.saved_bo, ptr, size);
 202
 203         return 0;
 204 }
 205
 206 int radeon_uvd_resume(struct radeon_device *rdev)
 207 {
 208         unsigned size;
 209         void *ptr;
 210
 211         if (rdev->uvd.vcpu_bo == NULL)
 212                 return -EINVAL;
 213
 214         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 215
 216         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 217         size -= rdev->uvd_fw->size;
 218
 219         ptr = rdev->uvd.cpu_addr;
 220         ptr += rdev->uvd_fw->size;
 221
 222         if (rdev->uvd.saved_bo != NULL) {
 223                 memcpy(ptr, rdev->uvd.saved_bo, size);
 224                 kfree(rdev->uvd.saved_bo);
 225                 rdev->uvd.saved_bo = NULL;
 226         } else
 227                 memset(ptr, 0, size);
 228
 229         return 0;
 230 }
 231
 232 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
 233 {
 234         rbo->placement.fpfn = 0 >> PAGE_SHIFT;
 235         rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 236 }
 237
 238 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 239 {
 240         int i, r;
 241         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 242                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 243                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 244                         struct radeon_fence *fence;
 245
 246                         radeon_uvd_note_usage(rdev);
 247
 248                         r = radeon_uvd_get_destroy_msg(rdev,
 249                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 250                         if (r) {
 251                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 252                                 continue;
 253                         }
 254
 255                         radeon_fence_wait(fence, false);
 256                         radeon_fence_unref(&fence);
 257
 258                         rdev->uvd.filp[i] = NULL;
 259                         atomic_set(&rdev->uvd.handles[i], 0);
 260                 }
 261         }
 262 }
 263
 264 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 265 {
 266         unsigned stream_type = msg[4];
 267         unsigned width = msg[6];
 268         unsigned height = msg[7];
 269         unsigned dpb_size = msg[9];
 270         unsigned pitch = msg[28];
 271
 272         unsigned width_in_mb = width / 16;
 273         unsigned height_in_mb = ALIGN(height / 16, 2);
 274
 275         unsigned image_size, tmp, min_dpb_size;
 276
 277         image_size = width * height;
 278         image_size += image_size / 2;
 279         image_size = ALIGN(image_size, 1024);
 280
 281         switch (stream_type) {
 282         case 0: /* H264 */
 283
 284                 /* reference picture buffer */
 285                 min_dpb_size = image_size * 17;
 286
 287                 /* macroblock context buffer */
 288                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 289
 290                 /* IT surface buffer */
 291                 min_dpb_size += width_in_mb * height_in_mb * 32;
 292                 break;
 293
 294         case 1: /* VC1 */
 295
 296                 /* reference picture buffer */
 297                 min_dpb_size = image_size * 3;
 298
 299                 /* CONTEXT_BUFFER */
 300                 min_dpb_size += width_in_mb * height_in_mb * 128;
 301
 302                 /* IT surface buffer */
 303                 min_dpb_size += width_in_mb * 64;
 304
 305                 /* DB surface buffer */
 306                 min_dpb_size += width_in_mb * 128;
 307
 308                 /* BP */
 309                 tmp = max(width_in_mb, height_in_mb);
 310                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 311                 break;
 312
 313         case 3: /* MPEG2 */
 314
 315                 /* reference picture buffer */
 316                 min_dpb_size = image_size * 3;
 317                 break;
 318
 319         case 4: /* MPEG4 */
 320
 321                 /* reference picture buffer */
 322                 min_dpb_size = image_size * 3;
 323
 324                 /* CM */
 325                 min_dpb_size += width_in_mb * height_in_mb * 64;
 326
 327                 /* IT surface buffer */
 328                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 329                 break;
 330
 331         default:
 332                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 333                 return -EINVAL;
 334         }
 335
 336         if (width > pitch) {
 337                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 338                 return -EINVAL;
 339         }
 340
 341         if (dpb_size < min_dpb_size) {
 342                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 343                           dpb_size, min_dpb_size);
 344                 return -EINVAL;
 345         }
 346
 347         buf_sizes[0x1] = dpb_size;
 348         buf_sizes[0x2] = image_size;
 349         return 0;
 350 }
 351
 352 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 353                              unsigned offset, unsigned buf_sizes[])
 354 {
 355         int32_t *msg, msg_type, handle;
 356         unsigned img_size = 0;
 357         void *ptr;
 358
 359         int i, r;
 360
 361         if (offset & 0x3F) {
 362                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 363                 return -EINVAL;
 364         }
 365
 366         if (bo->tbo.sync_obj) {
 367                 r = radeon_fence_wait(bo->tbo.sync_obj, false);
 368                 if (r) {
 369                         DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
 370                         return r;
 371                 }
 372         }
 373
 374         r = radeon_bo_kmap(bo, &ptr);
 375         if (r) {
 376                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 377                 return r;
 378         }
 379
 380         msg = ptr + offset;
 381
 382         msg_type = msg[1];
 383         handle = msg[2];
 384
 385         if (handle == 0) {
 386                 DRM_ERROR("Invalid UVD handle!\n");
 387                 return -EINVAL;
 388         }
 389
 390         if (msg_type == 1) {
 391                 /* it's a decode msg, calc buffer sizes */
 392                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 393                 /* calc image size (width * height) */
 394                 img_size = msg[6] * msg[7];
 395                 radeon_bo_kunmap(bo);
 396                 if (r)
 397                         return r;
 398
 399         } else if (msg_type == 2) {
 400                 /* it's a destroy msg, free the handle */
 401                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 402                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 403                 radeon_bo_kunmap(bo);
 404                 return 0;
 405         } else {
 406                 /* it's a create msg, calc image size (width * height) */
 407                 img_size = msg[7] * msg[8];
 408                 radeon_bo_kunmap(bo);
 409
 410                 if (msg_type != 0) {
 411                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 412                         return -EINVAL;
 413                 }
 414
 415                 /* it's a create msg, no special handling needed */
 416         }
 417
 418         /* create or decode, validate the handle */
 419         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 420                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 421                         return 0;
 422         }
 423
 424         /* handle not found try to alloc a new one */
 425         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 426                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 427                         p->rdev->uvd.filp[i] = p->filp;
 428                         p->rdev->uvd.img_size[i] = img_size;
 429                         return 0;
 430                 }
 431         }
 432
 433         DRM_ERROR("No more free UVD handles!\n");
 434         return -EINVAL;
 435 }
 436
 437 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 438                                int data0, int data1,
 439                                unsigned buf_sizes[], bool *has_msg_cmd)
 440 {
 441         struct radeon_cs_chunk *relocs_chunk;
 442         struct radeon_cs_reloc *reloc;
 443         unsigned idx, cmd, offset;
 444         uint64_t start, end;
 445         int r;
 446
 447         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 448         offset = radeon_get_ib_value(p, data0);
 449         idx = radeon_get_ib_value(p, data1);
 450         if (idx >= relocs_chunk->length_dw) {
 451                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 452                           idx, relocs_chunk->length_dw);
 453                 return -EINVAL;
 454         }
 455
 456         reloc = p->relocs_ptr[(idx / 4)];
 457         start = reloc->lobj.gpu_offset;
 458         end = start + radeon_bo_size(reloc->robj);
 459         start += offset;
 460
 461         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 462         p->ib.ptr[data1] = start >> 32;
 463
 464         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 465
 466         if (cmd < 0x4) {
 467                 if (end <= start) {
 468                         DRM_ERROR("invalid reloc offset %X!\n", offset);
 469                         return -EINVAL;
 470                 }
 471                 if ((end - start) < buf_sizes[cmd]) {
 472                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 473                                   (unsigned)(end - start), buf_sizes[cmd]);
 474                         return -EINVAL;
 475                 }
 476
 477         } else if (cmd != 0x100) {
 478                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 479                 return -EINVAL;
 480         }
 481
 482         if ((start >> 28) != ((end - 1) >> 28)) {
 483                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 484                           start, end);
 485                 return -EINVAL;
 486         }
 487
 488         /* TODO: is this still necessary on NI+ ? */
 489         if ((cmd == 0 || cmd == 0x3) &&
 490             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 491                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 492                           start, end);
 493                 return -EINVAL;
 494         }
 495
 496         if (cmd == 0) {
 497                 if (*has_msg_cmd) {
 498                         DRM_ERROR("More than one message in a UVD-IB!\n");
 499                         return -EINVAL;
 500                 }
 501                 *has_msg_cmd = true;
 502                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 503                 if (r)
 504                         return r;
 505         } else if (!*has_msg_cmd) {
 506                 DRM_ERROR("Message needed before other commands are send!\n");
 507                 return -EINVAL;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 514                              struct radeon_cs_packet *pkt,
 515                              int *data0, int *data1,
 516                              unsigned buf_sizes[],
 517                              bool *has_msg_cmd)
 518 {
 519         int i, r;
 520
 521         p->idx++;
 522         for (i = 0; i <= pkt->count; ++i) {
 523                 switch (pkt->reg + i*4) {
 524                 case UVD_GPCOM_VCPU_DATA0:
 525                         *data0 = p->idx;
 526                         break;
 527                 case UVD_GPCOM_VCPU_DATA1:
 528                         *data1 = p->idx;
 529                         break;
 530                 case UVD_GPCOM_VCPU_CMD:
 531                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 532                                                 buf_sizes, has_msg_cmd);
 533                         if (r)
 534                                 return r;
 535                         break;
 536                 case UVD_ENGINE_CNTL:
 537                         break;
 538                 default:
 539                         DRM_ERROR("Invalid reg 0x%X!\n",
 540                                   pkt->reg + i*4);
 541                         return -EINVAL;
 542                 }
 543                 p->idx++;
 544         }
 545         return 0;
 546 }
 547
 548 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 549 {
 550         struct radeon_cs_packet pkt;
 551         int r, data0 = 0, data1 = 0;
 552
 553         /* does the IB has a msg command */
 554         bool has_msg_cmd = false;
 555
 556         /* minimum buffer sizes */
 557         unsigned buf_sizes[] = {
 558                 [0x00000000]    =       2048,
 559                 [0x00000001]    =       32 * 1024 * 1024,
 560                 [0x00000002]    =       2048 * 1152 * 3,
 561                 [0x00000003]    =       2048,
 562         };
 563
 564         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 565                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 566                           p->chunks[p->chunk_ib_idx].length_dw);
 567                 return -EINVAL;
 568         }
 569
 570         if (p->chunk_relocs_idx == -1) {
 571                 DRM_ERROR("No relocation chunk !\n");
 572                 return -EINVAL;
 573         }
 574
 575
 576         do {
 577                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 578                 if (r)
 579                         return r;
 580                 switch (pkt.type) {
 581                 case RADEON_PACKET_TYPE0:
 582                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 583                                               buf_sizes, &has_msg_cmd);
 584                         if (r)
 585                                 return r;
 586                         break;
 587                 case RADEON_PACKET_TYPE2:
 588                         p->idx += pkt.count + 2;
 589                         break;
 590                 default:
 591                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 592                         return -EINVAL;
 593                 }
 594         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 595
 596         if (!has_msg_cmd) {
 597                 DRM_ERROR("UVD-IBs need a msg command!\n");
 598                 return -EINVAL;
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 605                                int ring, struct radeon_bo *bo,
 606                                struct radeon_fence **fence)
 607 {
 608         struct ttm_validate_buffer tv;
 609         struct ww_acquire_ctx ticket;
 610         struct list_head head;
 611         struct radeon_ib ib;
 612         uint64_t addr;
 613         int i, r;
 614
 615         memset(&tv, 0, sizeof(tv));
 616         tv.bo = &bo->tbo;
 617
 618         INIT_LIST_HEAD(&head);
 619         list_add(&tv.head, &head);
 620
 621         r = ttm_eu_reserve_buffers(&ticket, &head);
 622         if (r)
 623                 return r;
 624
 625         radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
 626         radeon_uvd_force_into_uvd_segment(bo);
 627
 628         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 629         if (r)
 630                 goto err;
 631
 632         r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
 633         if (r)
 634                 goto err;
 635
 636         addr = radeon_bo_gpu_offset(bo);
 637         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 638         ib.ptr[1] = addr;
 639         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 640         ib.ptr[3] = addr >> 32;
 641         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 642         ib.ptr[5] = 0;
 643         for (i = 6; i < 16; ++i)
 644                 ib.ptr[i] = PACKET2(0);
 645         ib.length_dw = 16;
 646
 647         r = radeon_ib_schedule(rdev, &ib, NULL);
 648         if (r)
 649                 goto err;
 650         ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 651
 652         if (fence)
 653                 *fence = radeon_fence_ref(ib.fence);
 654
 655         radeon_ib_free(rdev, &ib);
 656         radeon_bo_unref(&bo);
 657         return 0;
 658
 659 err:
 660         ttm_eu_backoff_reservation(&ticket, &head);
 661         return r;
 662 }
 663
 664 /* multiple fence commands without any stream commands in between can
 665    crash the vcpu so just try to emmit a dummy create/destroy msg to
 666    avoid this */
 667 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 668                               uint32_t handle, struct radeon_fence **fence)
 669 {
 670         struct radeon_bo *bo;
 671         uint32_t *msg;
 672         int r, i;
 673
 674         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 675                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 676         if (r)
 677                 return r;
 678
 679         r = radeon_bo_reserve(bo, false);
 680         if (r) {
 681                 radeon_bo_unref(&bo);
 682                 return r;
 683         }
 684
 685         r = radeon_bo_kmap(bo, (void **)&msg);
 686         if (r) {
 687                 radeon_bo_unreserve(bo);
 688                 radeon_bo_unref(&bo);
 689                 return r;
 690         }
 691
 692         /* stitch together an UVD create msg */
 693         msg[0] = cpu_to_le32(0x00000de4);
 694         msg[1] = cpu_to_le32(0x00000000);
 695         msg[2] = cpu_to_le32(handle);
 696         msg[3] = cpu_to_le32(0x00000000);
 697         msg[4] = cpu_to_le32(0x00000000);
 698         msg[5] = cpu_to_le32(0x00000000);
 699         msg[6] = cpu_to_le32(0x00000000);
 700         msg[7] = cpu_to_le32(0x00000780);
 701         msg[8] = cpu_to_le32(0x00000440);
 702         msg[9] = cpu_to_le32(0x00000000);
 703         msg[10] = cpu_to_le32(0x01b37000);
 704         for (i = 11; i < 1024; ++i)
 705                 msg[i] = cpu_to_le32(0x0);
 706
 707         radeon_bo_kunmap(bo);
 708         radeon_bo_unreserve(bo);
 709
 710         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 711 }
 712
 713 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 714                                uint32_t handle, struct radeon_fence **fence)
 715 {
 716         struct radeon_bo *bo;
 717         uint32_t *msg;
 718         int r, i;
 719
 720         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 721                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 722         if (r)
 723                 return r;
 724
 725         r = radeon_bo_reserve(bo, false);
 726         if (r) {
 727                 radeon_bo_unref(&bo);
 728                 return r;
 729         }
 730
 731         r = radeon_bo_kmap(bo, (void **)&msg);
 732         if (r) {
 733                 radeon_bo_unreserve(bo);
 734                 radeon_bo_unref(&bo);
 735                 return r;
 736         }
 737
 738         /* stitch together an UVD destroy msg */
 739         msg[0] = cpu_to_le32(0x00000de4);
 740         msg[1] = cpu_to_le32(0x00000002);
 741         msg[2] = cpu_to_le32(handle);
 742         msg[3] = cpu_to_le32(0x00000000);
 743         for (i = 4; i < 1024; ++i)
 744                 msg[i] = cpu_to_le32(0x0);
 745
 746         radeon_bo_kunmap(bo);
 747         radeon_bo_unreserve(bo);
 748
 749         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 750 }
 751
 752 /**
 753  * radeon_uvd_count_handles - count number of open streams
 754  *
 755  * @rdev: radeon_device pointer
 756  * @sd: number of SD streams
 757  * @hd: number of HD streams
 758  *
 759  * Count the number of open SD/HD streams as a hint for power mangement
 760  */
 761 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 762                                      unsigned *sd, unsigned *hd)
 763 {
 764         unsigned i;
 765
 766         *sd = 0;
 767         *hd = 0;
 768
 769         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 770                 if (!atomic_read(&rdev->uvd.handles[i]))
 771                         continue;
 772
 773                 if (rdev->uvd.img_size[i] >= 720*576)
 774                         ++(*hd);
 775                 else
 776                         ++(*sd);
 777         }
 778 }
 779
 780 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 781 {
 782         struct radeon_device *rdev =
 783                 container_of(work, struct radeon_device, uvd.idle_work.work);
 784
 785         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 786                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 787                         radeon_dpm_enable_uvd(rdev, false);
 788                 } else {
 789                         radeon_set_uvd_clocks(rdev, 0, 0);
 790                 }
 791         } else {
 792                 schedule_delayed_work(&rdev->uvd.idle_work,
 793                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 794         }
 795 }
 796
 797 void radeon_uvd_note_usage(struct radeon_device *rdev)
 798 {
 799         bool streams_changed = false;
 800         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 801         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 802                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 803
 804         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 805                 unsigned hd = 0, sd = 0;
 806                 radeon_uvd_count_handles(rdev, &sd, &hd);
 807                 if ((rdev->pm.dpm.sd != sd) ||
 808                     (rdev->pm.dpm.hd != hd)) {
 809                         rdev->pm.dpm.sd = sd;
 810                         rdev->pm.dpm.hd = hd;
 811                         /* disable this for now */
 812                         /*streams_changed = true;*/
 813                 }
 814         }
 815
 816         if (set_clocks || streams_changed) {
 817                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 818                         radeon_dpm_enable_uvd(rdev, true);
 819                 } else {
 820                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 821                 }
 822         }
 823 }
 824
 825 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 826                                               unsigned target_freq,
 827                                               unsigned pd_min,
 828                                               unsigned pd_even)
 829 {
 830         unsigned post_div = vco_freq / target_freq;
 831
 832         /* adjust to post divider minimum value */
 833         if (post_div < pd_min)
 834                 post_div = pd_min;
 835
 836         /* we alway need a frequency less than or equal the target */
 837         if ((vco_freq / post_div) > target_freq)
 838                 post_div += 1;
 839
 840         /* post dividers above a certain value must be even */
 841         if (post_div > pd_even && post_div % 2)
 842                 post_div += 1;
 843
 844         return post_div;
 845 }
 846
 847 /**
 848  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 849  *
 850  * @rdev: radeon_device pointer
 851  * @vclk: wanted VCLK
 852  * @dclk: wanted DCLK
 853  * @vco_min: minimum VCO frequency
 854  * @vco_max: maximum VCO frequency
 855  * @fb_factor: factor to multiply vco freq with
 856  * @fb_mask: limit and bitmask for feedback divider
 857  * @pd_min: post divider minimum
 858  * @pd_max: post divider maximum
 859  * @pd_even: post divider must be even above this value
 860  * @optimal_fb_div: resulting feedback divider
 861  * @optimal_vclk_div: resulting vclk post divider
 862  * @optimal_dclk_div: resulting dclk post divider
 863  *
 864  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 865  * Returns zero on success -EINVAL on error.
 866  */
 867 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 868                                   unsigned vclk, unsigned dclk,
 869                                   unsigned vco_min, unsigned vco_max,
 870                                   unsigned fb_factor, unsigned fb_mask,
 871                                   unsigned pd_min, unsigned pd_max,
 872                                   unsigned pd_even,
 873                                   unsigned *optimal_fb_div,
 874                                   unsigned *optimal_vclk_div,
 875                                   unsigned *optimal_dclk_div)
 876 {
 877         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 878
 879         /* start off with something large */
 880         unsigned optimal_score = ~0;
 881
 882         /* loop through vco from low to high */
 883         vco_min = max(max(vco_min, vclk), dclk);
 884         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 885
 886                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 887                 unsigned vclk_div, dclk_div, score;
 888
 889                 do_div(fb_div, ref_freq);
 890
 891                 /* fb div out of range ? */
 892                 if (fb_div > fb_mask)
 893                         break; /* it can oly get worse */
 894
 895                 fb_div &= fb_mask;
 896
 897                 /* calc vclk divider with current vco freq */
 898                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 899                                                          pd_min, pd_even);
 900                 if (vclk_div > pd_max)
 901                         break; /* vco is too big, it has to stop */
 902
 903                 /* calc dclk divider with current vco freq */
 904                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 905                                                          pd_min, pd_even);
 906                 if (vclk_div > pd_max)
 907                         break; /* vco is too big, it has to stop */
 908
 909                 /* calc score with current vco freq */
 910                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 911
 912                 /* determine if this vco setting is better than current optimal settings */
 913                 if (score < optimal_score) {
 914                         *optimal_fb_div = fb_div;
 915                         *optimal_vclk_div = vclk_div;
 916                         *optimal_dclk_div = dclk_div;
 917                         optimal_score = score;
 918                         if (optimal_score == 0)
 919                                 break; /* it can't get better than this */
 920                 }
 921         }
 922
 923         /* did we found a valid setup ? */
 924         if (optimal_score == ~0)
 925                 return -EINVAL;
 926
 927         return 0;
 928 }
 929
 930 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 931                                 unsigned cg_upll_func_cntl)
 932 {
 933         unsigned i;
 934
 935         /* make sure UPLL_CTLREQ is deasserted */
 936         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 937
 938         mdelay(10);
 939
 940         /* assert UPLL_CTLREQ */
 941         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 942
 943         /* wait for CTLACK and CTLACK2 to get asserted */
 944         for (i = 0; i < 100; ++i) {
 945                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 946                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 947                         break;
 948                 mdelay(10);
 949         }
 950
 951         /* deassert UPLL_CTLREQ */
 952         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 953
 954         if (i == 100) {
 955                 DRM_ERROR("Timeout setting UVD clocks!\n");
 956                 return -ETIMEDOUT;
 957         }
 958
 959         return 0;
 960 }