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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rs600.c
blobe0daa4fdb0737813b355be256700ba4ae5ac3953
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 /* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
38 #include <drm/drmP.h>
39 #include "radeon.h"
40 #include "radeon_asic.h"
41 #include "atom.h"
42 #include "rs600d.h"
43
44 #include "rs600_reg_safe.h"
45
46 static void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48
49 static const u32 crtc_offsets[2] =
50 {
51 0,
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53 };
54
55 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
56 {
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
58 return true;
59 else
60 return false;
61 }
62
63 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
64 {
65 u32 pos1, pos2;
66
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69
70 if (pos1 != pos2)
71 return true;
72 else
73 return false;
74 }
75
76 /**
77 * avivo_wait_for_vblank - vblank wait asic callback.
78 *
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
81 *
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
83 */
84 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
85 {
86 unsigned i = 0;
87
88 if (crtc >= rdev->num_crtc)
89 return;
90
91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
92 return;
93
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
96 */
97 while (avivo_is_in_vblank(rdev, crtc)) {
98 if (i++ % 100 == 0) {
99 if (!avivo_is_counter_moving(rdev, crtc))
100 break;
101 }
102 }
103
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
107 break;
108 }
109 }
110 }
111
112 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
113 {
114 /* enable the pflip int */
115 radeon_irq_kms_pflip_irq_get(rdev, crtc);
116 }
117
118 void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
119 {
120 /* disable the pflip int */
121 radeon_irq_kms_pflip_irq_put(rdev, crtc);
122 }
123
124 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
125 {
126 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
127 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
128 int i;
129
130 /* Lock the graphics update lock */
131 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
132 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
133
134 /* update the scanout addresses */
135 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
136 (u32)crtc_base);
137 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
138 (u32)crtc_base);
139
140 /* Wait for update_pending to go high. */
141 for (i = 0; i < rdev->usec_timeout; i++) {
142 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
143 break;
144 udelay(1);
145 }
146 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
147
148 /* Unlock the lock, so double-buffering can take place inside vblank */
149 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
150 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
151
152 /* Return current update_pending status: */
153 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
154 }
155
156 void rs600_pm_misc(struct radeon_device *rdev)
157 {
158 int requested_index = rdev->pm.requested_power_state_index;
159 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
160 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
161 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
162 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
163
164 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
165 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
166 tmp = RREG32(voltage->gpio.reg);
167 if (voltage->active_high)
168 tmp |= voltage->gpio.mask;
169 else
170 tmp &= ~(voltage->gpio.mask);
171 WREG32(voltage->gpio.reg, tmp);
172 if (voltage->delay)
173 udelay(voltage->delay);
174 } else {
175 tmp = RREG32(voltage->gpio.reg);
176 if (voltage->active_high)
177 tmp &= ~voltage->gpio.mask;
178 else
179 tmp |= voltage->gpio.mask;
180 WREG32(voltage->gpio.reg, tmp);
181 if (voltage->delay)
182 udelay(voltage->delay);
183 }
184 } else if (voltage->type == VOLTAGE_VDDC)
185 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
186
187 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
188 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
189 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
190 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
191 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
192 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
193 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
194 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
195 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
196 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
197 }
198 } else {
199 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
200 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
201 }
202 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
203
204 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
205 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
206 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
207 if (voltage->delay) {
208 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
209 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
210 } else
211 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
212 } else
213 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
214 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
215
216 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
217 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
218 hdp_dyn_cntl &= ~HDP_FORCEON;
219 else
220 hdp_dyn_cntl |= HDP_FORCEON;
221 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
222 #if 0
223 /* mc_host_dyn seems to cause hangs from time to time */
224 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
225 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
226 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
227 else
228 mc_host_dyn_cntl |= MC_HOST_FORCEON;
229 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
230 #endif
231 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
232 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
233 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
234 else
235 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
236 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
237
238 /* set pcie lanes */
239 if ((rdev->flags & RADEON_IS_PCIE) &&
240 !(rdev->flags & RADEON_IS_IGP) &&
241 rdev->asic->pm.set_pcie_lanes &&
242 (ps->pcie_lanes !=
243 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
244 radeon_set_pcie_lanes(rdev,
245 ps->pcie_lanes);
246 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
247 }
248 }
249
250 void rs600_pm_prepare(struct radeon_device *rdev)
251 {
252 struct drm_device *ddev = rdev->ddev;
253 struct drm_crtc *crtc;
254 struct radeon_crtc *radeon_crtc;
255 u32 tmp;
256
257 /* disable any active CRTCs */
258 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
259 radeon_crtc = to_radeon_crtc(crtc);
260 if (radeon_crtc->enabled) {
261 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
262 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
263 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
264 }
265 }
266 }
267
268 void rs600_pm_finish(struct radeon_device *rdev)
269 {
270 struct drm_device *ddev = rdev->ddev;
271 struct drm_crtc *crtc;
272 struct radeon_crtc *radeon_crtc;
273 u32 tmp;
274
275 /* enable any active CRTCs */
276 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
277 radeon_crtc = to_radeon_crtc(crtc);
278 if (radeon_crtc->enabled) {
279 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
280 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
281 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
282 }
283 }
284 }
285
286 /* hpd for digital panel detect/disconnect */
287 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
288 {
289 u32 tmp;
290 bool connected = false;
291
292 switch (hpd) {
293 case RADEON_HPD_1:
294 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
295 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
296 connected = true;
297 break;
298 case RADEON_HPD_2:
299 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
300 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
301 connected = true;
302 break;
303 default:
304 break;
305 }
306 return connected;
307 }
308
309 void rs600_hpd_set_polarity(struct radeon_device *rdev,
310 enum radeon_hpd_id hpd)
311 {
312 u32 tmp;
313 bool connected = rs600_hpd_sense(rdev, hpd);
314
315 switch (hpd) {
316 case RADEON_HPD_1:
317 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
318 if (connected)
319 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
320 else
321 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
322 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
323 break;
324 case RADEON_HPD_2:
325 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
326 if (connected)
327 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
328 else
329 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
330 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
331 break;
332 default:
333 break;
334 }
335 }
336
337 void rs600_hpd_init(struct radeon_device *rdev)
338 {
339 struct drm_device *dev = rdev->ddev;
340 struct drm_connector *connector;
341 unsigned enable = 0;
342
343 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
344 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
345 switch (radeon_connector->hpd.hpd) {
346 case RADEON_HPD_1:
347 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
348 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
349 break;
350 case RADEON_HPD_2:
351 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
352 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
353 break;
354 default:
355 break;
356 }
357 enable |= 1 << radeon_connector->hpd.hpd;
358 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
359 }
360 radeon_irq_kms_enable_hpd(rdev, enable);
361 }
362
363 void rs600_hpd_fini(struct radeon_device *rdev)
364 {
365 struct drm_device *dev = rdev->ddev;
366 struct drm_connector *connector;
367 unsigned disable = 0;
368
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
371 switch (radeon_connector->hpd.hpd) {
372 case RADEON_HPD_1:
373 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
374 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
375 break;
376 case RADEON_HPD_2:
377 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
378 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
379 break;
380 default:
381 break;
382 }
383 disable |= 1 << radeon_connector->hpd.hpd;
384 }
385 radeon_irq_kms_disable_hpd(rdev, disable);
386 }
387
388 int rs600_asic_reset(struct radeon_device *rdev)
389 {
390 struct rv515_mc_save save;
391 u32 status, tmp;
392 int ret = 0;
393
394 status = RREG32(R_000E40_RBBM_STATUS);
395 if (!G_000E40_GUI_ACTIVE(status)) {
396 return 0;
397 }
398 /* Stops all mc clients */
399 rv515_mc_stop(rdev, &save);
400 status = RREG32(R_000E40_RBBM_STATUS);
401 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
402 /* stop CP */
403 WREG32(RADEON_CP_CSQ_CNTL, 0);
404 tmp = RREG32(RADEON_CP_RB_CNTL);
405 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
406 WREG32(RADEON_CP_RB_RPTR_WR, 0);
407 WREG32(RADEON_CP_RB_WPTR, 0);
408 WREG32(RADEON_CP_RB_CNTL, tmp);
409 pci_save_state(rdev->pdev);
410 /* disable bus mastering */
411 pci_clear_master(rdev->pdev);
412 mdelay(1);
413 /* reset GA+VAP */
414 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
415 S_0000F0_SOFT_RESET_GA(1));
416 RREG32(R_0000F0_RBBM_SOFT_RESET);
417 mdelay(500);
418 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
419 mdelay(1);
420 status = RREG32(R_000E40_RBBM_STATUS);
421 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
422 /* reset CP */
423 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
424 RREG32(R_0000F0_RBBM_SOFT_RESET);
425 mdelay(500);
426 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
427 mdelay(1);
428 status = RREG32(R_000E40_RBBM_STATUS);
429 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
430 /* reset MC */
431 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
432 RREG32(R_0000F0_RBBM_SOFT_RESET);
433 mdelay(500);
434 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
435 mdelay(1);
436 status = RREG32(R_000E40_RBBM_STATUS);
437 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
438 /* restore PCI & busmastering */
439 pci_restore_state(rdev->pdev);
440 /* Check if GPU is idle */
441 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
442 dev_err(rdev->dev, "failed to reset GPU\n");
443 ret = -1;
444 } else
445 dev_info(rdev->dev, "GPU reset succeed\n");
446 rv515_mc_resume(rdev, &save);
447 return ret;
448 }
449
450 /*
451 * GART.
452 */
453 void rs600_gart_tlb_flush(struct radeon_device *rdev)
454 {
455 uint32_t tmp;
456
457 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
458 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
459 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
460
461 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
462 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
463 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
464
465 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
466 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
467 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
468 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
469 }
470
471 static int rs600_gart_init(struct radeon_device *rdev)
472 {
473 int r;
474
475 if (rdev->gart.robj) {
476 WARN(1, "RS600 GART already initialized\n");
477 return 0;
478 }
479 /* Initialize common gart structure */
480 r = radeon_gart_init(rdev);
481 if (r) {
482 return r;
483 }
484 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
485 return radeon_gart_table_vram_alloc(rdev);
486 }
487
488 static int rs600_gart_enable(struct radeon_device *rdev)
489 {
490 u32 tmp;
491 int r, i;
492
493 if (rdev->gart.robj == NULL) {
494 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
495 return -EINVAL;
496 }
497 r = radeon_gart_table_vram_pin(rdev);
498 if (r)
499 return r;
500 radeon_gart_restore(rdev);
501 /* Enable bus master */
502 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
503 WREG32(RADEON_BUS_CNTL, tmp);
504 /* FIXME: setup default page */
505 WREG32_MC(R_000100_MC_PT0_CNTL,
506 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
507 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
508
509 for (i = 0; i < 19; i++) {
510 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
511 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
512 S_00016C_SYSTEM_ACCESS_MODE_MASK(
513 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
514 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
515 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
516 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
517 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
518 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
519 }
520 /* enable first context */
521 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
522 S_000102_ENABLE_PAGE_TABLE(1) |
523 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
524
525 /* disable all other contexts */
526 for (i = 1; i < 8; i++)
527 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
528
529 /* setup the page table */
530 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
531 rdev->gart.table_addr);
532 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
533 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
534 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
535
536 /* System context maps to VRAM space */
537 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
538 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
539
540 /* enable page tables */
541 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
542 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
543 tmp = RREG32_MC(R_000009_MC_CNTL1);
544 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
545 rs600_gart_tlb_flush(rdev);
546 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
547 (unsigned)(rdev->mc.gtt_size >> 20),
548 (unsigned long long)rdev->gart.table_addr);
549 rdev->gart.ready = true;
550 return 0;
551 }
552
553 static void rs600_gart_disable(struct radeon_device *rdev)
554 {
555 u32 tmp;
556
557 /* FIXME: disable out of gart access */
558 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
559 tmp = RREG32_MC(R_000009_MC_CNTL1);
560 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
561 radeon_gart_table_vram_unpin(rdev);
562 }
563
564 static void rs600_gart_fini(struct radeon_device *rdev)
565 {
566 radeon_gart_fini(rdev);
567 rs600_gart_disable(rdev);
568 radeon_gart_table_vram_free(rdev);
569 }
570
571 #define R600_PTE_VALID (1 << 0)
572 #define R600_PTE_SYSTEM (1 << 1)
573 #define R600_PTE_SNOOPED (1 << 2)
574 #define R600_PTE_READABLE (1 << 5)
575 #define R600_PTE_WRITEABLE (1 << 6)
576
577 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
578 {
579 void __iomem *ptr = (void *)rdev->gart.ptr;
580
581 if (i < 0 || i > rdev->gart.num_gpu_pages) {
582 return -EINVAL;
583 }
584 addr = addr & 0xFFFFFFFFFFFFF000ULL;
585 if (addr != rdev->dummy_page.addr)
586 addr |= R600_PTE_VALID | R600_PTE_READABLE |
587 R600_PTE_WRITEABLE;
588 addr |= R600_PTE_SYSTEM | R600_PTE_SNOOPED;
589 writeq(addr, ptr + (i * 8));
590 return 0;
591 }
592
593 int rs600_irq_set(struct radeon_device *rdev)
594 {
595 uint32_t tmp = 0;
596 uint32_t mode_int = 0;
597 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
598 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
599 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
600 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
601 u32 hdmi0;
602 if (ASIC_IS_DCE2(rdev))
603 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
604 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
605 else
606 hdmi0 = 0;
607
608 if (!rdev->irq.installed) {
609 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
610 WREG32(R_000040_GEN_INT_CNTL, 0);
611 return -EINVAL;
612 }
613 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
614 tmp |= S_000040_SW_INT_EN(1);
615 }
616 if (rdev->irq.crtc_vblank_int[0] ||
617 atomic_read(&rdev->irq.pflip[0])) {
618 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
619 }
620 if (rdev->irq.crtc_vblank_int[1] ||
621 atomic_read(&rdev->irq.pflip[1])) {
622 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
623 }
624 if (rdev->irq.hpd[0]) {
625 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
626 }
627 if (rdev->irq.hpd[1]) {
628 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
629 }
630 if (rdev->irq.afmt[0]) {
631 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
632 }
633 WREG32(R_000040_GEN_INT_CNTL, tmp);
634 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
635 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
636 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
637 if (ASIC_IS_DCE2(rdev))
638 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
639 return 0;
640 }
641
642 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
643 {
644 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
645 uint32_t irq_mask = S_000044_SW_INT(1);
646 u32 tmp;
647
648 if (G_000044_DISPLAY_INT_STAT(irqs)) {
649 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
650 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
651 WREG32(R_006534_D1MODE_VBLANK_STATUS,
652 S_006534_D1MODE_VBLANK_ACK(1));
653 }
654 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
655 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
656 S_006D34_D2MODE_VBLANK_ACK(1));
657 }
658 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
659 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
660 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
661 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
662 }
663 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
664 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
665 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
666 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
667 }
668 } else {
669 rdev->irq.stat_regs.r500.disp_int = 0;
670 }
671
672 if (ASIC_IS_DCE2(rdev)) {
673 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
674 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
675 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
676 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
677 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
678 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
679 }
680 } else
681 rdev->irq.stat_regs.r500.hdmi0_status = 0;
682
683 if (irqs) {
684 WREG32(R_000044_GEN_INT_STATUS, irqs);
685 }
686 return irqs & irq_mask;
687 }
688
689 void rs600_irq_disable(struct radeon_device *rdev)
690 {
691 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
692 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
693 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
694 WREG32(R_000040_GEN_INT_CNTL, 0);
695 WREG32(R_006540_DxMODE_INT_MASK, 0);
696 /* Wait and acknowledge irq */
697 mdelay(1);
698 rs600_irq_ack(rdev);
699 }
700
701 int rs600_irq_process(struct radeon_device *rdev)
702 {
703 u32 status, msi_rearm;
704 bool queue_hotplug = false;
705 bool queue_hdmi = false;
706
707 status = rs600_irq_ack(rdev);
708 if (!status &&
709 !rdev->irq.stat_regs.r500.disp_int &&
710 !rdev->irq.stat_regs.r500.hdmi0_status) {
711 return IRQ_NONE;
712 }
713 while (status ||
714 rdev->irq.stat_regs.r500.disp_int ||
715 rdev->irq.stat_regs.r500.hdmi0_status) {
716 /* SW interrupt */
717 if (G_000044_SW_INT(status)) {
718 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
719 }
720 /* Vertical blank interrupts */
721 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
722 if (rdev->irq.crtc_vblank_int[0]) {
723 drm_handle_vblank(rdev->ddev, 0);
724 rdev->pm.vblank_sync = true;
725 wake_up(&rdev->irq.vblank_queue);
726 }
727 if (atomic_read(&rdev->irq.pflip[0]))
728 radeon_crtc_handle_flip(rdev, 0);
729 }
730 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
731 if (rdev->irq.crtc_vblank_int[1]) {
732 drm_handle_vblank(rdev->ddev, 1);
733 rdev->pm.vblank_sync = true;
734 wake_up(&rdev->irq.vblank_queue);
735 }
736 if (atomic_read(&rdev->irq.pflip[1]))
737 radeon_crtc_handle_flip(rdev, 1);
738 }
739 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
740 queue_hotplug = true;
741 DRM_DEBUG("HPD1\n");
742 }
743 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
744 queue_hotplug = true;
745 DRM_DEBUG("HPD2\n");
746 }
747 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
748 queue_hdmi = true;
749 DRM_DEBUG("HDMI0\n");
750 }
751 status = rs600_irq_ack(rdev);
752 }
753 if (queue_hotplug)
754 schedule_work(&rdev->hotplug_work);
755 if (queue_hdmi)
756 schedule_work(&rdev->audio_work);
757 if (rdev->msi_enabled) {
758 switch (rdev->family) {
759 case CHIP_RS600:
760 case CHIP_RS690:
761 case CHIP_RS740:
762 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
763 WREG32(RADEON_BUS_CNTL, msi_rearm);
764 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
765 break;
766 default:
767 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
768 break;
769 }
770 }
771 return IRQ_HANDLED;
772 }
773
774 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
775 {
776 if (crtc == 0)
777 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
778 else
779 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
780 }
781
782 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
783 {
784 unsigned i;
785
786 for (i = 0; i < rdev->usec_timeout; i++) {
787 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
788 return 0;
789 udelay(1);
790 }
791 return -1;
792 }
793
794 static void rs600_gpu_init(struct radeon_device *rdev)
795 {
796 r420_pipes_init(rdev);
797 /* Wait for mc idle */
798 if (rs600_mc_wait_for_idle(rdev))
799 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
800 }
801
802 static void rs600_mc_init(struct radeon_device *rdev)
803 {
804 u64 base;
805
806 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
807 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
808 rdev->mc.vram_is_ddr = true;
809 rdev->mc.vram_width = 128;
810 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
811 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
812 rdev->mc.visible_vram_size = rdev->mc.aper_size;
813 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
814 base = RREG32_MC(R_000004_MC_FB_LOCATION);
815 base = G_000004_MC_FB_START(base) << 16;
816 radeon_vram_location(rdev, &rdev->mc, base);
817 rdev->mc.gtt_base_align = 0;
818 radeon_gtt_location(rdev, &rdev->mc);
819 radeon_update_bandwidth_info(rdev);
820 }
821
822 void rs600_bandwidth_update(struct radeon_device *rdev)
823 {
824 struct drm_display_mode *mode0 = NULL;
825 struct drm_display_mode *mode1 = NULL;
826 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
827 /* FIXME: implement full support */
828
829 radeon_update_display_priority(rdev);
830
831 if (rdev->mode_info.crtcs[0]->base.enabled)
832 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
833 if (rdev->mode_info.crtcs[1]->base.enabled)
834 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
835
836 rs690_line_buffer_adjust(rdev, mode0, mode1);
837
838 if (rdev->disp_priority == 2) {
839 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
840 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
841 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
842 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
843 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
844 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
845 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
846 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
847 }
848 }
849
850 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
851 {
852 unsigned long flags;
853 u32 r;
854
855 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
856 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
857 S_000070_MC_IND_CITF_ARB0(1));
858 r = RREG32(R_000074_MC_IND_DATA);
859 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
860 return r;
861 }
862
863 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
864 {
865 unsigned long flags;
866
867 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
868 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
869 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
870 WREG32(R_000074_MC_IND_DATA, v);
871 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
872 }
873
874 static void rs600_debugfs(struct radeon_device *rdev)
875 {
876 if (r100_debugfs_rbbm_init(rdev))
877 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
878 }
879
880 void rs600_set_safe_registers(struct radeon_device *rdev)
881 {
882 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
883 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
884 }
885
886 static void rs600_mc_program(struct radeon_device *rdev)
887 {
888 struct rv515_mc_save save;
889
890 /* Stops all mc clients */
891 rv515_mc_stop(rdev, &save);
892
893 /* Wait for mc idle */
894 if (rs600_mc_wait_for_idle(rdev))
895 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
896
897 /* FIXME: What does AGP means for such chipset ? */
898 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
899 WREG32_MC(R_000006_AGP_BASE, 0);
900 WREG32_MC(R_000007_AGP_BASE_2, 0);
901 /* Program MC */
902 WREG32_MC(R_000004_MC_FB_LOCATION,
903 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
904 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
905 WREG32(R_000134_HDP_FB_LOCATION,
906 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
907
908 rv515_mc_resume(rdev, &save);
909 }
910
911 static int rs600_startup(struct radeon_device *rdev)
912 {
913 int r;
914
915 rs600_mc_program(rdev);
916 /* Resume clock */
917 rv515_clock_startup(rdev);
918 /* Initialize GPU configuration (# pipes, ...) */
919 rs600_gpu_init(rdev);
920 /* Initialize GART (initialize after TTM so we can allocate
921 * memory through TTM but finalize after TTM) */
922 r = rs600_gart_enable(rdev);
923 if (r)
924 return r;
925
926 /* allocate wb buffer */
927 r = radeon_wb_init(rdev);
928 if (r)
929 return r;
930
931 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
932 if (r) {
933 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
934 return r;
935 }
936
937 /* Enable IRQ */
938 if (!rdev->irq.installed) {
939 r = radeon_irq_kms_init(rdev);
940 if (r)
941 return r;
942 }
943
944 rs600_irq_set(rdev);
945 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
946 /* 1M ring buffer */
947 r = r100_cp_init(rdev, 1024 * 1024);
948 if (r) {
949 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
950 return r;
951 }
952
953 r = radeon_ib_pool_init(rdev);
954 if (r) {
955 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
956 return r;
957 }
958
959 r = r600_audio_init(rdev);
960 if (r) {
961 dev_err(rdev->dev, "failed initializing audio\n");
962 return r;
963 }
964
965 return 0;
966 }
967
968 int rs600_resume(struct radeon_device *rdev)
969 {
970 int r;
971
972 /* Make sur GART are not working */
973 rs600_gart_disable(rdev);
974 /* Resume clock before doing reset */
975 rv515_clock_startup(rdev);
976 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
977 if (radeon_asic_reset(rdev)) {
978 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
979 RREG32(R_000E40_RBBM_STATUS),
980 RREG32(R_0007C0_CP_STAT));
981 }
982 /* post */
983 atom_asic_init(rdev->mode_info.atom_context);
984 /* Resume clock after posting */
985 rv515_clock_startup(rdev);
986 /* Initialize surface registers */
987 radeon_surface_init(rdev);
988
989 rdev->accel_working = true;
990 r = rs600_startup(rdev);
991 if (r) {
992 rdev->accel_working = false;
993 }
994 return r;
995 }
996
997 int rs600_suspend(struct radeon_device *rdev)
998 {
999 r600_audio_fini(rdev);
1000 r100_cp_disable(rdev);
1001 radeon_wb_disable(rdev);
1002 rs600_irq_disable(rdev);
1003 rs600_gart_disable(rdev);
1004 return 0;
1005 }
1006
1007 void rs600_fini(struct radeon_device *rdev)
1008 {
1009 r600_audio_fini(rdev);
1010 r100_cp_fini(rdev);
1011 radeon_wb_fini(rdev);
1012 radeon_ib_pool_fini(rdev);
1013 radeon_gem_fini(rdev);
1014 rs600_gart_fini(rdev);
1015 radeon_irq_kms_fini(rdev);
1016 radeon_fence_driver_fini(rdev);
1017 radeon_bo_fini(rdev);
1018 radeon_atombios_fini(rdev);
1019 kfree(rdev->bios);
1020 rdev->bios = NULL;
1021 }
1022
1023 int rs600_init(struct radeon_device *rdev)
1024 {
1025 int r;
1026
1027 /* Disable VGA */
1028 rv515_vga_render_disable(rdev);
1029 /* Initialize scratch registers */
1030 radeon_scratch_init(rdev);
1031 /* Initialize surface registers */
1032 radeon_surface_init(rdev);
1033 /* restore some register to sane defaults */
1034 r100_restore_sanity(rdev);
1035 /* BIOS */
1036 if (!radeon_get_bios(rdev)) {
1037 if (ASIC_IS_AVIVO(rdev))
1038 return -EINVAL;
1039 }
1040 if (rdev->is_atom_bios) {
1041 r = radeon_atombios_init(rdev);
1042 if (r)
1043 return r;
1044 } else {
1045 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1046 return -EINVAL;
1047 }
1048 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1049 if (radeon_asic_reset(rdev)) {
1050 dev_warn(rdev->dev,
1051 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1052 RREG32(R_000E40_RBBM_STATUS),
1053 RREG32(R_0007C0_CP_STAT));
1054 }
1055 /* check if cards are posted or not */
1056 if (radeon_boot_test_post_card(rdev) == false)
1057 return -EINVAL;
1058
1059 /* Initialize clocks */
1060 radeon_get_clock_info(rdev->ddev);
1061 /* initialize memory controller */
1062 rs600_mc_init(rdev);
1063 rs600_debugfs(rdev);
1064 /* Fence driver */
1065 r = radeon_fence_driver_init(rdev);
1066 if (r)
1067 return r;
1068 /* Memory manager */
1069 r = radeon_bo_init(rdev);
1070 if (r)
1071 return r;
1072 r = rs600_gart_init(rdev);
1073 if (r)
1074 return r;
1075 rs600_set_safe_registers(rdev);
1076
1077 rdev->accel_working = true;
1078 r = rs600_startup(rdev);
1079 if (r) {
1080 /* Somethings want wront with the accel init stop accel */
1081 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1082 r100_cp_fini(rdev);
1083 radeon_wb_fini(rdev);
1084 radeon_ib_pool_fini(rdev);
1085 rs600_gart_fini(rdev);
1086 radeon_irq_kms_fini(rdev);
1087 rdev->accel_working = false;
1088 }
1089 return 0;
1090 }
Linux with added FPC-III support