2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
62 Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
63 BayTrail (SOC) 0x0f12 32 hard yes yes yes
65 Features supported by this driver:
69 Block process call transaction no
70 I2C block read transaction yes (doesn't use the block buffer)
72 Interrupt processing yes
74 See the file Documentation/i2c/busses/i2c-i801 for details.
77 #include <linux/interrupt.h>
78 #include <linux/module.h>
79 #include <linux/pci.h>
80 #include <linux/kernel.h>
81 #include <linux/stddef.h>
82 #include <linux/delay.h>
83 #include <linux/ioport.h>
84 #include <linux/init.h>
85 #include <linux/i2c.h>
86 #include <linux/acpi.h>
88 #include <linux/dmi.h>
89 #include <linux/slab.h>
90 #include <linux/wait.h>
91 #include <linux/err.h>
93 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
95 #include <linux/gpio.h>
96 #include <linux/i2c-mux-gpio.h>
97 #include <linux/platform_device.h>
100 /* I801 SMBus address offsets */
101 #define SMBHSTSTS(p) (0 + (p)->smba)
102 #define SMBHSTCNT(p) (2 + (p)->smba)
103 #define SMBHSTCMD(p) (3 + (p)->smba)
104 #define SMBHSTADD(p) (4 + (p)->smba)
105 #define SMBHSTDAT0(p) (5 + (p)->smba)
106 #define SMBHSTDAT1(p) (6 + (p)->smba)
107 #define SMBBLKDAT(p) (7 + (p)->smba)
108 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
109 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
110 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
112 /* PCI Address Constants */
114 #define SMBPCISTS 0x006
115 #define SMBHSTCFG 0x040
117 /* Host status bits for SMBPCISTS */
118 #define SMBPCISTS_INTS 0x08
120 /* Host configuration bits for SMBHSTCFG */
121 #define SMBHSTCFG_HST_EN 1
122 #define SMBHSTCFG_SMB_SMI_EN 2
123 #define SMBHSTCFG_I2C_EN 4
125 /* Auxiliary control register bits, ICH4+ only */
126 #define SMBAUXCTL_CRC 1
127 #define SMBAUXCTL_E32B 2
130 #define MAX_RETRIES 400
132 /* I801 command constants */
133 #define I801_QUICK 0x00
134 #define I801_BYTE 0x04
135 #define I801_BYTE_DATA 0x08
136 #define I801_WORD_DATA 0x0C
137 #define I801_PROC_CALL 0x10 /* unimplemented */
138 #define I801_BLOCK_DATA 0x14
139 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
141 /* I801 Host Control register bits */
142 #define SMBHSTCNT_INTREN 0x01
143 #define SMBHSTCNT_KILL 0x02
144 #define SMBHSTCNT_LAST_BYTE 0x20
145 #define SMBHSTCNT_START 0x40
146 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
148 /* I801 Hosts Status register bits */
149 #define SMBHSTSTS_BYTE_DONE 0x80
150 #define SMBHSTSTS_INUSE_STS 0x40
151 #define SMBHSTSTS_SMBALERT_STS 0x20
152 #define SMBHSTSTS_FAILED 0x10
153 #define SMBHSTSTS_BUS_ERR 0x08
154 #define SMBHSTSTS_DEV_ERR 0x04
155 #define SMBHSTSTS_INTR 0x02
156 #define SMBHSTSTS_HOST_BUSY 0x01
158 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
161 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
164 /* Older devices have their ID defined in <linux/pci_ids.h> */
165 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
166 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
168 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
171 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
172 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
173 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
174 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
175 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
176 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
177 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
179 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
182 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
183 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
185 struct i801_mux_config
{
190 unsigned gpios
[2]; /* Relative to gpio_chip->base */
195 struct i2c_adapter adapter
;
197 unsigned char original_hstcfg
;
198 struct pci_dev
*pci_dev
;
199 unsigned int features
;
202 wait_queue_head_t waitq
;
205 /* Command state used by isr for byte-by-byte block transactions */
212 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
214 const struct i801_mux_config
*mux_drvdata
;
215 struct platform_device
*mux_pdev
;
219 static struct pci_driver i801_driver
;
221 #define FEATURE_SMBUS_PEC (1 << 0)
222 #define FEATURE_BLOCK_BUFFER (1 << 1)
223 #define FEATURE_BLOCK_PROC (1 << 2)
224 #define FEATURE_I2C_BLOCK_READ (1 << 3)
225 #define FEATURE_IRQ (1 << 4)
226 /* Not really a feature, but it's convenient to handle it as such */
227 #define FEATURE_IDF (1 << 15)
229 static const char *i801_feature_names
[] = {
232 "Block process call",
237 static unsigned int disable_features
;
238 module_param(disable_features
, uint
, S_IRUGO
| S_IWUSR
);
239 MODULE_PARM_DESC(disable_features
, "Disable selected driver features:\n"
240 "\t\t 0x01 disable SMBus PEC\n"
241 "\t\t 0x02 disable the block buffer\n"
242 "\t\t 0x08 disable the I2C block read functionality\n"
243 "\t\t 0x10 don't use interrupts ");
245 /* Make sure the SMBus host is ready to start transmitting.
246 Return 0 if it is, -EBUSY if it is not. */
247 static int i801_check_pre(struct i801_priv
*priv
)
251 status
= inb_p(SMBHSTSTS(priv
));
252 if (status
& SMBHSTSTS_HOST_BUSY
) {
253 dev_err(&priv
->pci_dev
->dev
, "SMBus is busy, can't use it!\n");
257 status
&= STATUS_FLAGS
;
259 dev_dbg(&priv
->pci_dev
->dev
, "Clearing status flags (%02x)\n",
261 outb_p(status
, SMBHSTSTS(priv
));
262 status
= inb_p(SMBHSTSTS(priv
)) & STATUS_FLAGS
;
264 dev_err(&priv
->pci_dev
->dev
,
265 "Failed clearing status flags (%02x)\n",
275 * Convert the status register to an error code, and clear it.
276 * Note that status only contains the bits we want to clear, not the
277 * actual register value.
279 static int i801_check_post(struct i801_priv
*priv
, int status
)
284 * If the SMBus is still busy, we give up
285 * Note: This timeout condition only happens when using polling
286 * transactions. For interrupt operation, NAK/timeout is indicated by
289 if (unlikely(status
< 0)) {
290 dev_err(&priv
->pci_dev
->dev
, "Transaction timeout\n");
291 /* try to stop the current command */
292 dev_dbg(&priv
->pci_dev
->dev
, "Terminating the current operation\n");
293 outb_p(inb_p(SMBHSTCNT(priv
)) | SMBHSTCNT_KILL
,
295 usleep_range(1000, 2000);
296 outb_p(inb_p(SMBHSTCNT(priv
)) & (~SMBHSTCNT_KILL
),
299 /* Check if it worked */
300 status
= inb_p(SMBHSTSTS(priv
));
301 if ((status
& SMBHSTSTS_HOST_BUSY
) ||
302 !(status
& SMBHSTSTS_FAILED
))
303 dev_err(&priv
->pci_dev
->dev
,
304 "Failed terminating the transaction\n");
305 outb_p(STATUS_FLAGS
, SMBHSTSTS(priv
));
309 if (status
& SMBHSTSTS_FAILED
) {
311 dev_err(&priv
->pci_dev
->dev
, "Transaction failed\n");
313 if (status
& SMBHSTSTS_DEV_ERR
) {
315 dev_dbg(&priv
->pci_dev
->dev
, "No response\n");
317 if (status
& SMBHSTSTS_BUS_ERR
) {
319 dev_dbg(&priv
->pci_dev
->dev
, "Lost arbitration\n");
322 /* Clear status flags except BYTE_DONE, to be cleared by caller */
323 outb_p(status
, SMBHSTSTS(priv
));
328 /* Wait for BUSY being cleared and either INTR or an error flag being set */
329 static int i801_wait_intr(struct i801_priv
*priv
)
334 /* We will always wait for a fraction of a second! */
336 usleep_range(250, 500);
337 status
= inb_p(SMBHSTSTS(priv
));
338 } while (((status
& SMBHSTSTS_HOST_BUSY
) ||
339 !(status
& (STATUS_ERROR_FLAGS
| SMBHSTSTS_INTR
))) &&
340 (timeout
++ < MAX_RETRIES
));
342 if (timeout
> MAX_RETRIES
) {
343 dev_dbg(&priv
->pci_dev
->dev
, "INTR Timeout!\n");
346 return status
& (STATUS_ERROR_FLAGS
| SMBHSTSTS_INTR
);
349 /* Wait for either BYTE_DONE or an error flag being set */
350 static int i801_wait_byte_done(struct i801_priv
*priv
)
355 /* We will always wait for a fraction of a second! */
357 usleep_range(250, 500);
358 status
= inb_p(SMBHSTSTS(priv
));
359 } while (!(status
& (STATUS_ERROR_FLAGS
| SMBHSTSTS_BYTE_DONE
)) &&
360 (timeout
++ < MAX_RETRIES
));
362 if (timeout
> MAX_RETRIES
) {
363 dev_dbg(&priv
->pci_dev
->dev
, "BYTE_DONE Timeout!\n");
366 return status
& STATUS_ERROR_FLAGS
;
369 static int i801_transaction(struct i801_priv
*priv
, int xact
)
374 result
= i801_check_pre(priv
);
378 if (priv
->features
& FEATURE_IRQ
) {
379 outb_p(xact
| SMBHSTCNT_INTREN
| SMBHSTCNT_START
,
381 wait_event(priv
->waitq
, (status
= priv
->status
));
383 return i801_check_post(priv
, status
);
386 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
387 * SMBSCMD are passed in xact */
388 outb_p(xact
| SMBHSTCNT_START
, SMBHSTCNT(priv
));
390 status
= i801_wait_intr(priv
);
391 return i801_check_post(priv
, status
);
394 static int i801_block_transaction_by_block(struct i801_priv
*priv
,
395 union i2c_smbus_data
*data
,
396 char read_write
, int hwpec
)
401 inb_p(SMBHSTCNT(priv
)); /* reset the data buffer index */
403 /* Use 32-byte buffer to process this transaction */
404 if (read_write
== I2C_SMBUS_WRITE
) {
405 len
= data
->block
[0];
406 outb_p(len
, SMBHSTDAT0(priv
));
407 for (i
= 0; i
< len
; i
++)
408 outb_p(data
->block
[i
+1], SMBBLKDAT(priv
));
411 status
= i801_transaction(priv
, I801_BLOCK_DATA
|
412 (hwpec
? SMBHSTCNT_PEC_EN
: 0));
416 if (read_write
== I2C_SMBUS_READ
) {
417 len
= inb_p(SMBHSTDAT0(priv
));
418 if (len
< 1 || len
> I2C_SMBUS_BLOCK_MAX
)
421 data
->block
[0] = len
;
422 for (i
= 0; i
< len
; i
++)
423 data
->block
[i
+ 1] = inb_p(SMBBLKDAT(priv
));
428 static void i801_isr_byte_done(struct i801_priv
*priv
)
431 /* For SMBus block reads, length is received with first byte */
432 if (((priv
->cmd
& 0x1c) == I801_BLOCK_DATA
) &&
433 (priv
->count
== 0)) {
434 priv
->len
= inb_p(SMBHSTDAT0(priv
));
435 if (priv
->len
< 1 || priv
->len
> I2C_SMBUS_BLOCK_MAX
) {
436 dev_err(&priv
->pci_dev
->dev
,
437 "Illegal SMBus block read size %d\n",
440 priv
->len
= I2C_SMBUS_BLOCK_MAX
;
442 dev_dbg(&priv
->pci_dev
->dev
,
443 "SMBus block read size is %d\n",
446 priv
->data
[-1] = priv
->len
;
450 if (priv
->count
< priv
->len
)
451 priv
->data
[priv
->count
++] = inb(SMBBLKDAT(priv
));
453 dev_dbg(&priv
->pci_dev
->dev
,
454 "Discarding extra byte on block read\n");
456 /* Set LAST_BYTE for last byte of read transaction */
457 if (priv
->count
== priv
->len
- 1)
458 outb_p(priv
->cmd
| SMBHSTCNT_LAST_BYTE
,
460 } else if (priv
->count
< priv
->len
- 1) {
461 /* Write next byte, except for IRQ after last byte */
462 outb_p(priv
->data
[++priv
->count
], SMBBLKDAT(priv
));
465 /* Clear BYTE_DONE to continue with next byte */
466 outb_p(SMBHSTSTS_BYTE_DONE
, SMBHSTSTS(priv
));
470 * There are two kinds of interrupts:
472 * 1) i801 signals transaction completion with one of these interrupts:
474 * DEV_ERR - Invalid command, NAK or communication timeout
475 * BUS_ERR - SMI# transaction collision
476 * FAILED - transaction was canceled due to a KILL request
477 * When any of these occur, update ->status and wake up the waitq.
478 * ->status must be cleared before kicking off the next transaction.
480 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
481 * occurs for each byte of a byte-by-byte to prepare the next byte.
483 static irqreturn_t
i801_isr(int irq
, void *dev_id
)
485 struct i801_priv
*priv
= dev_id
;
489 /* Confirm this is our interrupt */
490 pci_read_config_word(priv
->pci_dev
, SMBPCISTS
, &pcists
);
491 if (!(pcists
& SMBPCISTS_INTS
))
494 status
= inb_p(SMBHSTSTS(priv
));
496 dev_dbg(&priv
->pci_dev
->dev
, "irq: status = %02x\n", status
);
498 if (status
& SMBHSTSTS_BYTE_DONE
)
499 i801_isr_byte_done(priv
);
502 * Clear irq sources and report transaction result.
503 * ->status must be cleared before the next transaction is started.
505 status
&= SMBHSTSTS_INTR
| STATUS_ERROR_FLAGS
;
507 outb_p(status
, SMBHSTSTS(priv
));
508 priv
->status
|= status
;
509 wake_up(&priv
->waitq
);
516 * For "byte-by-byte" block transactions:
517 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
518 * I2C read uses cmd=I801_I2C_BLOCK_DATA
520 static int i801_block_transaction_byte_by_byte(struct i801_priv
*priv
,
521 union i2c_smbus_data
*data
,
522 char read_write
, int command
,
530 result
= i801_check_pre(priv
);
534 len
= data
->block
[0];
536 if (read_write
== I2C_SMBUS_WRITE
) {
537 outb_p(len
, SMBHSTDAT0(priv
));
538 outb_p(data
->block
[1], SMBBLKDAT(priv
));
541 if (command
== I2C_SMBUS_I2C_BLOCK_DATA
&&
542 read_write
== I2C_SMBUS_READ
)
543 smbcmd
= I801_I2C_BLOCK_DATA
;
545 smbcmd
= I801_BLOCK_DATA
;
547 if (priv
->features
& FEATURE_IRQ
) {
548 priv
->is_read
= (read_write
== I2C_SMBUS_READ
);
549 if (len
== 1 && priv
->is_read
)
550 smbcmd
|= SMBHSTCNT_LAST_BYTE
;
551 priv
->cmd
= smbcmd
| SMBHSTCNT_INTREN
;
554 priv
->data
= &data
->block
[1];
556 outb_p(priv
->cmd
| SMBHSTCNT_START
, SMBHSTCNT(priv
));
557 wait_event(priv
->waitq
, (status
= priv
->status
));
559 return i801_check_post(priv
, status
);
562 for (i
= 1; i
<= len
; i
++) {
563 if (i
== len
&& read_write
== I2C_SMBUS_READ
)
564 smbcmd
|= SMBHSTCNT_LAST_BYTE
;
565 outb_p(smbcmd
, SMBHSTCNT(priv
));
568 outb_p(inb(SMBHSTCNT(priv
)) | SMBHSTCNT_START
,
571 status
= i801_wait_byte_done(priv
);
575 if (i
== 1 && read_write
== I2C_SMBUS_READ
576 && command
!= I2C_SMBUS_I2C_BLOCK_DATA
) {
577 len
= inb_p(SMBHSTDAT0(priv
));
578 if (len
< 1 || len
> I2C_SMBUS_BLOCK_MAX
) {
579 dev_err(&priv
->pci_dev
->dev
,
580 "Illegal SMBus block read size %d\n",
583 while (inb_p(SMBHSTSTS(priv
)) &
585 outb_p(SMBHSTSTS_BYTE_DONE
,
587 outb_p(SMBHSTSTS_INTR
, SMBHSTSTS(priv
));
590 data
->block
[0] = len
;
593 /* Retrieve/store value in SMBBLKDAT */
594 if (read_write
== I2C_SMBUS_READ
)
595 data
->block
[i
] = inb_p(SMBBLKDAT(priv
));
596 if (read_write
== I2C_SMBUS_WRITE
&& i
+1 <= len
)
597 outb_p(data
->block
[i
+1], SMBBLKDAT(priv
));
599 /* signals SMBBLKDAT ready */
600 outb_p(SMBHSTSTS_BYTE_DONE
, SMBHSTSTS(priv
));
603 status
= i801_wait_intr(priv
);
605 return i801_check_post(priv
, status
);
608 static int i801_set_block_buffer_mode(struct i801_priv
*priv
)
610 outb_p(inb_p(SMBAUXCTL(priv
)) | SMBAUXCTL_E32B
, SMBAUXCTL(priv
));
611 if ((inb_p(SMBAUXCTL(priv
)) & SMBAUXCTL_E32B
) == 0)
616 /* Block transaction function */
617 static int i801_block_transaction(struct i801_priv
*priv
,
618 union i2c_smbus_data
*data
, char read_write
,
619 int command
, int hwpec
)
624 if (command
== I2C_SMBUS_I2C_BLOCK_DATA
) {
625 if (read_write
== I2C_SMBUS_WRITE
) {
626 /* set I2C_EN bit in configuration register */
627 pci_read_config_byte(priv
->pci_dev
, SMBHSTCFG
, &hostc
);
628 pci_write_config_byte(priv
->pci_dev
, SMBHSTCFG
,
629 hostc
| SMBHSTCFG_I2C_EN
);
630 } else if (!(priv
->features
& FEATURE_I2C_BLOCK_READ
)) {
631 dev_err(&priv
->pci_dev
->dev
,
632 "I2C block read is unsupported!\n");
637 if (read_write
== I2C_SMBUS_WRITE
638 || command
== I2C_SMBUS_I2C_BLOCK_DATA
) {
639 if (data
->block
[0] < 1)
641 if (data
->block
[0] > I2C_SMBUS_BLOCK_MAX
)
642 data
->block
[0] = I2C_SMBUS_BLOCK_MAX
;
644 data
->block
[0] = 32; /* max for SMBus block reads */
647 /* Experience has shown that the block buffer can only be used for
648 SMBus (not I2C) block transactions, even though the datasheet
649 doesn't mention this limitation. */
650 if ((priv
->features
& FEATURE_BLOCK_BUFFER
)
651 && command
!= I2C_SMBUS_I2C_BLOCK_DATA
652 && i801_set_block_buffer_mode(priv
) == 0)
653 result
= i801_block_transaction_by_block(priv
, data
,
656 result
= i801_block_transaction_byte_by_byte(priv
, data
,
660 if (command
== I2C_SMBUS_I2C_BLOCK_DATA
661 && read_write
== I2C_SMBUS_WRITE
) {
662 /* restore saved configuration register value */
663 pci_write_config_byte(priv
->pci_dev
, SMBHSTCFG
, hostc
);
668 /* Return negative errno on error. */
669 static s32
i801_access(struct i2c_adapter
*adap
, u16 addr
,
670 unsigned short flags
, char read_write
, u8 command
,
671 int size
, union i2c_smbus_data
*data
)
676 struct i801_priv
*priv
= i2c_get_adapdata(adap
);
678 hwpec
= (priv
->features
& FEATURE_SMBUS_PEC
) && (flags
& I2C_CLIENT_PEC
)
679 && size
!= I2C_SMBUS_QUICK
680 && size
!= I2C_SMBUS_I2C_BLOCK_DATA
;
683 case I2C_SMBUS_QUICK
:
684 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
689 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
691 if (read_write
== I2C_SMBUS_WRITE
)
692 outb_p(command
, SMBHSTCMD(priv
));
695 case I2C_SMBUS_BYTE_DATA
:
696 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
698 outb_p(command
, SMBHSTCMD(priv
));
699 if (read_write
== I2C_SMBUS_WRITE
)
700 outb_p(data
->byte
, SMBHSTDAT0(priv
));
701 xact
= I801_BYTE_DATA
;
703 case I2C_SMBUS_WORD_DATA
:
704 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
706 outb_p(command
, SMBHSTCMD(priv
));
707 if (read_write
== I2C_SMBUS_WRITE
) {
708 outb_p(data
->word
& 0xff, SMBHSTDAT0(priv
));
709 outb_p((data
->word
& 0xff00) >> 8, SMBHSTDAT1(priv
));
711 xact
= I801_WORD_DATA
;
713 case I2C_SMBUS_BLOCK_DATA
:
714 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
716 outb_p(command
, SMBHSTCMD(priv
));
719 case I2C_SMBUS_I2C_BLOCK_DATA
:
720 /* NB: page 240 of ICH5 datasheet shows that the R/#W
721 * bit should be cleared here, even when reading */
722 outb_p((addr
& 0x7f) << 1, SMBHSTADD(priv
));
723 if (read_write
== I2C_SMBUS_READ
) {
724 /* NB: page 240 of ICH5 datasheet also shows
725 * that DATA1 is the cmd field when reading */
726 outb_p(command
, SMBHSTDAT1(priv
));
728 outb_p(command
, SMBHSTCMD(priv
));
732 dev_err(&priv
->pci_dev
->dev
, "Unsupported transaction %d\n",
737 if (hwpec
) /* enable/disable hardware PEC */
738 outb_p(inb_p(SMBAUXCTL(priv
)) | SMBAUXCTL_CRC
, SMBAUXCTL(priv
));
740 outb_p(inb_p(SMBAUXCTL(priv
)) & (~SMBAUXCTL_CRC
),
744 ret
= i801_block_transaction(priv
, data
, read_write
, size
,
747 ret
= i801_transaction(priv
, xact
);
749 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
750 time, so we forcibly disable it after every transaction. Turn off
751 E32B for the same reason. */
753 outb_p(inb_p(SMBAUXCTL(priv
)) &
754 ~(SMBAUXCTL_CRC
| SMBAUXCTL_E32B
), SMBAUXCTL(priv
));
760 if ((read_write
== I2C_SMBUS_WRITE
) || (xact
== I801_QUICK
))
763 switch (xact
& 0x7f) {
764 case I801_BYTE
: /* Result put in SMBHSTDAT0 */
766 data
->byte
= inb_p(SMBHSTDAT0(priv
));
769 data
->word
= inb_p(SMBHSTDAT0(priv
)) +
770 (inb_p(SMBHSTDAT1(priv
)) << 8);
777 static u32
i801_func(struct i2c_adapter
*adapter
)
779 struct i801_priv
*priv
= i2c_get_adapdata(adapter
);
781 return I2C_FUNC_SMBUS_QUICK
| I2C_FUNC_SMBUS_BYTE
|
782 I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA
|
783 I2C_FUNC_SMBUS_BLOCK_DATA
| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
|
784 ((priv
->features
& FEATURE_SMBUS_PEC
) ? I2C_FUNC_SMBUS_PEC
: 0) |
785 ((priv
->features
& FEATURE_I2C_BLOCK_READ
) ?
786 I2C_FUNC_SMBUS_READ_I2C_BLOCK
: 0);
789 static const struct i2c_algorithm smbus_algorithm
= {
790 .smbus_xfer
= i801_access
,
791 .functionality
= i801_func
,
794 static DEFINE_PCI_DEVICE_TABLE(i801_ids
) = {
795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_3
) },
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_3
) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_2
) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_3
) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_3
) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_3
) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_4
) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_16
) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_17
) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_17
) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_5
) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_6
) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EP80579_1
) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_4
) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_5
) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS
) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS
) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS
) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0
) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1
) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2
) },
816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS
) },
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS
) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS
) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS
) },
820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS
) },
821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS
) },
822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0
) },
823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1
) },
824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2
) },
825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS
) },
826 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS
) },
827 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS
) },
831 MODULE_DEVICE_TABLE(pci
, i801_ids
);
833 #if defined CONFIG_X86 && defined CONFIG_DMI
834 static unsigned char apanel_addr
;
836 /* Scan the system ROM for the signature "FJKEYINF" */
837 static __init
const void __iomem
*bios_signature(const void __iomem
*bios
)
840 const unsigned char signature
[] = "FJKEYINF";
842 for (offset
= 0; offset
< 0x10000; offset
+= 0x10) {
843 if (check_signature(bios
+ offset
, signature
,
844 sizeof(signature
)-1))
845 return bios
+ offset
;
850 static void __init
input_apanel_init(void)
853 const void __iomem
*p
;
855 bios
= ioremap(0xF0000, 0x10000); /* Can't fail */
856 p
= bios_signature(bios
);
858 /* just use the first address */
859 apanel_addr
= readb(p
+ 8 + 3) >> 1;
864 struct dmi_onboard_device_info
{
867 unsigned short i2c_addr
;
868 const char *i2c_type
;
871 static const struct dmi_onboard_device_info dmi_devices
[] = {
872 { "Syleus", DMI_DEV_TYPE_OTHER
, 0x73, "fscsyl" },
873 { "Hermes", DMI_DEV_TYPE_OTHER
, 0x73, "fscher" },
874 { "Hades", DMI_DEV_TYPE_OTHER
, 0x73, "fschds" },
877 static void dmi_check_onboard_device(u8 type
, const char *name
,
878 struct i2c_adapter
*adap
)
881 struct i2c_board_info info
;
883 for (i
= 0; i
< ARRAY_SIZE(dmi_devices
); i
++) {
884 /* & ~0x80, ignore enabled/disabled bit */
885 if ((type
& ~0x80) != dmi_devices
[i
].type
)
887 if (strcasecmp(name
, dmi_devices
[i
].name
))
890 memset(&info
, 0, sizeof(struct i2c_board_info
));
891 info
.addr
= dmi_devices
[i
].i2c_addr
;
892 strlcpy(info
.type
, dmi_devices
[i
].i2c_type
, I2C_NAME_SIZE
);
893 i2c_new_device(adap
, &info
);
898 /* We use our own function to check for onboard devices instead of
899 dmi_find_device() as some buggy BIOS's have the devices we are interested
900 in marked as disabled */
901 static void dmi_check_onboard_devices(const struct dmi_header
*dm
, void *adap
)
908 count
= (dm
->length
- sizeof(struct dmi_header
)) / 2;
909 for (i
= 0; i
< count
; i
++) {
910 const u8
*d
= (char *)(dm
+ 1) + (i
* 2);
911 const char *name
= ((char *) dm
) + dm
->length
;
918 while (s
> 0 && name
[0]) {
919 name
+= strlen(name
) + 1;
922 if (name
[0] == 0) /* Bogus string reference */
925 dmi_check_onboard_device(type
, name
, adap
);
929 /* Register optional slaves */
930 static void i801_probe_optional_slaves(struct i801_priv
*priv
)
932 /* Only register slaves on main SMBus channel */
933 if (priv
->features
& FEATURE_IDF
)
937 struct i2c_board_info info
;
939 memset(&info
, 0, sizeof(struct i2c_board_info
));
940 info
.addr
= apanel_addr
;
941 strlcpy(info
.type
, "fujitsu_apanel", I2C_NAME_SIZE
);
942 i2c_new_device(&priv
->adapter
, &info
);
945 if (dmi_name_in_vendors("FUJITSU"))
946 dmi_walk(dmi_check_onboard_devices
, &priv
->adapter
);
949 static void __init
input_apanel_init(void) {}
950 static void i801_probe_optional_slaves(struct i801_priv
*priv
) {}
951 #endif /* CONFIG_X86 && CONFIG_DMI */
953 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
955 static struct i801_mux_config i801_mux_config_asus_z8_d12
= {
956 .gpio_chip
= "gpio_ich",
957 .values
= { 0x02, 0x03 },
959 .classes
= { I2C_CLASS_SPD
, I2C_CLASS_SPD
},
964 static struct i801_mux_config i801_mux_config_asus_z8_d18
= {
965 .gpio_chip
= "gpio_ich",
966 .values
= { 0x02, 0x03, 0x01 },
968 .classes
= { I2C_CLASS_SPD
, I2C_CLASS_SPD
, I2C_CLASS_SPD
},
973 static const struct dmi_system_id mux_dmi_table
[] = {
976 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
977 DMI_MATCH(DMI_BOARD_NAME
, "Z8NA-D6(C)"),
979 .driver_data
= &i801_mux_config_asus_z8_d12
,
983 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
984 DMI_MATCH(DMI_BOARD_NAME
, "Z8P(N)E-D12(X)"),
986 .driver_data
= &i801_mux_config_asus_z8_d12
,
990 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
991 DMI_MATCH(DMI_BOARD_NAME
, "Z8NH-D12"),
993 .driver_data
= &i801_mux_config_asus_z8_d12
,
997 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
998 DMI_MATCH(DMI_BOARD_NAME
, "Z8PH-D12/IFB"),
1000 .driver_data
= &i801_mux_config_asus_z8_d12
,
1004 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1005 DMI_MATCH(DMI_BOARD_NAME
, "Z8NR-D12"),
1007 .driver_data
= &i801_mux_config_asus_z8_d12
,
1011 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1012 DMI_MATCH(DMI_BOARD_NAME
, "Z8P(N)H-D12"),
1014 .driver_data
= &i801_mux_config_asus_z8_d12
,
1018 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1019 DMI_MATCH(DMI_BOARD_NAME
, "Z8PG-D18"),
1021 .driver_data
= &i801_mux_config_asus_z8_d18
,
1025 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1026 DMI_MATCH(DMI_BOARD_NAME
, "Z8PE-D18"),
1028 .driver_data
= &i801_mux_config_asus_z8_d18
,
1032 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1033 DMI_MATCH(DMI_BOARD_NAME
, "Z8PS-D12"),
1035 .driver_data
= &i801_mux_config_asus_z8_d12
,
1040 /* Setup multiplexing if needed */
1041 static int i801_add_mux(struct i801_priv
*priv
)
1043 struct device
*dev
= &priv
->adapter
.dev
;
1044 const struct i801_mux_config
*mux_config
;
1045 struct i2c_mux_gpio_platform_data gpio_data
;
1048 if (!priv
->mux_drvdata
)
1050 mux_config
= priv
->mux_drvdata
;
1052 /* Prepare the platform data */
1053 memset(&gpio_data
, 0, sizeof(struct i2c_mux_gpio_platform_data
));
1054 gpio_data
.parent
= priv
->adapter
.nr
;
1055 gpio_data
.values
= mux_config
->values
;
1056 gpio_data
.n_values
= mux_config
->n_values
;
1057 gpio_data
.classes
= mux_config
->classes
;
1058 gpio_data
.gpio_chip
= mux_config
->gpio_chip
;
1059 gpio_data
.gpios
= mux_config
->gpios
;
1060 gpio_data
.n_gpios
= mux_config
->n_gpios
;
1061 gpio_data
.idle
= I2C_MUX_GPIO_NO_IDLE
;
1063 /* Register the mux device */
1064 priv
->mux_pdev
= platform_device_register_data(dev
, "i2c-mux-gpio",
1065 PLATFORM_DEVID_AUTO
, &gpio_data
,
1066 sizeof(struct i2c_mux_gpio_platform_data
));
1067 if (IS_ERR(priv
->mux_pdev
)) {
1068 err
= PTR_ERR(priv
->mux_pdev
);
1069 priv
->mux_pdev
= NULL
;
1070 dev_err(dev
, "Failed to register i2c-mux-gpio device\n");
1077 static void i801_del_mux(struct i801_priv
*priv
)
1080 platform_device_unregister(priv
->mux_pdev
);
1083 static unsigned int i801_get_adapter_class(struct i801_priv
*priv
)
1085 const struct dmi_system_id
*id
;
1086 const struct i801_mux_config
*mux_config
;
1087 unsigned int class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
1090 id
= dmi_first_match(mux_dmi_table
);
1092 /* Remove branch classes from trunk */
1093 mux_config
= id
->driver_data
;
1094 for (i
= 0; i
< mux_config
->n_values
; i
++)
1095 class &= ~mux_config
->classes
[i
];
1097 /* Remember for later */
1098 priv
->mux_drvdata
= mux_config
;
1104 static inline int i801_add_mux(struct i801_priv
*priv
) { return 0; }
1105 static inline void i801_del_mux(struct i801_priv
*priv
) { }
1107 static inline unsigned int i801_get_adapter_class(struct i801_priv
*priv
)
1109 return I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
1113 static int i801_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1117 struct i801_priv
*priv
;
1119 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
1123 i2c_set_adapdata(&priv
->adapter
, priv
);
1124 priv
->adapter
.owner
= THIS_MODULE
;
1125 priv
->adapter
.class = i801_get_adapter_class(priv
);
1126 priv
->adapter
.algo
= &smbus_algorithm
;
1128 priv
->pci_dev
= dev
;
1129 switch (dev
->device
) {
1130 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0
:
1131 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1
:
1132 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2
:
1133 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0
:
1134 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1
:
1135 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2
:
1136 priv
->features
|= FEATURE_IDF
;
1139 priv
->features
|= FEATURE_I2C_BLOCK_READ
;
1140 priv
->features
|= FEATURE_IRQ
;
1142 case PCI_DEVICE_ID_INTEL_82801DB_3
:
1143 priv
->features
|= FEATURE_SMBUS_PEC
;
1144 priv
->features
|= FEATURE_BLOCK_BUFFER
;
1146 case PCI_DEVICE_ID_INTEL_82801CA_3
:
1147 case PCI_DEVICE_ID_INTEL_82801BA_2
:
1148 case PCI_DEVICE_ID_INTEL_82801AB_3
:
1149 case PCI_DEVICE_ID_INTEL_82801AA_3
:
1153 /* Disable features on user request */
1154 for (i
= 0; i
< ARRAY_SIZE(i801_feature_names
); i
++) {
1155 if (priv
->features
& disable_features
& (1 << i
))
1156 dev_notice(&dev
->dev
, "%s disabled by user\n",
1157 i801_feature_names
[i
]);
1159 priv
->features
&= ~disable_features
;
1161 err
= pci_enable_device(dev
);
1163 dev_err(&dev
->dev
, "Failed to enable SMBus PCI device (%d)\n",
1168 /* Determine the address of the SMBus area */
1169 priv
->smba
= pci_resource_start(dev
, SMBBAR
);
1171 dev_err(&dev
->dev
, "SMBus base address uninitialized, "
1177 err
= acpi_check_resource_conflict(&dev
->resource
[SMBBAR
]);
1183 err
= pci_request_region(dev
, SMBBAR
, i801_driver
.name
);
1185 dev_err(&dev
->dev
, "Failed to request SMBus region "
1186 "0x%lx-0x%Lx\n", priv
->smba
,
1187 (unsigned long long)pci_resource_end(dev
, SMBBAR
));
1191 pci_read_config_byte(priv
->pci_dev
, SMBHSTCFG
, &temp
);
1192 priv
->original_hstcfg
= temp
;
1193 temp
&= ~SMBHSTCFG_I2C_EN
; /* SMBus timing */
1194 if (!(temp
& SMBHSTCFG_HST_EN
)) {
1195 dev_info(&dev
->dev
, "Enabling SMBus device\n");
1196 temp
|= SMBHSTCFG_HST_EN
;
1198 pci_write_config_byte(priv
->pci_dev
, SMBHSTCFG
, temp
);
1200 if (temp
& SMBHSTCFG_SMB_SMI_EN
) {
1201 dev_dbg(&dev
->dev
, "SMBus using interrupt SMI#\n");
1202 /* Disable SMBus interrupt feature if SMBus using SMI# */
1203 priv
->features
&= ~FEATURE_IRQ
;
1206 /* Clear special mode bits */
1207 if (priv
->features
& (FEATURE_SMBUS_PEC
| FEATURE_BLOCK_BUFFER
))
1208 outb_p(inb_p(SMBAUXCTL(priv
)) &
1209 ~(SMBAUXCTL_CRC
| SMBAUXCTL_E32B
), SMBAUXCTL(priv
));
1211 if (priv
->features
& FEATURE_IRQ
) {
1212 init_waitqueue_head(&priv
->waitq
);
1214 err
= request_irq(dev
->irq
, i801_isr
, IRQF_SHARED
,
1215 i801_driver
.name
, priv
);
1217 dev_err(&dev
->dev
, "Failed to allocate irq %d: %d\n",
1221 dev_info(&dev
->dev
, "SMBus using PCI Interrupt\n");
1224 /* set up the sysfs linkage to our parent device */
1225 priv
->adapter
.dev
.parent
= &dev
->dev
;
1227 /* Retry up to 3 times on lost arbitration */
1228 priv
->adapter
.retries
= 3;
1230 snprintf(priv
->adapter
.name
, sizeof(priv
->adapter
.name
),
1231 "SMBus I801 adapter at %04lx", priv
->smba
);
1232 err
= i2c_add_adapter(&priv
->adapter
);
1234 dev_err(&dev
->dev
, "Failed to add SMBus adapter\n");
1238 i801_probe_optional_slaves(priv
);
1239 /* We ignore errors - multiplexing is optional */
1242 pci_set_drvdata(dev
, priv
);
1247 if (priv
->features
& FEATURE_IRQ
)
1248 free_irq(dev
->irq
, priv
);
1250 pci_release_region(dev
, SMBBAR
);
1256 static void i801_remove(struct pci_dev
*dev
)
1258 struct i801_priv
*priv
= pci_get_drvdata(dev
);
1261 i2c_del_adapter(&priv
->adapter
);
1262 pci_write_config_byte(dev
, SMBHSTCFG
, priv
->original_hstcfg
);
1264 if (priv
->features
& FEATURE_IRQ
)
1265 free_irq(dev
->irq
, priv
);
1266 pci_release_region(dev
, SMBBAR
);
1270 * do not call pci_disable_device(dev) since it can cause hard hangs on
1271 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1276 static int i801_suspend(struct pci_dev
*dev
, pm_message_t mesg
)
1278 struct i801_priv
*priv
= pci_get_drvdata(dev
);
1280 pci_save_state(dev
);
1281 pci_write_config_byte(dev
, SMBHSTCFG
, priv
->original_hstcfg
);
1282 pci_set_power_state(dev
, pci_choose_state(dev
, mesg
));
1286 static int i801_resume(struct pci_dev
*dev
)
1288 pci_set_power_state(dev
, PCI_D0
);
1289 pci_restore_state(dev
);
1290 return pci_enable_device(dev
);
1293 #define i801_suspend NULL
1294 #define i801_resume NULL
1297 static struct pci_driver i801_driver
= {
1298 .name
= "i801_smbus",
1299 .id_table
= i801_ids
,
1300 .probe
= i801_probe
,
1301 .remove
= i801_remove
,
1302 .suspend
= i801_suspend
,
1303 .resume
= i801_resume
,
1306 static int __init
i2c_i801_init(void)
1308 if (dmi_name_in_vendors("FUJITSU"))
1309 input_apanel_init();
1310 return pci_register_driver(&i801_driver
);
1313 static void __exit
i2c_i801_exit(void)
1315 pci_unregister_driver(&i801_driver
);
1318 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
1319 "Jean Delvare <khali@linux-fr.org>");
1320 MODULE_DESCRIPTION("I801 SMBus driver");
1321 MODULE_LICENSE("GPL");
1323 module_init(i2c_i801_init
);
1324 module_exit(i2c_i801_exit
);