?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-imx.c
blob1d7efa3169cd772ed2ba580b0c8cfd149eee09d5
1 /*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
17 * USA.
18 *
19 * Author:
20 * Darius Augulis, Teltonika Inc.
21 *
22 * Desc.:
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
25 *
26 * Derived from Motorola GSG China I2C example driver
27 *
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
32 *
33 * Copyright 2013 Freescale Semiconductor, Inc.
34 *
35 */
36
37 /** Includes *******************************************************************
38 *******************************************************************************/
39
40 #include <linux/init.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/errno.h>
44 #include <linux/err.h>
45 #include <linux/interrupt.h>
46 #include <linux/delay.h>
47 #include <linux/i2c.h>
48 #include <linux/io.h>
49 #include <linux/sched.h>
50 #include <linux/platform_device.h>
51 #include <linux/clk.h>
52 #include <linux/slab.h>
53 #include <linux/of.h>
54 #include <linux/of_device.h>
55 #include <linux/platform_data/i2c-imx.h>
56
57 /** Defines ********************************************************************
58 *******************************************************************************/
59
60 /* This will be the driver name the kernel reports */
61 #define DRIVER_NAME "imx-i2c"
62
63 /* Default value */
64 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
65
66 /* IMX I2C registers:
67 * the I2C register offset is different between SoCs,
68 * to provid support for all these chips, split the
69 * register offset into a fixed base address and a
70 * variable shift value, then the full register offset
71 * will be calculated by
72 * reg_off = ( reg_base_addr << reg_shift)
73 */
74 #define IMX_I2C_IADR 0x00 /* i2c slave address */
75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
76 #define IMX_I2C_I2CR 0x02 /* i2c control */
77 #define IMX_I2C_I2SR 0x03 /* i2c status */
78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
79
80 #define IMX_I2C_REGSHIFT 2
81 #define VF610_I2C_REGSHIFT 0
82
83 /* Bits of IMX I2C registers */
84 #define I2SR_RXAK 0x01
85 #define I2SR_IIF 0x02
86 #define I2SR_SRW 0x04
87 #define I2SR_IAL 0x10
88 #define I2SR_IBB 0x20
89 #define I2SR_IAAS 0x40
90 #define I2SR_ICF 0x80
91 #define I2CR_RSTA 0x04
92 #define I2CR_TXAK 0x08
93 #define I2CR_MTX 0x10
94 #define I2CR_MSTA 0x20
95 #define I2CR_IIEN 0x40
96 #define I2CR_IEN 0x80
97
98 /* register bits different operating codes definition:
99 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
100 * - write zero to clear(w0c) INT flag on i.MX,
101 * - but write one to clear(w1c) INT flag on Vybrid.
102 * 2) I2CR: I2C module enable operation also differ between SoCs:
103 * - set I2CR_IEN bit enable the module on i.MX,
104 * - but clear I2CR_IEN bit enable the module on Vybrid.
105 */
106 #define I2SR_CLR_OPCODE_W0C 0x0
107 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
108 #define I2CR_IEN_OPCODE_0 0x0
109 #define I2CR_IEN_OPCODE_1 I2CR_IEN
110
111 /** Variables ******************************************************************
112 *******************************************************************************/
113
114 /*
115 * sorted list of clock divider, register value pairs
116 * taken from table 26-5, p.26-9, Freescale i.MX
117 * Integrated Portable System Processor Reference Manual
118 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
119 *
120 * Duplicated divider values removed from list
121 */
122 struct imx_i2c_clk_pair {
123 u16 div;
124 u16 val;
125 };
126
127 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
128 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
129 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
130 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
131 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
132 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
133 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
134 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
135 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
136 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
137 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
138 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
139 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
140 { 3072, 0x1E }, { 3840, 0x1F }
141 };
142
143 /* Vybrid VF610 clock divider, register value pairs */
144 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
145 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
146 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
147 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
148 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
149 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
150 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
151 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
152 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
153 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
154 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
155 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
156 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
157 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
158 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
159 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
160 };
161
162 enum imx_i2c_type {
163 IMX1_I2C,
164 IMX21_I2C,
165 VF610_I2C,
166 };
167
168 struct imx_i2c_hwdata {
169 enum imx_i2c_type devtype;
170 unsigned regshift;
171 struct imx_i2c_clk_pair *clk_div;
172 unsigned ndivs;
173 unsigned i2sr_clr_opcode;
174 unsigned i2cr_ien_opcode;
175 };
176
177 struct imx_i2c_struct {
178 struct i2c_adapter adapter;
179 struct clk *clk;
180 void __iomem *base;
181 wait_queue_head_t queue;
182 unsigned long i2csr;
183 unsigned int disable_delay;
184 int stopped;
185 unsigned int ifdr; /* IMX_I2C_IFDR */
186 const struct imx_i2c_hwdata *hwdata;
187 };
188
189 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
190 .devtype = IMX1_I2C,
191 .regshift = IMX_I2C_REGSHIFT,
192 .clk_div = imx_i2c_clk_div,
193 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
194 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
195 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
196
197 };
198
199 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
200 .devtype = IMX21_I2C,
201 .regshift = IMX_I2C_REGSHIFT,
202 .clk_div = imx_i2c_clk_div,
203 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
204 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
205 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
206
207 };
208
209 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
210 .devtype = VF610_I2C,
211 .regshift = VF610_I2C_REGSHIFT,
212 .clk_div = vf610_i2c_clk_div,
213 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
214 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
215 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
216
217 };
218
219 static struct platform_device_id imx_i2c_devtype[] = {
220 {
221 .name = "imx1-i2c",
222 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
223 }, {
224 .name = "imx21-i2c",
225 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
226 }, {
227 /* sentinel */
228 }
229 };
230 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
231
232 static const struct of_device_id i2c_imx_dt_ids[] = {
233 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
234 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
235 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
236 { /* sentinel */ }
237 };
238 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
239
240 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
241 {
242 return i2c_imx->hwdata->devtype == IMX1_I2C;
243 }
244
245 static inline void imx_i2c_write_reg(unsigned int val,
246 struct imx_i2c_struct *i2c_imx, unsigned int reg)
247 {
248 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
249 }
250
251 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
252 unsigned int reg)
253 {
254 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
255 }
256
257 /** Functions for IMX I2C adapter driver ***************************************
258 *******************************************************************************/
259
260 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
261 {
262 unsigned long orig_jiffies = jiffies;
263 unsigned int temp;
264
265 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
266
267 while (1) {
268 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
269 if (for_busy && (temp & I2SR_IBB))
270 break;
271 if (!for_busy && !(temp & I2SR_IBB))
272 break;
273 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
274 dev_dbg(&i2c_imx->adapter.dev,
275 "<%s> I2C bus is busy\n", __func__);
276 return -ETIMEDOUT;
277 }
278 schedule();
279 }
280
281 return 0;
282 }
283
284 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
285 {
286 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
287
288 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
289 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
290 return -ETIMEDOUT;
291 }
292 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
293 i2c_imx->i2csr = 0;
294 return 0;
295 }
296
297 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
298 {
299 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
300 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
301 return -EIO; /* No ACK */
302 }
303
304 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
305 return 0;
306 }
307
308 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
309 {
310 unsigned int temp = 0;
311 int result;
312
313 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
314
315 clk_prepare_enable(i2c_imx->clk);
316 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
317 /* Enable I2C controller */
318 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
319 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
320
321 /* Wait controller to be stable */
322 udelay(50);
323
324 /* Start I2C transaction */
325 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
326 temp |= I2CR_MSTA;
327 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
328 result = i2c_imx_bus_busy(i2c_imx, 1);
329 if (result)
330 return result;
331 i2c_imx->stopped = 0;
332
333 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
334 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
335 return result;
336 }
337
338 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
339 {
340 unsigned int temp = 0;
341
342 if (!i2c_imx->stopped) {
343 /* Stop I2C transaction */
344 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
345 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
346 temp &= ~(I2CR_MSTA | I2CR_MTX);
347 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
348 }
349 if (is_imx1_i2c(i2c_imx)) {
350 /*
351 * This delay caused by an i.MXL hardware bug.
352 * If no (or too short) delay, no "STOP" bit will be generated.
353 */
354 udelay(i2c_imx->disable_delay);
355 }
356
357 if (!i2c_imx->stopped) {
358 i2c_imx_bus_busy(i2c_imx, 0);
359 i2c_imx->stopped = 1;
360 }
361
362 /* Disable I2C controller */
363 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
364 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
365 clk_disable_unprepare(i2c_imx->clk);
366 }
367
368 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
369 unsigned int rate)
370 {
371 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
372 unsigned int i2c_clk_rate;
373 unsigned int div;
374 int i;
375
376 /* Divider value calculation */
377 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
378 div = (i2c_clk_rate + rate - 1) / rate;
379 if (div < i2c_clk_div[0].div)
380 i = 0;
381 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
382 i = i2c_imx->hwdata->ndivs - 1;
383 else
384 for (i = 0; i2c_clk_div[i].div < div; i++);
385
386 /* Store divider value */
387 i2c_imx->ifdr = i2c_clk_div[i].val;
388
389 /*
390 * There dummy delay is calculated.
391 * It should be about one I2C clock period long.
392 * This delay is used in I2C bus disable function
393 * to fix chip hardware bug.
394 */
395 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
396 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
397
398 /* dev_dbg() can't be used, because adapter is not yet registered */
399 #ifdef CONFIG_I2C_DEBUG_BUS
400 dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
401 __func__, i2c_clk_rate, div);
402 dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
403 __func__, i2c_clk_div[i].val, i2c_clk_div[i].div);
404 #endif
405 }
406
407 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
408 {
409 struct imx_i2c_struct *i2c_imx = dev_id;
410 unsigned int temp;
411
412 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
413 if (temp & I2SR_IIF) {
414 /* save status register */
415 i2c_imx->i2csr = temp;
416 temp &= ~I2SR_IIF;
417 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
418 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
419 wake_up(&i2c_imx->queue);
420 return IRQ_HANDLED;
421 }
422
423 return IRQ_NONE;
424 }
425
426 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
427 {
428 int i, result;
429
430 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
431 __func__, msgs->addr << 1);
432
433 /* write slave address */
434 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
435 result = i2c_imx_trx_complete(i2c_imx);
436 if (result)
437 return result;
438 result = i2c_imx_acked(i2c_imx);
439 if (result)
440 return result;
441 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
442
443 /* write data */
444 for (i = 0; i < msgs->len; i++) {
445 dev_dbg(&i2c_imx->adapter.dev,
446 "<%s> write byte: B%d=0x%X\n",
447 __func__, i, msgs->buf[i]);
448 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
449 result = i2c_imx_trx_complete(i2c_imx);
450 if (result)
451 return result;
452 result = i2c_imx_acked(i2c_imx);
453 if (result)
454 return result;
455 }
456 return 0;
457 }
458
459 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
460 {
461 int i, result;
462 unsigned int temp;
463
464 dev_dbg(&i2c_imx->adapter.dev,
465 "<%s> write slave address: addr=0x%x\n",
466 __func__, (msgs->addr << 1) | 0x01);
467
468 /* write slave address */
469 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
470 result = i2c_imx_trx_complete(i2c_imx);
471 if (result)
472 return result;
473 result = i2c_imx_acked(i2c_imx);
474 if (result)
475 return result;
476
477 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
478
479 /* setup bus to read data */
480 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
481 temp &= ~I2CR_MTX;
482 if (msgs->len - 1)
483 temp &= ~I2CR_TXAK;
484 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
485 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
486
487 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
488
489 /* read data */
490 for (i = 0; i < msgs->len; i++) {
491 result = i2c_imx_trx_complete(i2c_imx);
492 if (result)
493 return result;
494 if (i == (msgs->len - 1)) {
495 /* It must generate STOP before read I2DR to prevent
496 controller from generating another clock cycle */
497 dev_dbg(&i2c_imx->adapter.dev,
498 "<%s> clear MSTA\n", __func__);
499 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
500 temp &= ~(I2CR_MSTA | I2CR_MTX);
501 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
502 i2c_imx_bus_busy(i2c_imx, 0);
503 i2c_imx->stopped = 1;
504 } else if (i == (msgs->len - 2)) {
505 dev_dbg(&i2c_imx->adapter.dev,
506 "<%s> set TXAK\n", __func__);
507 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
508 temp |= I2CR_TXAK;
509 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
510 }
511 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
512 dev_dbg(&i2c_imx->adapter.dev,
513 "<%s> read byte: B%d=0x%X\n",
514 __func__, i, msgs->buf[i]);
515 }
516 return 0;
517 }
518
519 static int i2c_imx_xfer(struct i2c_adapter *adapter,
520 struct i2c_msg *msgs, int num)
521 {
522 unsigned int i, temp;
523 int result;
524 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
525
526 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
527
528 /* Start I2C transfer */
529 result = i2c_imx_start(i2c_imx);
530 if (result)
531 goto fail0;
532
533 /* read/write data */
534 for (i = 0; i < num; i++) {
535 if (i) {
536 dev_dbg(&i2c_imx->adapter.dev,
537 "<%s> repeated start\n", __func__);
538 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
539 temp |= I2CR_RSTA;
540 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
541 result = i2c_imx_bus_busy(i2c_imx, 1);
542 if (result)
543 goto fail0;
544 }
545 dev_dbg(&i2c_imx->adapter.dev,
546 "<%s> transfer message: %d\n", __func__, i);
547 /* write/read data */
548 #ifdef CONFIG_I2C_DEBUG_BUS
549 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
550 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
551 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
552 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
553 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
554 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
555 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
556 dev_dbg(&i2c_imx->adapter.dev,
557 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
558 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
559 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
560 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
561 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
562 (temp & I2SR_RXAK ? 1 : 0));
563 #endif
564 if (msgs[i].flags & I2C_M_RD)
565 result = i2c_imx_read(i2c_imx, &msgs[i]);
566 else
567 result = i2c_imx_write(i2c_imx, &msgs[i]);
568 if (result)
569 goto fail0;
570 }
571
572 fail0:
573 /* Stop I2C transfer */
574 i2c_imx_stop(i2c_imx);
575
576 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
577 (result < 0) ? "error" : "success msg",
578 (result < 0) ? result : num);
579 return (result < 0) ? result : num;
580 }
581
582 static u32 i2c_imx_func(struct i2c_adapter *adapter)
583 {
584 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
585 }
586
587 static struct i2c_algorithm i2c_imx_algo = {
588 .master_xfer = i2c_imx_xfer,
589 .functionality = i2c_imx_func,
590 };
591
592 static int i2c_imx_probe(struct platform_device *pdev)
593 {
594 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
595 &pdev->dev);
596 struct imx_i2c_struct *i2c_imx;
597 struct resource *res;
598 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
599 void __iomem *base;
600 int irq, ret;
601 u32 bitrate;
602
603 dev_dbg(&pdev->dev, "<%s>\n", __func__);
604
605 irq = platform_get_irq(pdev, 0);
606 if (irq < 0) {
607 dev_err(&pdev->dev, "can't get irq number\n");
608 return -ENOENT;
609 }
610
611 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
612 base = devm_ioremap_resource(&pdev->dev, res);
613 if (IS_ERR(base))
614 return PTR_ERR(base);
615
616 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
617 GFP_KERNEL);
618 if (!i2c_imx) {
619 dev_err(&pdev->dev, "can't allocate interface\n");
620 return -ENOMEM;
621 }
622
623 if (of_id)
624 i2c_imx->hwdata = of_id->data;
625 else
626 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
627 platform_get_device_id(pdev)->driver_data;
628
629 /* Setup i2c_imx driver structure */
630 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
631 i2c_imx->adapter.owner = THIS_MODULE;
632 i2c_imx->adapter.algo = &i2c_imx_algo;
633 i2c_imx->adapter.dev.parent = &pdev->dev;
634 i2c_imx->adapter.nr = pdev->id;
635 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
636 i2c_imx->base = base;
637
638 /* Get I2C clock */
639 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
640 if (IS_ERR(i2c_imx->clk)) {
641 dev_err(&pdev->dev, "can't get I2C clock\n");
642 return PTR_ERR(i2c_imx->clk);
643 }
644
645 ret = clk_prepare_enable(i2c_imx->clk);
646 if (ret) {
647 dev_err(&pdev->dev, "can't enable I2C clock\n");
648 return ret;
649 }
650 /* Request IRQ */
651 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
652 pdev->name, i2c_imx);
653 if (ret) {
654 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
655 return ret;
656 }
657
658 /* Init queue */
659 init_waitqueue_head(&i2c_imx->queue);
660
661 /* Set up adapter data */
662 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
663
664 /* Set up clock divider */
665 bitrate = IMX_I2C_BIT_RATE;
666 ret = of_property_read_u32(pdev->dev.of_node,
667 "clock-frequency", &bitrate);
668 if (ret < 0 && pdata && pdata->bitrate)
669 bitrate = pdata->bitrate;
670 i2c_imx_set_clk(i2c_imx, bitrate);
671
672 /* Set up chip registers to defaults */
673 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
674 i2c_imx, IMX_I2C_I2CR);
675 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
676
677 /* Add I2C adapter */
678 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
679 if (ret < 0) {
680 dev_err(&pdev->dev, "registration failed\n");
681 return ret;
682 }
683
684 /* Set up platform driver data */
685 platform_set_drvdata(pdev, i2c_imx);
686 clk_disable_unprepare(i2c_imx->clk);
687
688 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
689 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
690 res->start, res->end);
691 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
692 resource_size(res), res->start);
693 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
694 i2c_imx->adapter.name);
695 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
696
697 return 0; /* Return OK */
698 }
699
700 static int i2c_imx_remove(struct platform_device *pdev)
701 {
702 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
703
704 /* remove adapter */
705 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
706 i2c_del_adapter(&i2c_imx->adapter);
707
708 /* setup chip registers to defaults */
709 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
710 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
711 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
712 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
713
714 return 0;
715 }
716
717 static struct platform_driver i2c_imx_driver = {
718 .probe = i2c_imx_probe,
719 .remove = i2c_imx_remove,
720 .driver = {
721 .name = DRIVER_NAME,
722 .owner = THIS_MODULE,
723 .of_match_table = i2c_imx_dt_ids,
724 },
725 .id_table = imx_i2c_devtype,
726 };
727
728 static int __init i2c_adap_imx_init(void)
729 {
730 return platform_driver_register(&i2c_imx_driver);
731 }
732 subsys_initcall(i2c_adap_imx_init);
733
734 static void __exit i2c_adap_imx_exit(void)
735 {
736 platform_driver_unregister(&i2c_imx_driver);
737 }
738 module_exit(i2c_adap_imx_exit);
739
740 MODULE_LICENSE("GPL");
741 MODULE_AUTHOR("Darius Augulis");
742 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
743 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support