2 * Provides I2C support for Philips PNX010x/PNX4008 boards.
4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
5 * Vitaly Wool <vwool@ru.mvista.com>
7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/timer.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c-pnx.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
27 #define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */
28 #define I2C_PNX_SPEED_KHZ_DEFAULT 100
29 #define I2C_PNX_REGION_SIZE 0x100
32 mstatus_tdi
= 0x00000001,
33 mstatus_afi
= 0x00000002,
34 mstatus_nai
= 0x00000004,
35 mstatus_drmi
= 0x00000008,
36 mstatus_active
= 0x00000020,
37 mstatus_scl
= 0x00000040,
38 mstatus_sda
= 0x00000080,
39 mstatus_rff
= 0x00000100,
40 mstatus_rfe
= 0x00000200,
41 mstatus_tff
= 0x00000400,
42 mstatus_tfe
= 0x00000800,
46 mcntrl_tdie
= 0x00000001,
47 mcntrl_afie
= 0x00000002,
48 mcntrl_naie
= 0x00000004,
49 mcntrl_drmie
= 0x00000008,
50 mcntrl_drsie
= 0x00000010,
51 mcntrl_rffie
= 0x00000020,
52 mcntrl_daie
= 0x00000040,
53 mcntrl_tffie
= 0x00000080,
54 mcntrl_reset
= 0x00000100,
55 mcntrl_cdbmode
= 0x00000400,
64 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
65 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
66 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
67 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
68 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
69 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
70 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
71 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
72 #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
73 #define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
74 #define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
75 #define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
76 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
78 static inline int wait_timeout(struct i2c_pnx_algo_data
*data
)
80 long timeout
= data
->timeout
;
82 (ioread32(I2C_REG_STS(data
)) & mstatus_active
)) {
86 return (timeout
<= 0);
89 static inline int wait_reset(struct i2c_pnx_algo_data
*data
)
91 long timeout
= data
->timeout
;
93 (ioread32(I2C_REG_CTL(data
)) & mcntrl_reset
)) {
97 return (timeout
<= 0);
100 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data
*alg_data
)
102 struct timer_list
*timer
= &alg_data
->mif
.timer
;
103 unsigned long expires
= msecs_to_jiffies(alg_data
->timeout
);
108 del_timer_sync(timer
);
110 dev_dbg(&alg_data
->adapter
.dev
, "Timer armed at %lu plus %lu jiffies.\n",
113 timer
->expires
= jiffies
+ expires
;
114 timer
->data
= (unsigned long)alg_data
;
120 * i2c_pnx_start - start a device
121 * @slave_addr: slave address
122 * @adap: pointer to adapter structure
124 * Generate a START signal in the desired mode.
126 static int i2c_pnx_start(unsigned char slave_addr
,
127 struct i2c_pnx_algo_data
*alg_data
)
129 dev_dbg(&alg_data
->adapter
.dev
, "%s(): addr 0x%x mode %d\n", __func__
,
130 slave_addr
, alg_data
->mif
.mode
);
132 /* Check for 7 bit slave addresses only */
133 if (slave_addr
& ~0x7f) {
134 dev_err(&alg_data
->adapter
.dev
,
135 "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
136 alg_data
->adapter
.name
, slave_addr
);
140 /* First, make sure bus is idle */
141 if (wait_timeout(alg_data
)) {
142 /* Somebody else is monopolizing the bus */
143 dev_err(&alg_data
->adapter
.dev
,
144 "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
145 alg_data
->adapter
.name
, slave_addr
,
146 ioread32(I2C_REG_CTL(alg_data
)),
147 ioread32(I2C_REG_STS(alg_data
)));
149 } else if (ioread32(I2C_REG_STS(alg_data
)) & mstatus_afi
) {
150 /* Sorry, we lost the bus */
151 dev_err(&alg_data
->adapter
.dev
,
152 "%s: Arbitration failure. Slave addr = %02x\n",
153 alg_data
->adapter
.name
, slave_addr
);
158 * OK, I2C is enabled and we have the bus.
159 * Clear the current TDI and AFI status flags.
161 iowrite32(ioread32(I2C_REG_STS(alg_data
)) | mstatus_tdi
| mstatus_afi
,
162 I2C_REG_STS(alg_data
));
164 dev_dbg(&alg_data
->adapter
.dev
, "%s(): sending %#x\n", __func__
,
165 (slave_addr
<< 1) | start_bit
| alg_data
->mif
.mode
);
167 /* Write the slave address, START bit and R/W bit */
168 iowrite32((slave_addr
<< 1) | start_bit
| alg_data
->mif
.mode
,
169 I2C_REG_TX(alg_data
));
171 dev_dbg(&alg_data
->adapter
.dev
, "%s(): exit\n", __func__
);
177 * i2c_pnx_stop - stop a device
178 * @adap: pointer to I2C adapter structure
180 * Generate a STOP signal to terminate the master transaction.
182 static void i2c_pnx_stop(struct i2c_pnx_algo_data
*alg_data
)
184 /* Only 1 msec max timeout due to interrupt context */
187 dev_dbg(&alg_data
->adapter
.dev
, "%s(): entering: stat = %04x.\n",
188 __func__
, ioread32(I2C_REG_STS(alg_data
)));
190 /* Write a STOP bit to TX FIFO */
191 iowrite32(0xff | stop_bit
, I2C_REG_TX(alg_data
));
193 /* Wait until the STOP is seen. */
194 while (timeout
> 0 &&
195 (ioread32(I2C_REG_STS(alg_data
)) & mstatus_active
)) {
196 /* may be called from interrupt context */
201 dev_dbg(&alg_data
->adapter
.dev
, "%s(): exiting: stat = %04x.\n",
202 __func__
, ioread32(I2C_REG_STS(alg_data
)));
206 * i2c_pnx_master_xmit - transmit data to slave
207 * @adap: pointer to I2C adapter structure
209 * Sends one byte of data to the slave
211 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data
*alg_data
)
215 dev_dbg(&alg_data
->adapter
.dev
, "%s(): entering: stat = %04x.\n",
216 __func__
, ioread32(I2C_REG_STS(alg_data
)));
218 if (alg_data
->mif
.len
> 0) {
219 /* We still have something to talk about... */
220 val
= *alg_data
->mif
.buf
++;
222 if (alg_data
->mif
.len
== 1)
226 iowrite32(val
, I2C_REG_TX(alg_data
));
228 dev_dbg(&alg_data
->adapter
.dev
, "%s(): xmit %#x [%d]\n",
229 __func__
, val
, alg_data
->mif
.len
+ 1);
231 if (alg_data
->mif
.len
== 0) {
232 if (alg_data
->last
) {
233 /* Wait until the STOP is seen. */
234 if (wait_timeout(alg_data
))
235 dev_err(&alg_data
->adapter
.dev
,
236 "The bus is still active after timeout\n");
238 /* Disable master interrupts */
239 iowrite32(ioread32(I2C_REG_CTL(alg_data
)) &
240 ~(mcntrl_afie
| mcntrl_naie
| mcntrl_drmie
),
241 I2C_REG_CTL(alg_data
));
243 del_timer_sync(&alg_data
->mif
.timer
);
245 dev_dbg(&alg_data
->adapter
.dev
,
246 "%s(): Waking up xfer routine.\n",
249 complete(&alg_data
->mif
.complete
);
251 } else if (alg_data
->mif
.len
== 0) {
252 /* zero-sized transfer */
253 i2c_pnx_stop(alg_data
);
255 /* Disable master interrupts. */
256 iowrite32(ioread32(I2C_REG_CTL(alg_data
)) &
257 ~(mcntrl_afie
| mcntrl_naie
| mcntrl_drmie
),
258 I2C_REG_CTL(alg_data
));
261 del_timer_sync(&alg_data
->mif
.timer
);
262 dev_dbg(&alg_data
->adapter
.dev
,
263 "%s(): Waking up xfer routine after zero-xfer.\n",
266 complete(&alg_data
->mif
.complete
);
269 dev_dbg(&alg_data
->adapter
.dev
, "%s(): exiting: stat = %04x.\n",
270 __func__
, ioread32(I2C_REG_STS(alg_data
)));
276 * i2c_pnx_master_rcv - receive data from slave
277 * @adap: pointer to I2C adapter structure
279 * Reads one byte data from the slave
281 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data
*alg_data
)
283 unsigned int val
= 0;
286 dev_dbg(&alg_data
->adapter
.dev
, "%s(): entering: stat = %04x.\n",
287 __func__
, ioread32(I2C_REG_STS(alg_data
)));
289 /* Check, whether there is already data,
290 * or we didn't 'ask' for it yet.
292 if (ioread32(I2C_REG_STS(alg_data
)) & mstatus_rfe
) {
293 /* 'Asking' is done asynchronously, e.g. dummy TX of several
294 * bytes is done before the first actual RX arrives in FIFO.
295 * Therefore, ordered bytes (via TX) are counted separately.
297 if (alg_data
->mif
.order
) {
298 dev_dbg(&alg_data
->adapter
.dev
,
299 "%s(): Write dummy data to fill Rx-fifo...\n",
302 if (alg_data
->mif
.order
== 1) {
303 /* Last byte, do not acknowledge next rcv. */
307 * Enable interrupt RFDAIE (data in Rx fifo),
308 * and disable DRMIE (need data for Tx)
310 ctl
= ioread32(I2C_REG_CTL(alg_data
));
311 ctl
|= mcntrl_rffie
| mcntrl_daie
;
312 ctl
&= ~mcntrl_drmie
;
313 iowrite32(ctl
, I2C_REG_CTL(alg_data
));
317 * Now we'll 'ask' for data:
318 * For each byte we want to receive, we must
319 * write a (dummy) byte to the Tx-FIFO.
321 iowrite32(val
, I2C_REG_TX(alg_data
));
322 alg_data
->mif
.order
--;
328 if (alg_data
->mif
.len
> 0) {
329 val
= ioread32(I2C_REG_RX(alg_data
));
330 *alg_data
->mif
.buf
++ = (u8
) (val
& 0xff);
331 dev_dbg(&alg_data
->adapter
.dev
, "%s(): rcv 0x%x [%d]\n",
332 __func__
, val
, alg_data
->mif
.len
);
335 if (alg_data
->mif
.len
== 0) {
337 /* Wait until the STOP is seen. */
338 if (wait_timeout(alg_data
))
339 dev_err(&alg_data
->adapter
.dev
,
340 "The bus is still active after timeout\n");
342 /* Disable master interrupts */
343 ctl
= ioread32(I2C_REG_CTL(alg_data
));
344 ctl
&= ~(mcntrl_afie
| mcntrl_naie
| mcntrl_rffie
|
345 mcntrl_drmie
| mcntrl_daie
);
346 iowrite32(ctl
, I2C_REG_CTL(alg_data
));
349 del_timer_sync(&alg_data
->mif
.timer
);
350 complete(&alg_data
->mif
.complete
);
354 dev_dbg(&alg_data
->adapter
.dev
, "%s(): exiting: stat = %04x.\n",
355 __func__
, ioread32(I2C_REG_STS(alg_data
)));
360 static irqreturn_t
i2c_pnx_interrupt(int irq
, void *dev_id
)
362 struct i2c_pnx_algo_data
*alg_data
= dev_id
;
365 dev_dbg(&alg_data
->adapter
.dev
,
366 "%s(): mstat = %x mctrl = %x, mode = %d\n",
368 ioread32(I2C_REG_STS(alg_data
)),
369 ioread32(I2C_REG_CTL(alg_data
)),
371 stat
= ioread32(I2C_REG_STS(alg_data
));
373 /* let's see what kind of event this is */
374 if (stat
& mstatus_afi
) {
375 /* We lost arbitration in the midst of a transfer */
376 alg_data
->mif
.ret
= -EIO
;
378 /* Disable master interrupts. */
379 ctl
= ioread32(I2C_REG_CTL(alg_data
));
380 ctl
&= ~(mcntrl_afie
| mcntrl_naie
| mcntrl_rffie
|
382 iowrite32(ctl
, I2C_REG_CTL(alg_data
));
384 /* Stop timer, to prevent timeout. */
385 del_timer_sync(&alg_data
->mif
.timer
);
386 complete(&alg_data
->mif
.complete
);
387 } else if (stat
& mstatus_nai
) {
388 /* Slave did not acknowledge, generate a STOP */
389 dev_dbg(&alg_data
->adapter
.dev
,
390 "%s(): Slave did not acknowledge, generating a STOP.\n",
392 i2c_pnx_stop(alg_data
);
394 /* Disable master interrupts. */
395 ctl
= ioread32(I2C_REG_CTL(alg_data
));
396 ctl
&= ~(mcntrl_afie
| mcntrl_naie
| mcntrl_rffie
|
398 iowrite32(ctl
, I2C_REG_CTL(alg_data
));
400 /* Our return value. */
401 alg_data
->mif
.ret
= -EIO
;
403 /* Stop timer, to prevent timeout. */
404 del_timer_sync(&alg_data
->mif
.timer
);
405 complete(&alg_data
->mif
.complete
);
409 * - Master Tx needs data.
410 * - There is data in the Rx-fifo
411 * The latter is only the case if we have requested for data,
412 * via a dummy write. (See 'i2c_pnx_master_rcv'.)
413 * We therefore check, as a sanity check, whether that interrupt
416 if ((stat
& mstatus_drmi
) || !(stat
& mstatus_rfe
)) {
417 if (alg_data
->mif
.mode
== I2C_SMBUS_WRITE
) {
418 i2c_pnx_master_xmit(alg_data
);
419 } else if (alg_data
->mif
.mode
== I2C_SMBUS_READ
) {
420 i2c_pnx_master_rcv(alg_data
);
425 /* Clear TDI and AFI bits */
426 stat
= ioread32(I2C_REG_STS(alg_data
));
427 iowrite32(stat
| mstatus_tdi
| mstatus_afi
, I2C_REG_STS(alg_data
));
429 dev_dbg(&alg_data
->adapter
.dev
,
430 "%s(): exiting, stat = %x ctrl = %x.\n",
431 __func__
, ioread32(I2C_REG_STS(alg_data
)),
432 ioread32(I2C_REG_CTL(alg_data
)));
437 static void i2c_pnx_timeout(unsigned long data
)
439 struct i2c_pnx_algo_data
*alg_data
= (struct i2c_pnx_algo_data
*)data
;
442 dev_err(&alg_data
->adapter
.dev
,
443 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
444 ioread32(I2C_REG_STS(alg_data
)),
445 ioread32(I2C_REG_CTL(alg_data
)));
447 /* Reset master and disable interrupts */
448 ctl
= ioread32(I2C_REG_CTL(alg_data
));
449 ctl
&= ~(mcntrl_afie
| mcntrl_naie
| mcntrl_rffie
| mcntrl_drmie
);
450 iowrite32(ctl
, I2C_REG_CTL(alg_data
));
453 iowrite32(ctl
, I2C_REG_CTL(alg_data
));
454 wait_reset(alg_data
);
455 alg_data
->mif
.ret
= -EIO
;
456 complete(&alg_data
->mif
.complete
);
459 static inline void bus_reset_if_active(struct i2c_pnx_algo_data
*alg_data
)
463 if ((stat
= ioread32(I2C_REG_STS(alg_data
))) & mstatus_active
) {
464 dev_err(&alg_data
->adapter
.dev
,
465 "%s: Bus is still active after xfer. Reset it...\n",
466 alg_data
->adapter
.name
);
467 iowrite32(ioread32(I2C_REG_CTL(alg_data
)) | mcntrl_reset
,
468 I2C_REG_CTL(alg_data
));
469 wait_reset(alg_data
);
470 } else if (!(stat
& mstatus_rfe
) || !(stat
& mstatus_tfe
)) {
471 /* If there is data in the fifo's after transfer,
472 * flush fifo's by reset.
474 iowrite32(ioread32(I2C_REG_CTL(alg_data
)) | mcntrl_reset
,
475 I2C_REG_CTL(alg_data
));
476 wait_reset(alg_data
);
477 } else if (stat
& mstatus_nai
) {
478 iowrite32(ioread32(I2C_REG_CTL(alg_data
)) | mcntrl_reset
,
479 I2C_REG_CTL(alg_data
));
480 wait_reset(alg_data
);
485 * i2c_pnx_xfer - generic transfer entry point
486 * @adap: pointer to I2C adapter structure
487 * @msgs: array of messages
488 * @num: number of messages
490 * Initiates the transfer
493 i2c_pnx_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
495 struct i2c_msg
*pmsg
;
496 int rc
= 0, completed
= 0, i
;
497 struct i2c_pnx_algo_data
*alg_data
= adap
->algo_data
;
498 u32 stat
= ioread32(I2C_REG_STS(alg_data
));
500 dev_dbg(&alg_data
->adapter
.dev
,
501 "%s(): entering: %d messages, stat = %04x.\n",
502 __func__
, num
, ioread32(I2C_REG_STS(alg_data
)));
504 bus_reset_if_active(alg_data
);
506 /* Process transactions in a loop. */
507 for (i
= 0; rc
>= 0 && i
< num
; i
++) {
513 if (pmsg
->flags
& I2C_M_TEN
) {
514 dev_err(&alg_data
->adapter
.dev
,
515 "%s: 10 bits addr not supported!\n",
516 alg_data
->adapter
.name
);
521 alg_data
->mif
.buf
= pmsg
->buf
;
522 alg_data
->mif
.len
= pmsg
->len
;
523 alg_data
->mif
.order
= pmsg
->len
;
524 alg_data
->mif
.mode
= (pmsg
->flags
& I2C_M_RD
) ?
525 I2C_SMBUS_READ
: I2C_SMBUS_WRITE
;
526 alg_data
->mif
.ret
= 0;
527 alg_data
->last
= (i
== num
- 1);
529 dev_dbg(&alg_data
->adapter
.dev
, "%s(): mode %d, %d bytes\n",
530 __func__
, alg_data
->mif
.mode
, alg_data
->mif
.len
);
532 i2c_pnx_arm_timer(alg_data
);
534 /* initialize the completion var */
535 init_completion(&alg_data
->mif
.complete
);
537 /* Enable master interrupt */
538 iowrite32(ioread32(I2C_REG_CTL(alg_data
)) | mcntrl_afie
|
539 mcntrl_naie
| mcntrl_drmie
,
540 I2C_REG_CTL(alg_data
));
542 /* Put start-code and slave-address on the bus. */
543 rc
= i2c_pnx_start(addr
, alg_data
);
547 /* Wait for completion */
548 wait_for_completion(&alg_data
->mif
.complete
);
550 if (!(rc
= alg_data
->mif
.ret
))
552 dev_dbg(&alg_data
->adapter
.dev
,
553 "%s(): Complete, return code = %d.\n",
556 /* Clear TDI and AFI bits in case they are set. */
557 if ((stat
= ioread32(I2C_REG_STS(alg_data
))) & mstatus_tdi
) {
558 dev_dbg(&alg_data
->adapter
.dev
,
559 "%s: TDI still set... clearing now.\n",
560 alg_data
->adapter
.name
);
561 iowrite32(stat
, I2C_REG_STS(alg_data
));
563 if ((stat
= ioread32(I2C_REG_STS(alg_data
))) & mstatus_afi
) {
564 dev_dbg(&alg_data
->adapter
.dev
,
565 "%s: AFI still set... clearing now.\n",
566 alg_data
->adapter
.name
);
567 iowrite32(stat
, I2C_REG_STS(alg_data
));
571 bus_reset_if_active(alg_data
);
573 /* Cleanup to be sure... */
574 alg_data
->mif
.buf
= NULL
;
575 alg_data
->mif
.len
= 0;
576 alg_data
->mif
.order
= 0;
578 dev_dbg(&alg_data
->adapter
.dev
, "%s(): exiting, stat = %x\n",
579 __func__
, ioread32(I2C_REG_STS(alg_data
)));
581 if (completed
!= num
)
582 return ((rc
< 0) ? rc
: -EREMOTEIO
);
587 static u32
i2c_pnx_func(struct i2c_adapter
*adapter
)
589 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
592 static struct i2c_algorithm pnx_algorithm
= {
593 .master_xfer
= i2c_pnx_xfer
,
594 .functionality
= i2c_pnx_func
,
597 #ifdef CONFIG_PM_SLEEP
598 static int i2c_pnx_controller_suspend(struct device
*dev
)
600 struct i2c_pnx_algo_data
*alg_data
= dev_get_drvdata(dev
);
602 clk_disable(alg_data
->clk
);
607 static int i2c_pnx_controller_resume(struct device
*dev
)
609 struct i2c_pnx_algo_data
*alg_data
= dev_get_drvdata(dev
);
611 return clk_enable(alg_data
->clk
);
614 static SIMPLE_DEV_PM_OPS(i2c_pnx_pm
,
615 i2c_pnx_controller_suspend
, i2c_pnx_controller_resume
);
616 #define PNX_I2C_PM (&i2c_pnx_pm)
618 #define PNX_I2C_PM NULL
621 static int i2c_pnx_probe(struct platform_device
*pdev
)
625 struct i2c_pnx_algo_data
*alg_data
;
627 struct resource
*res
;
628 u32 speed
= I2C_PNX_SPEED_KHZ_DEFAULT
* 1000;
630 alg_data
= kzalloc(sizeof(*alg_data
), GFP_KERNEL
);
636 platform_set_drvdata(pdev
, alg_data
);
638 alg_data
->adapter
.dev
.parent
= &pdev
->dev
;
639 alg_data
->adapter
.algo
= &pnx_algorithm
;
640 alg_data
->adapter
.algo_data
= alg_data
;
641 alg_data
->adapter
.nr
= pdev
->id
;
643 alg_data
->timeout
= I2C_PNX_TIMEOUT_DEFAULT
;
645 alg_data
->adapter
.dev
.of_node
= of_node_get(pdev
->dev
.of_node
);
646 if (pdev
->dev
.of_node
) {
647 of_property_read_u32(pdev
->dev
.of_node
, "clock-frequency",
650 * At this point, it is planned to add an OF timeout property.
651 * As soon as there is a consensus about how to call and handle
652 * this, sth. like the following can be put here:
654 * of_property_read_u32(pdev->dev.of_node, "timeout",
655 * &alg_data->timeout);
659 alg_data
->clk
= clk_get(&pdev
->dev
, NULL
);
660 if (IS_ERR(alg_data
->clk
)) {
661 ret
= PTR_ERR(alg_data
->clk
);
665 init_timer(&alg_data
->mif
.timer
);
666 alg_data
->mif
.timer
.function
= i2c_pnx_timeout
;
667 alg_data
->mif
.timer
.data
= (unsigned long)alg_data
;
669 snprintf(alg_data
->adapter
.name
, sizeof(alg_data
->adapter
.name
),
672 /* Register I/O resource */
673 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
675 dev_err(&pdev
->dev
, "Unable to get mem resource.\n");
679 if (!request_mem_region(res
->start
, I2C_PNX_REGION_SIZE
,
682 "I/O region 0x%08x for I2C already in use.\n",
688 alg_data
->base
= res
->start
;
689 alg_data
->ioaddr
= ioremap(res
->start
, I2C_PNX_REGION_SIZE
);
690 if (!alg_data
->ioaddr
) {
691 dev_err(&pdev
->dev
, "Couldn't ioremap I2C I/O region\n");
696 ret
= clk_enable(alg_data
->clk
);
700 freq
= clk_get_rate(alg_data
->clk
);
703 * Clock Divisor High This value is the number of system clocks
704 * the serial clock (SCL) will be high.
705 * For example, if the system clock period is 50 ns and the maximum
706 * desired serial period is 10000 ns (100 kHz), then CLKHI would be
707 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
708 * programmed into CLKHI will vary from this slightly due to
709 * variations in the output pad's rise and fall times as well as
710 * the deglitching filter length.
713 tmp
= (freq
/ speed
) / 2 - 2;
716 iowrite32(tmp
, I2C_REG_CKH(alg_data
));
717 iowrite32(tmp
, I2C_REG_CKL(alg_data
));
719 iowrite32(mcntrl_reset
, I2C_REG_CTL(alg_data
));
720 if (wait_reset(alg_data
)) {
724 init_completion(&alg_data
->mif
.complete
);
726 alg_data
->irq
= platform_get_irq(pdev
, 0);
727 if (alg_data
->irq
< 0) {
728 dev_err(&pdev
->dev
, "Failed to get IRQ from platform resource\n");
732 ret
= request_irq(alg_data
->irq
, i2c_pnx_interrupt
,
733 0, pdev
->name
, alg_data
);
737 /* Register this adapter with the I2C subsystem */
738 ret
= i2c_add_numbered_adapter(&alg_data
->adapter
);
740 dev_err(&pdev
->dev
, "I2C: Failed to add bus\n");
744 dev_dbg(&pdev
->dev
, "%s: Master at %#8x, irq %d.\n",
745 alg_data
->adapter
.name
, res
->start
, alg_data
->irq
);
750 free_irq(alg_data
->irq
, alg_data
);
752 clk_disable(alg_data
->clk
);
754 iounmap(alg_data
->ioaddr
);
756 release_mem_region(res
->start
, I2C_PNX_REGION_SIZE
);
758 clk_put(alg_data
->clk
);
765 static int i2c_pnx_remove(struct platform_device
*pdev
)
767 struct i2c_pnx_algo_data
*alg_data
= platform_get_drvdata(pdev
);
769 free_irq(alg_data
->irq
, alg_data
);
770 i2c_del_adapter(&alg_data
->adapter
);
771 clk_disable(alg_data
->clk
);
772 iounmap(alg_data
->ioaddr
);
773 release_mem_region(alg_data
->base
, I2C_PNX_REGION_SIZE
);
774 clk_put(alg_data
->clk
);
781 static const struct of_device_id i2c_pnx_of_match
[] = {
782 { .compatible
= "nxp,pnx-i2c" },
785 MODULE_DEVICE_TABLE(of
, i2c_pnx_of_match
);
788 static struct platform_driver i2c_pnx_driver
= {
791 .owner
= THIS_MODULE
,
792 .of_match_table
= of_match_ptr(i2c_pnx_of_match
),
795 .probe
= i2c_pnx_probe
,
796 .remove
= i2c_pnx_remove
,
799 static int __init
i2c_adap_pnx_init(void)
801 return platform_driver_register(&i2c_pnx_driver
);
804 static void __exit
i2c_adap_pnx_exit(void)
806 platform_driver_unregister(&i2c_pnx_driver
);
809 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
810 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
811 MODULE_LICENSE("GPL");
812 MODULE_ALIAS("platform:pnx-i2c");
814 /* We need to make sure I2C is initialized before USB */
815 subsys_initcall(i2c_adap_pnx_init
);
816 module_exit(i2c_adap_pnx_exit
);