1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
9 #include <asm/io_apic.h>
12 #include <linux/intel-iommu.h>
13 #include <acpi/acpi.h>
14 #include <asm/irq_remapping.h>
15 #include <asm/pci-direct.h>
16 #include <asm/msidef.h>
18 #include "irq_remapping.h"
21 struct intel_iommu
*iommu
;
23 unsigned int bus
; /* PCI bus number */
24 unsigned int devfn
; /* PCI devfn number */
28 struct intel_iommu
*iommu
;
34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
35 #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
37 static struct ioapic_scope ir_ioapic
[MAX_IO_APICS
];
38 static struct hpet_scope ir_hpet
[MAX_HPET_TBS
];
39 static int ir_ioapic_num
, ir_hpet_num
;
41 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock
);
43 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
45 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
46 return cfg
? &cfg
->irq_2_iommu
: NULL
;
49 int get_irte(int irq
, struct irte
*entry
)
51 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
55 if (!entry
|| !irq_iommu
)
58 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
60 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
61 *entry
= *(irq_iommu
->iommu
->ir_table
->base
+ index
);
63 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
67 static int alloc_irte(struct intel_iommu
*iommu
, int irq
, u16 count
)
69 struct ir_table
*table
= iommu
->ir_table
;
70 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
71 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
72 u16 index
, start_index
;
73 unsigned int mask
= 0;
77 if (!count
|| !irq_iommu
)
81 * start the IRTE search from index 0.
83 index
= start_index
= 0;
86 count
= __roundup_pow_of_two(count
);
90 if (mask
> ecap_max_handle_mask(iommu
->ecap
)) {
92 "Requested mask %x exceeds the max invalidation handle"
93 " mask value %Lx\n", mask
,
94 ecap_max_handle_mask(iommu
->ecap
));
98 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
100 for (i
= index
; i
< index
+ count
; i
++)
101 if (table
->base
[i
].present
)
103 /* empty index found */
104 if (i
== index
+ count
)
107 index
= (index
+ count
) % INTR_REMAP_TABLE_ENTRIES
;
109 if (index
== start_index
) {
110 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
111 printk(KERN_ERR
"can't allocate an IRTE\n");
116 for (i
= index
; i
< index
+ count
; i
++)
117 table
->base
[i
].present
= 1;
120 irq_iommu
->iommu
= iommu
;
121 irq_iommu
->irte_index
= index
;
122 irq_iommu
->sub_handle
= 0;
123 irq_iommu
->irte_mask
= mask
;
125 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
130 static int qi_flush_iec(struct intel_iommu
*iommu
, int index
, int mask
)
134 desc
.low
= QI_IEC_IIDEX(index
) | QI_IEC_TYPE
| QI_IEC_IM(mask
)
138 return qi_submit_sync(&desc
, iommu
);
141 static int map_irq_to_irte_handle(int irq
, u16
*sub_handle
)
143 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
150 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
151 *sub_handle
= irq_iommu
->sub_handle
;
152 index
= irq_iommu
->irte_index
;
153 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
157 static int set_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
, u16 subhandle
)
159 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
160 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
166 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
169 irq_iommu
->iommu
= iommu
;
170 irq_iommu
->irte_index
= index
;
171 irq_iommu
->sub_handle
= subhandle
;
172 irq_iommu
->irte_mask
= 0;
174 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
179 static int modify_irte(int irq
, struct irte
*irte_modified
)
181 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
182 struct intel_iommu
*iommu
;
190 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
192 iommu
= irq_iommu
->iommu
;
194 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
195 irte
= &iommu
->ir_table
->base
[index
];
197 set_64bit(&irte
->low
, irte_modified
->low
);
198 set_64bit(&irte
->high
, irte_modified
->high
);
199 __iommu_flush_cache(iommu
, irte
, sizeof(*irte
));
201 rc
= qi_flush_iec(iommu
, index
, 0);
202 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
207 static struct intel_iommu
*map_hpet_to_ir(u8 hpet_id
)
211 for (i
= 0; i
< MAX_HPET_TBS
; i
++)
212 if (ir_hpet
[i
].id
== hpet_id
)
213 return ir_hpet
[i
].iommu
;
217 static struct intel_iommu
*map_ioapic_to_ir(int apic
)
221 for (i
= 0; i
< MAX_IO_APICS
; i
++)
222 if (ir_ioapic
[i
].id
== apic
)
223 return ir_ioapic
[i
].iommu
;
227 static struct intel_iommu
*map_dev_to_ir(struct pci_dev
*dev
)
229 struct dmar_drhd_unit
*drhd
;
231 drhd
= dmar_find_matched_drhd_unit(dev
);
238 static int clear_entries(struct irq_2_iommu
*irq_iommu
)
240 struct irte
*start
, *entry
, *end
;
241 struct intel_iommu
*iommu
;
244 if (irq_iommu
->sub_handle
)
247 iommu
= irq_iommu
->iommu
;
248 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
250 start
= iommu
->ir_table
->base
+ index
;
251 end
= start
+ (1 << irq_iommu
->irte_mask
);
253 for (entry
= start
; entry
< end
; entry
++) {
254 set_64bit(&entry
->low
, 0);
255 set_64bit(&entry
->high
, 0);
258 return qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
261 static int free_irte(int irq
)
263 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
270 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
272 rc
= clear_entries(irq_iommu
);
274 irq_iommu
->iommu
= NULL
;
275 irq_iommu
->irte_index
= 0;
276 irq_iommu
->sub_handle
= 0;
277 irq_iommu
->irte_mask
= 0;
279 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
285 * source validation type
287 #define SVT_NO_VERIFY 0x0 /* no verification is required */
288 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
289 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
292 * source-id qualifier
294 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
295 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
296 * the third least significant bit
298 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
299 * the second and third least significant bits
301 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
302 * the least three significant bits
306 * set SVT, SQ and SID fields of irte to verify
307 * source ids of interrupt requests
309 static void set_irte_sid(struct irte
*irte
, unsigned int svt
,
310 unsigned int sq
, unsigned int sid
)
312 if (disable_sourceid_checking
)
319 static int set_ioapic_sid(struct irte
*irte
, int apic
)
327 for (i
= 0; i
< MAX_IO_APICS
; i
++) {
328 if (ir_ioapic
[i
].id
== apic
) {
329 sid
= (ir_ioapic
[i
].bus
<< 8) | ir_ioapic
[i
].devfn
;
335 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic
);
339 set_irte_sid(irte
, 1, 0, sid
);
344 static int set_hpet_sid(struct irte
*irte
, u8 id
)
352 for (i
= 0; i
< MAX_HPET_TBS
; i
++) {
353 if (ir_hpet
[i
].id
== id
) {
354 sid
= (ir_hpet
[i
].bus
<< 8) | ir_hpet
[i
].devfn
;
360 pr_warning("Failed to set source-id of HPET block (%d)\n", id
);
365 * Should really use SQ_ALL_16. Some platforms are broken.
366 * While we figure out the right quirks for these broken platforms, use
367 * SQ_13_IGNORE_3 for now.
369 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_13_IGNORE_3
, sid
);
374 static int set_msi_sid(struct irte
*irte
, struct pci_dev
*dev
)
376 struct pci_dev
*bridge
;
381 /* PCIe device or Root Complex integrated PCI device */
382 if (pci_is_pcie(dev
) || !dev
->bus
->parent
) {
383 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
,
384 (dev
->bus
->number
<< 8) | dev
->devfn
);
388 bridge
= pci_find_upstream_pcie_bridge(dev
);
390 if (pci_is_pcie(bridge
))/* this is a PCIe-to-PCI/PCIX bridge */
391 set_irte_sid(irte
, SVT_VERIFY_BUS
, SQ_ALL_16
,
392 (bridge
->bus
->number
<< 8) | dev
->bus
->number
);
393 else /* this is a legacy PCI bridge */
394 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
,
395 (bridge
->bus
->number
<< 8) | bridge
->devfn
);
401 static void iommu_set_irq_remapping(struct intel_iommu
*iommu
, int mode
)
407 addr
= virt_to_phys((void *)iommu
->ir_table
->base
);
409 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
411 dmar_writeq(iommu
->reg
+ DMAR_IRTA_REG
,
412 (addr
) | IR_X2APIC_MODE(mode
) | INTR_REMAP_TABLE_REG_SIZE
);
414 /* Set interrupt-remapping table pointer */
415 iommu
->gcmd
|= DMA_GCMD_SIRTP
;
416 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
418 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
419 readl
, (sts
& DMA_GSTS_IRTPS
), sts
);
420 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
423 * global invalidation of interrupt entry cache before enabling
424 * interrupt-remapping.
426 qi_global_iec(iommu
);
428 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
430 /* Enable interrupt-remapping */
431 iommu
->gcmd
|= DMA_GCMD_IRE
;
432 iommu
->gcmd
&= ~DMA_GCMD_CFI
; /* Block compatibility-format MSIs */
433 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
435 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
436 readl
, (sts
& DMA_GSTS_IRES
), sts
);
439 * With CFI clear in the Global Command register, we should be
440 * protected from dangerous (i.e. compatibility) interrupts
441 * regardless of x2apic status. Check just to be sure.
443 if (sts
& DMA_GSTS_CFIS
)
445 "Compatibility-format IRQs enabled despite intr remapping;\n"
446 "you are vulnerable to IRQ injection.\n");
448 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
452 static int intel_setup_irq_remapping(struct intel_iommu
*iommu
, int mode
)
454 struct ir_table
*ir_table
;
457 ir_table
= iommu
->ir_table
= kzalloc(sizeof(struct ir_table
),
460 if (!iommu
->ir_table
)
463 pages
= alloc_pages_node(iommu
->node
, GFP_ATOMIC
| __GFP_ZERO
,
464 INTR_REMAP_PAGE_ORDER
);
467 printk(KERN_ERR
"failed to allocate pages of order %d\n",
468 INTR_REMAP_PAGE_ORDER
);
469 kfree(iommu
->ir_table
);
473 ir_table
->base
= page_address(pages
);
475 iommu_set_irq_remapping(iommu
, mode
);
480 * Disable Interrupt Remapping.
482 static void iommu_disable_irq_remapping(struct intel_iommu
*iommu
)
487 if (!ecap_ir_support(iommu
->ecap
))
491 * global invalidation of interrupt entry cache before disabling
492 * interrupt-remapping.
494 qi_global_iec(iommu
);
496 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
498 sts
= dmar_readq(iommu
->reg
+ DMAR_GSTS_REG
);
499 if (!(sts
& DMA_GSTS_IRES
))
502 iommu
->gcmd
&= ~DMA_GCMD_IRE
;
503 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
505 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
506 readl
, !(sts
& DMA_GSTS_IRES
), sts
);
509 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
512 static int __init
dmar_x2apic_optout(void)
514 struct acpi_table_dmar
*dmar
;
515 dmar
= (struct acpi_table_dmar
*)dmar_tbl
;
516 if (!dmar
|| no_x2apic_optout
)
518 return dmar
->flags
& DMAR_X2APIC_OPT_OUT
;
521 static int __init
intel_irq_remapping_supported(void)
523 struct dmar_drhd_unit
*drhd
;
525 if (disable_irq_remap
)
527 if (irq_remap_broken
) {
529 "This system BIOS has enabled interrupt remapping\n"
530 "on a chipset that contains an erratum making that\n"
531 "feature unstable. To maintain system stability\n"
532 "interrupt remapping is being disabled. Please\n"
533 "contact your BIOS vendor for an update\n");
534 add_taint(TAINT_FIRMWARE_WORKAROUND
, LOCKDEP_STILL_OK
);
535 disable_irq_remap
= 1;
539 if (!dmar_ir_support())
542 for_each_drhd_unit(drhd
) {
543 struct intel_iommu
*iommu
= drhd
->iommu
;
545 if (!ecap_ir_support(iommu
->ecap
))
552 static int __init
intel_enable_irq_remapping(void)
554 struct dmar_drhd_unit
*drhd
;
559 x2apic_present
= x2apic_supported();
561 if (parse_ioapics_under_ir() != 1) {
562 printk(KERN_INFO
"Not enable interrupt remapping\n");
566 if (x2apic_present
) {
567 eim
= !dmar_x2apic_optout();
570 "Your BIOS is broken and requested that x2apic be disabled.\n"
571 "This will slightly decrease performance.\n"
572 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
575 for_each_drhd_unit(drhd
) {
576 struct intel_iommu
*iommu
= drhd
->iommu
;
579 * If the queued invalidation is already initialized,
580 * shouldn't disable it.
586 * Clear previous faults.
588 dmar_fault(-1, iommu
);
591 * Disable intr remapping and queued invalidation, if already
592 * enabled prior to OS handover.
594 iommu_disable_irq_remapping(iommu
);
596 dmar_disable_qi(iommu
);
600 * check for the Interrupt-remapping support
602 for_each_drhd_unit(drhd
) {
603 struct intel_iommu
*iommu
= drhd
->iommu
;
605 if (!ecap_ir_support(iommu
->ecap
))
608 if (eim
&& !ecap_eim_support(iommu
->ecap
)) {
609 printk(KERN_INFO
"DRHD %Lx: EIM not supported by DRHD, "
610 " ecap %Lx\n", drhd
->reg_base_addr
, iommu
->ecap
);
616 * Enable queued invalidation for all the DRHD's.
618 for_each_drhd_unit(drhd
) {
620 struct intel_iommu
*iommu
= drhd
->iommu
;
621 ret
= dmar_enable_qi(iommu
);
624 printk(KERN_ERR
"DRHD %Lx: failed to enable queued, "
625 " invalidation, ecap %Lx, ret %d\n",
626 drhd
->reg_base_addr
, iommu
->ecap
, ret
);
632 * Setup Interrupt-remapping for all the DRHD's now.
634 for_each_drhd_unit(drhd
) {
635 struct intel_iommu
*iommu
= drhd
->iommu
;
637 if (!ecap_ir_support(iommu
->ecap
))
640 if (intel_setup_irq_remapping(iommu
, eim
))
649 irq_remapping_enabled
= 1;
652 * VT-d has a different layout for IO-APIC entries when
653 * interrupt remapping is enabled. So it needs a special routine
654 * to print IO-APIC entries for debugging purposes too.
656 x86_io_apic_ops
.print_entries
= intel_ir_io_apic_print_entries
;
658 pr_info("Enabled IRQ remapping in %s mode\n", eim
? "x2apic" : "xapic");
660 return eim
? IRQ_REMAP_X2APIC_MODE
: IRQ_REMAP_XAPIC_MODE
;
664 * handle error condition gracefully here!
668 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
673 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope
*scope
,
674 struct intel_iommu
*iommu
)
676 struct acpi_dmar_pci_path
*path
;
681 path
= (struct acpi_dmar_pci_path
*)(scope
+ 1);
682 count
= (scope
->length
- sizeof(struct acpi_dmar_device_scope
))
683 / sizeof(struct acpi_dmar_pci_path
);
685 while (--count
> 0) {
687 * Access PCI directly due to the PCI
688 * subsystem isn't initialized yet.
690 bus
= read_pci_config_byte(bus
, path
->dev
, path
->fn
,
694 ir_hpet
[ir_hpet_num
].bus
= bus
;
695 ir_hpet
[ir_hpet_num
].devfn
= PCI_DEVFN(path
->dev
, path
->fn
);
696 ir_hpet
[ir_hpet_num
].iommu
= iommu
;
697 ir_hpet
[ir_hpet_num
].id
= scope
->enumeration_id
;
701 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope
*scope
,
702 struct intel_iommu
*iommu
)
704 struct acpi_dmar_pci_path
*path
;
709 path
= (struct acpi_dmar_pci_path
*)(scope
+ 1);
710 count
= (scope
->length
- sizeof(struct acpi_dmar_device_scope
))
711 / sizeof(struct acpi_dmar_pci_path
);
713 while (--count
> 0) {
715 * Access PCI directly due to the PCI
716 * subsystem isn't initialized yet.
718 bus
= read_pci_config_byte(bus
, path
->dev
, path
->fn
,
723 ir_ioapic
[ir_ioapic_num
].bus
= bus
;
724 ir_ioapic
[ir_ioapic_num
].devfn
= PCI_DEVFN(path
->dev
, path
->fn
);
725 ir_ioapic
[ir_ioapic_num
].iommu
= iommu
;
726 ir_ioapic
[ir_ioapic_num
].id
= scope
->enumeration_id
;
730 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header
*header
,
731 struct intel_iommu
*iommu
)
733 struct acpi_dmar_hardware_unit
*drhd
;
734 struct acpi_dmar_device_scope
*scope
;
737 drhd
= (struct acpi_dmar_hardware_unit
*)header
;
739 start
= (void *)(drhd
+ 1);
740 end
= ((void *)drhd
) + header
->length
;
742 while (start
< end
) {
744 if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_IOAPIC
) {
745 if (ir_ioapic_num
== MAX_IO_APICS
) {
746 printk(KERN_WARNING
"Exceeded Max IO APICS\n");
750 printk(KERN_INFO
"IOAPIC id %d under DRHD base "
751 " 0x%Lx IOMMU %d\n", scope
->enumeration_id
,
752 drhd
->address
, iommu
->seq_id
);
754 ir_parse_one_ioapic_scope(scope
, iommu
);
755 } else if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_HPET
) {
756 if (ir_hpet_num
== MAX_HPET_TBS
) {
757 printk(KERN_WARNING
"Exceeded Max HPET blocks\n");
761 printk(KERN_INFO
"HPET id %d under DRHD base"
762 " 0x%Lx\n", scope
->enumeration_id
,
765 ir_parse_one_hpet_scope(scope
, iommu
);
767 start
+= scope
->length
;
774 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
777 int __init
parse_ioapics_under_ir(void)
779 struct dmar_drhd_unit
*drhd
;
780 int ir_supported
= 0;
783 for_each_drhd_unit(drhd
) {
784 struct intel_iommu
*iommu
= drhd
->iommu
;
786 if (ecap_ir_support(iommu
->ecap
)) {
787 if (ir_parse_ioapic_hpet_scope(drhd
->hdr
, iommu
))
797 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++) {
798 int ioapic_id
= mpc_ioapic_id(ioapic_idx
);
799 if (!map_ioapic_to_ir(ioapic_id
)) {
800 pr_err(FW_BUG
"ioapic %d has no mapping iommu, "
801 "interrupt remapping will be disabled\n",
810 int __init
ir_dev_scope_init(void)
812 if (!irq_remapping_enabled
)
815 return dmar_dev_scope_init();
817 rootfs_initcall(ir_dev_scope_init
);
819 static void disable_irq_remapping(void)
821 struct dmar_drhd_unit
*drhd
;
822 struct intel_iommu
*iommu
= NULL
;
825 * Disable Interrupt-remapping for all the DRHD's now.
827 for_each_iommu(iommu
, drhd
) {
828 if (!ecap_ir_support(iommu
->ecap
))
831 iommu_disable_irq_remapping(iommu
);
835 static int reenable_irq_remapping(int eim
)
837 struct dmar_drhd_unit
*drhd
;
839 struct intel_iommu
*iommu
= NULL
;
841 for_each_iommu(iommu
, drhd
)
843 dmar_reenable_qi(iommu
);
846 * Setup Interrupt-remapping for all the DRHD's now.
848 for_each_iommu(iommu
, drhd
) {
849 if (!ecap_ir_support(iommu
->ecap
))
852 /* Set up interrupt remapping for iommu.*/
853 iommu_set_irq_remapping(iommu
, eim
);
864 * handle error condition gracefully here!
869 static void prepare_irte(struct irte
*irte
, int vector
,
872 memset(irte
, 0, sizeof(*irte
));
875 irte
->dst_mode
= apic
->irq_dest_mode
;
877 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
878 * actual level or edge trigger will be setup in the IO-APIC
879 * RTE. This will help simplify level triggered irq migration.
880 * For more details, see the comments (in io_apic.c) explainig IO-APIC
881 * irq migration in the presence of interrupt-remapping.
883 irte
->trigger_mode
= 0;
884 irte
->dlvry_mode
= apic
->irq_delivery_mode
;
885 irte
->vector
= vector
;
886 irte
->dest_id
= IRTE_DEST(dest
);
887 irte
->redir_hint
= 1;
890 static int intel_setup_ioapic_entry(int irq
,
891 struct IO_APIC_route_entry
*route_entry
,
892 unsigned int destination
, int vector
,
893 struct io_apic_irq_attr
*attr
)
895 int ioapic_id
= mpc_ioapic_id(attr
->ioapic
);
896 struct intel_iommu
*iommu
= map_ioapic_to_ir(ioapic_id
);
897 struct IR_IO_APIC_route_entry
*entry
;
902 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id
);
906 entry
= (struct IR_IO_APIC_route_entry
*)route_entry
;
908 index
= alloc_irte(iommu
, irq
, 1);
910 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id
);
914 prepare_irte(&irte
, vector
, destination
);
916 /* Set source-id of interrupt request */
917 set_ioapic_sid(&irte
, ioapic_id
);
919 modify_irte(irq
, &irte
);
921 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"IOAPIC[%d]: "
922 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
923 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
924 "Avail:%X Vector:%02X Dest:%08X "
925 "SID:%04X SQ:%X SVT:%X)\n",
926 attr
->ioapic
, irte
.present
, irte
.fpd
, irte
.dst_mode
,
927 irte
.redir_hint
, irte
.trigger_mode
, irte
.dlvry_mode
,
928 irte
.avail
, irte
.vector
, irte
.dest_id
,
929 irte
.sid
, irte
.sq
, irte
.svt
);
931 memset(entry
, 0, sizeof(*entry
));
933 entry
->index2
= (index
>> 15) & 0x1;
936 entry
->index
= (index
& 0x7fff);
938 * IO-APIC RTE will be configured with virtual vector.
939 * irq handler will do the explicit EOI to the io-apic.
941 entry
->vector
= attr
->ioapic_pin
;
942 entry
->mask
= 0; /* enable IRQ */
943 entry
->trigger
= attr
->trigger
;
944 entry
->polarity
= attr
->polarity
;
946 /* Mask level triggered irqs.
947 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
956 * Migrate the IO-APIC irq in the presence of intr-remapping.
958 * For both level and edge triggered, irq migration is a simple atomic
959 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
961 * For level triggered, we eliminate the io-apic RTE modification (with the
962 * updated vector information), by using a virtual vector (io-apic pin number).
963 * Real vector that is used for interrupting cpu will be coming from
964 * the interrupt-remapping table entry.
966 * As the migration is a simple atomic update of IRTE, the same mechanism
967 * is used to migrate MSI irq's in the presence of interrupt-remapping.
970 intel_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
973 struct irq_cfg
*cfg
= data
->chip_data
;
974 unsigned int dest
, irq
= data
->irq
;
978 if (!config_enabled(CONFIG_SMP
))
981 if (!cpumask_intersects(mask
, cpu_online_mask
))
984 if (get_irte(irq
, &irte
))
987 err
= assign_irq_vector(irq
, cfg
, mask
);
991 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
, &dest
);
993 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
994 pr_err("Failed to recover vector for irq %d\n", irq
);
998 irte
.vector
= cfg
->vector
;
999 irte
.dest_id
= IRTE_DEST(dest
);
1002 * Atomically updates the IRTE with the new destination, vector
1003 * and flushes the interrupt entry cache.
1005 modify_irte(irq
, &irte
);
1008 * After this point, all the interrupts will start arriving
1009 * at the new destination. So, time to cleanup the previous
1010 * vector allocation.
1012 if (cfg
->move_in_progress
)
1013 send_cleanup_vector(cfg
);
1015 cpumask_copy(data
->affinity
, mask
);
1019 static void intel_compose_msi_msg(struct pci_dev
*pdev
,
1020 unsigned int irq
, unsigned int dest
,
1021 struct msi_msg
*msg
, u8 hpet_id
)
1023 struct irq_cfg
*cfg
;
1028 cfg
= irq_get_chip_data(irq
);
1030 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
1031 BUG_ON(ir_index
== -1);
1033 prepare_irte(&irte
, cfg
->vector
, dest
);
1035 /* Set source-id of interrupt request */
1037 set_msi_sid(&irte
, pdev
);
1039 set_hpet_sid(&irte
, hpet_id
);
1041 modify_irte(irq
, &irte
);
1043 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1044 msg
->data
= sub_handle
;
1045 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
1047 MSI_ADDR_IR_INDEX1(ir_index
) |
1048 MSI_ADDR_IR_INDEX2(ir_index
);
1052 * Map the PCI dev to the corresponding remapping hardware unit
1053 * and allocate 'nvec' consecutive interrupt-remapping table entries
1056 static int intel_msi_alloc_irq(struct pci_dev
*dev
, int irq
, int nvec
)
1058 struct intel_iommu
*iommu
;
1061 iommu
= map_dev_to_ir(dev
);
1064 "Unable to map PCI %s to iommu\n", pci_name(dev
));
1068 index
= alloc_irte(iommu
, irq
, nvec
);
1071 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
1078 static int intel_msi_setup_irq(struct pci_dev
*pdev
, unsigned int irq
,
1079 int index
, int sub_handle
)
1081 struct intel_iommu
*iommu
;
1083 iommu
= map_dev_to_ir(pdev
);
1087 * setup the mapping between the irq and the IRTE
1088 * base index, the sub_handle pointing to the
1089 * appropriate interrupt remap table entry.
1091 set_irte_irq(irq
, iommu
, index
, sub_handle
);
1096 static int intel_setup_hpet_msi(unsigned int irq
, unsigned int id
)
1098 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
1104 index
= alloc_irte(iommu
, irq
, 1);
1111 struct irq_remap_ops intel_irq_remap_ops
= {
1112 .supported
= intel_irq_remapping_supported
,
1113 .prepare
= dmar_table_init
,
1114 .enable
= intel_enable_irq_remapping
,
1115 .disable
= disable_irq_remapping
,
1116 .reenable
= reenable_irq_remapping
,
1117 .enable_faulting
= enable_drhd_fault_handling
,
1118 .setup_ioapic_entry
= intel_setup_ioapic_entry
,
1119 .set_affinity
= intel_ioapic_set_affinity
,
1120 .free_irq
= free_irte
,
1121 .compose_msi_msg
= intel_compose_msi_msg
,
1122 .msi_alloc_irq
= intel_msi_alloc_irq
,
1123 .msi_setup_irq
= intel_msi_setup_irq
,
1124 .setup_hpet_msi
= intel_setup_hpet_msi
,