2 * Driver for Intel MSIC
4 * Copyright (C) 2011, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
13 #include <linux/gpio.h>
15 #include <linux/module.h>
16 #include <linux/mfd/core.h>
17 #include <linux/mfd/intel_msic.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <asm/intel_scu_ipc.h>
23 #define MSIC_VENDOR(id) ((id >> 6) & 3)
24 #define MSIC_VERSION(id) (id & 0x3f)
25 #define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7))
26 #define MSIC_MINOR(id) (id & 7)
29 * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
30 * Since IRQ block starts from address 0x002 we need to substract that from
31 * the actual IRQ status register address.
33 #define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
34 #define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)
37 * The SCU hardware has limitation of 16 bytes per read/write buffer on
40 #define SCU_IPC_RWBUF_LIMIT 16
43 * struct intel_msic - an MSIC MFD instance
44 * @pdev: pointer to the platform device
46 * @version: chip version
47 * @irq_base: base address of the mapped MSIC SRAM interrupt tree
50 struct platform_device
*pdev
;
53 void __iomem
*irq_base
;
56 static struct resource msic_touch_resources
[] = {
58 .flags
= IORESOURCE_IRQ
,
62 static struct resource msic_adc_resources
[] = {
64 .flags
= IORESOURCE_IRQ
,
68 static struct resource msic_battery_resources
[] = {
70 .flags
= IORESOURCE_IRQ
,
74 static struct resource msic_gpio_resources
[] = {
76 .flags
= IORESOURCE_IRQ
,
80 static struct resource msic_audio_resources
[] = {
83 .flags
= IORESOURCE_IRQ
,
86 * We will pass IRQ_BASE to the driver now but this can be removed
87 * when/if the driver starts to use intel_msic_irq_read().
91 .flags
= IORESOURCE_MEM
,
92 .start
= MSIC_IRQ_STATUS_ACCDET
,
93 .end
= MSIC_IRQ_STATUS_ACCDET
,
97 static struct resource msic_hdmi_resources
[] = {
99 .flags
= IORESOURCE_IRQ
,
103 static struct resource msic_thermal_resources
[] = {
105 .flags
= IORESOURCE_IRQ
,
109 static struct resource msic_power_btn_resources
[] = {
111 .flags
= IORESOURCE_IRQ
,
115 static struct resource msic_ocd_resources
[] = {
117 .flags
= IORESOURCE_IRQ
,
122 * Devices that are part of the MSIC and are available via firmware
123 * populated SFI DEVS table.
125 static struct mfd_cell msic_devs
[] = {
126 [INTEL_MSIC_BLOCK_TOUCH
] = {
127 .name
= "msic_touch",
128 .num_resources
= ARRAY_SIZE(msic_touch_resources
),
129 .resources
= msic_touch_resources
,
131 [INTEL_MSIC_BLOCK_ADC
] = {
133 .num_resources
= ARRAY_SIZE(msic_adc_resources
),
134 .resources
= msic_adc_resources
,
136 [INTEL_MSIC_BLOCK_BATTERY
] = {
137 .name
= "msic_battery",
138 .num_resources
= ARRAY_SIZE(msic_battery_resources
),
139 .resources
= msic_battery_resources
,
141 [INTEL_MSIC_BLOCK_GPIO
] = {
143 .num_resources
= ARRAY_SIZE(msic_gpio_resources
),
144 .resources
= msic_gpio_resources
,
146 [INTEL_MSIC_BLOCK_AUDIO
] = {
147 .name
= "msic_audio",
148 .num_resources
= ARRAY_SIZE(msic_audio_resources
),
149 .resources
= msic_audio_resources
,
151 [INTEL_MSIC_BLOCK_HDMI
] = {
153 .num_resources
= ARRAY_SIZE(msic_hdmi_resources
),
154 .resources
= msic_hdmi_resources
,
156 [INTEL_MSIC_BLOCK_THERMAL
] = {
157 .name
= "msic_thermal",
158 .num_resources
= ARRAY_SIZE(msic_thermal_resources
),
159 .resources
= msic_thermal_resources
,
161 [INTEL_MSIC_BLOCK_POWER_BTN
] = {
162 .name
= "msic_power_btn",
163 .num_resources
= ARRAY_SIZE(msic_power_btn_resources
),
164 .resources
= msic_power_btn_resources
,
166 [INTEL_MSIC_BLOCK_OCD
] = {
168 .num_resources
= ARRAY_SIZE(msic_ocd_resources
),
169 .resources
= msic_ocd_resources
,
174 * Other MSIC related devices which are not directly available via SFI DEVS
175 * table. These can be pseudo devices, regulators etc. which are needed for
176 * different purposes.
178 * These devices appear only after the MSIC driver itself is initialized so
179 * we can guarantee that the SCU IPC interface is ready.
181 static struct mfd_cell msic_other_devs
[] = {
182 /* Audio codec in the MSIC */
190 * intel_msic_reg_read - read a single MSIC register
191 * @reg: register to read
192 * @val: register value is placed here
194 * Read a single register from MSIC. Returns %0 on success and negative
195 * errno in case of failure.
197 * Function may sleep.
199 int intel_msic_reg_read(unsigned short reg
, u8
*val
)
201 return intel_scu_ipc_ioread8(reg
, val
);
203 EXPORT_SYMBOL_GPL(intel_msic_reg_read
);
206 * intel_msic_reg_write - write a single MSIC register
207 * @reg: register to write
208 * @val: value to write to that register
210 * Write a single MSIC register. Returns 0 on success and negative
211 * errno in case of failure.
213 * Function may sleep.
215 int intel_msic_reg_write(unsigned short reg
, u8 val
)
217 return intel_scu_ipc_iowrite8(reg
, val
);
219 EXPORT_SYMBOL_GPL(intel_msic_reg_write
);
222 * intel_msic_reg_update - update a single MSIC register
223 * @reg: register to update
224 * @val: value to write to the register
225 * @mask: specifies which of the bits are updated (%0 = don't update,
228 * Perform an update to a register @reg. @mask is used to specify which
229 * bits are updated. Returns %0 in case of success and negative errno in
232 * Function may sleep.
234 int intel_msic_reg_update(unsigned short reg
, u8 val
, u8 mask
)
236 return intel_scu_ipc_update_register(reg
, val
, mask
);
238 EXPORT_SYMBOL_GPL(intel_msic_reg_update
);
241 * intel_msic_bulk_read - read an array of registers
242 * @reg: array of register addresses to read
243 * @buf: array where the read values are placed
244 * @count: number of registers to read
246 * Function reads @count registers from the MSIC using addresses passed in
247 * @reg. Read values are placed in @buf. Reads are performed atomically
250 * Returns %0 in case of success and negative errno in case of failure.
252 * Function may sleep.
254 int intel_msic_bulk_read(unsigned short *reg
, u8
*buf
, size_t count
)
256 if (WARN_ON(count
> SCU_IPC_RWBUF_LIMIT
))
259 return intel_scu_ipc_readv(reg
, buf
, count
);
261 EXPORT_SYMBOL_GPL(intel_msic_bulk_read
);
264 * intel_msic_bulk_write - write an array of values to the MSIC registers
265 * @reg: array of registers to write
266 * @buf: values to write to each register
267 * @count: number of registers to write
269 * Function writes @count registers in @buf to MSIC. Writes are performed
270 * atomically wrt MSIC. Returns %0 in case of success and negative errno in
273 * Function may sleep.
275 int intel_msic_bulk_write(unsigned short *reg
, u8
*buf
, size_t count
)
277 if (WARN_ON(count
> SCU_IPC_RWBUF_LIMIT
))
280 return intel_scu_ipc_writev(reg
, buf
, count
);
282 EXPORT_SYMBOL_GPL(intel_msic_bulk_write
);
285 * intel_msic_irq_read - read a register from an MSIC interrupt tree
286 * @msic: MSIC instance
287 * @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
288 * %INTEL_MSIC_RESETIRQ2)
289 * @val: value of the register is placed here
291 * This function can be used by an MSIC subdevice interrupt handler to read
292 * a register value from the MSIC interrupt tree. In this way subdevice
293 * drivers don't have to map in the interrupt tree themselves but can just
294 * call this function instead.
296 * Function doesn't sleep and is callable from interrupt context.
298 * Returns %-EINVAL if @reg is outside of the allowed register region.
300 int intel_msic_irq_read(struct intel_msic
*msic
, unsigned short reg
, u8
*val
)
302 if (WARN_ON(reg
< INTEL_MSIC_IRQLVL1
|| reg
> INTEL_MSIC_RESETIRQ2
))
305 *val
= readb(msic
->irq_base
+ (reg
- INTEL_MSIC_IRQLVL1
));
308 EXPORT_SYMBOL_GPL(intel_msic_irq_read
);
310 static int intel_msic_init_devices(struct intel_msic
*msic
)
312 struct platform_device
*pdev
= msic
->pdev
;
313 struct intel_msic_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
317 struct mfd_cell
*cell
= &msic_devs
[INTEL_MSIC_BLOCK_GPIO
];
319 cell
->platform_data
= pdata
->gpio
;
320 cell
->pdata_size
= sizeof(*pdata
->gpio
);
324 unsigned gpio
= pdata
->ocd
->gpio
;
326 ret
= devm_gpio_request_one(&pdev
->dev
, gpio
,
327 GPIOF_IN
, "ocd_gpio");
329 dev_err(&pdev
->dev
, "failed to register OCD GPIO\n");
333 ret
= gpio_to_irq(gpio
);
335 dev_err(&pdev
->dev
, "no IRQ number for OCD GPIO\n");
339 /* Update the IRQ number for the OCD */
340 pdata
->irq
[INTEL_MSIC_BLOCK_OCD
] = ret
;
343 for (i
= 0; i
< ARRAY_SIZE(msic_devs
); i
++) {
347 ret
= mfd_add_devices(&pdev
->dev
, -1, &msic_devs
[i
], 1, NULL
,
348 pdata
->irq
[i
], NULL
);
353 ret
= mfd_add_devices(&pdev
->dev
, 0, msic_other_devs
,
354 ARRAY_SIZE(msic_other_devs
), NULL
, 0, NULL
);
361 mfd_remove_devices(&pdev
->dev
);
366 static void intel_msic_remove_devices(struct intel_msic
*msic
)
368 struct platform_device
*pdev
= msic
->pdev
;
370 mfd_remove_devices(&pdev
->dev
);
373 static int intel_msic_probe(struct platform_device
*pdev
)
375 struct intel_msic_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
376 struct intel_msic
*msic
;
377 struct resource
*res
;
382 dev_err(&pdev
->dev
, "no platform data passed\n");
386 /* First validate that we have an MSIC in place */
387 ret
= intel_scu_ipc_ioread8(INTEL_MSIC_ID0
, &id0
);
389 dev_err(&pdev
->dev
, "failed to identify the MSIC chip (ID0)\n");
393 ret
= intel_scu_ipc_ioread8(INTEL_MSIC_ID1
, &id1
);
395 dev_err(&pdev
->dev
, "failed to identify the MSIC chip (ID1)\n");
399 if (MSIC_VENDOR(id0
) != MSIC_VENDOR(id1
)) {
400 dev_err(&pdev
->dev
, "invalid vendor ID: %x, %x\n", id0
, id1
);
404 msic
= devm_kzalloc(&pdev
->dev
, sizeof(*msic
), GFP_KERNEL
);
408 msic
->vendor
= MSIC_VENDOR(id0
);
409 msic
->version
= MSIC_VERSION(id0
);
413 * Map in the MSIC interrupt tree area in SRAM. This is exposed to
414 * the clients via intel_msic_irq_read().
416 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
417 msic
->irq_base
= devm_ioremap_resource(&pdev
->dev
, res
);
418 if (IS_ERR(msic
->irq_base
))
419 return PTR_ERR(msic
->irq_base
);
421 platform_set_drvdata(pdev
, msic
);
423 ret
= intel_msic_init_devices(msic
);
425 dev_err(&pdev
->dev
, "failed to initialize MSIC devices\n");
429 dev_info(&pdev
->dev
, "Intel MSIC version %c%d (vendor %#x)\n",
430 MSIC_MAJOR(msic
->version
), MSIC_MINOR(msic
->version
),
436 static int intel_msic_remove(struct platform_device
*pdev
)
438 struct intel_msic
*msic
= platform_get_drvdata(pdev
);
440 intel_msic_remove_devices(msic
);
445 static struct platform_driver intel_msic_driver
= {
446 .probe
= intel_msic_probe
,
447 .remove
= intel_msic_remove
,
449 .name
= "intel_msic",
450 .owner
= THIS_MODULE
,
454 module_platform_driver(intel_msic_driver
);
456 MODULE_DESCRIPTION("Driver for Intel MSIC");
457 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
458 MODULE_LICENSE("GPL");