1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * Roger Tseng <rogerable@realtek.com>
23 #include <linux/module.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/mfd/rtsx_pci.h>
30 static u8
rtl8411_get_ic_version(struct rtsx_pcr
*pcr
)
34 rtsx_pci_read_register(pcr
, SYS_VER
, &val
);
38 static int rtl8411b_is_qfn48(struct rtsx_pcr
*pcr
)
42 rtsx_pci_read_register(pcr
, RTL8411B_PACKAGE_MODE
, &val
);
50 static void rtl8411_fetch_vendor_settings(struct rtsx_pcr
*pcr
)
55 rtsx_pci_read_config_dword(pcr
, PCR_SETTING_REG1
, ®1
);
56 dev_dbg(&(pcr
->pci
->dev
), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1
, reg1
);
58 if (!rtsx_vendor_setting_valid(reg1
))
61 pcr
->aspm_en
= rtsx_reg_to_aspm(reg1
);
62 pcr
->sd30_drive_sel_1v8
=
63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1
));
64 pcr
->card_drive_sel
&= 0x3F;
65 pcr
->card_drive_sel
|= rtsx_reg_to_card_drive_sel(reg1
);
67 rtsx_pci_read_config_byte(pcr
, PCR_SETTING_REG3
, ®3
);
68 dev_dbg(&(pcr
->pci
->dev
), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3
, reg3
);
69 pcr
->sd30_drive_sel_3v3
= rtl8411_reg_to_sd30_drive_sel_3v3(reg3
);
72 static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr
*pcr
)
76 rtsx_pci_read_config_dword(pcr
, PCR_SETTING_REG1
, ®
);
77 dev_dbg(&(pcr
->pci
->dev
), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1
, reg
);
79 if (!rtsx_vendor_setting_valid(reg
))
82 pcr
->aspm_en
= rtsx_reg_to_aspm(reg
);
83 pcr
->sd30_drive_sel_1v8
=
84 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg
));
85 pcr
->sd30_drive_sel_3v3
=
86 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg
));
89 static void rtl8411_force_power_down(struct rtsx_pcr
*pcr
, u8 pm_state
)
91 rtsx_pci_write_register(pcr
, FPDCTL
, 0x07, 0x07);
94 static int rtl8411_extra_init_hw(struct rtsx_pcr
*pcr
)
96 rtsx_pci_init_cmd(pcr
);
98 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
99 0xFF, pcr
->sd30_drive_sel_3v3
);
100 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CD_PAD_CTL
,
101 CD_DISABLE_MASK
| CD_AUTO_DISABLE
, CD_ENABLE
);
103 return rtsx_pci_send_cmd(pcr
, 100);
106 static int rtl8411b_extra_init_hw(struct rtsx_pcr
*pcr
)
108 rtsx_pci_init_cmd(pcr
);
110 if (rtl8411b_is_qfn48(pcr
))
111 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
112 CARD_PULL_CTL3
, 0xFF, 0xF5);
113 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
114 0xFF, pcr
->sd30_drive_sel_3v3
);
115 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CD_PAD_CTL
,
116 CD_DISABLE_MASK
| CD_AUTO_DISABLE
, CD_ENABLE
);
117 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, FUNC_FORCE_CTL
,
120 return rtsx_pci_send_cmd(pcr
, 100);
123 static int rtl8411_turn_on_led(struct rtsx_pcr
*pcr
)
125 return rtsx_pci_write_register(pcr
, CARD_GPIO
, 0x01, 0x00);
128 static int rtl8411_turn_off_led(struct rtsx_pcr
*pcr
)
130 return rtsx_pci_write_register(pcr
, CARD_GPIO
, 0x01, 0x01);
133 static int rtl8411_enable_auto_blink(struct rtsx_pcr
*pcr
)
135 return rtsx_pci_write_register(pcr
, CARD_AUTO_BLINK
, 0xFF, 0x0D);
138 static int rtl8411_disable_auto_blink(struct rtsx_pcr
*pcr
)
140 return rtsx_pci_write_register(pcr
, CARD_AUTO_BLINK
, 0x08, 0x00);
143 static int rtl8411_card_power_on(struct rtsx_pcr
*pcr
, int card
)
147 rtsx_pci_init_cmd(pcr
);
148 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_PWR_CTL
,
149 BPP_POWER_MASK
, BPP_POWER_5_PERCENT_ON
);
150 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, LDO_CTL
,
151 BPP_LDO_POWB
, BPP_LDO_SUSPEND
);
152 err
= rtsx_pci_send_cmd(pcr
, 100);
156 /* To avoid too large in-rush current */
159 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
160 BPP_POWER_MASK
, BPP_POWER_10_PERCENT_ON
);
166 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
167 BPP_POWER_MASK
, BPP_POWER_15_PERCENT_ON
);
173 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
174 BPP_POWER_MASK
, BPP_POWER_ON
);
178 return rtsx_pci_write_register(pcr
, LDO_CTL
, BPP_LDO_POWB
, BPP_LDO_ON
);
181 static int rtl8411_card_power_off(struct rtsx_pcr
*pcr
, int card
)
185 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
186 BPP_POWER_MASK
, BPP_POWER_OFF
);
190 return rtsx_pci_write_register(pcr
, LDO_CTL
,
191 BPP_LDO_POWB
, BPP_LDO_SUSPEND
);
194 static int rtl8411_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
199 mask
= (BPP_REG_TUNED18
<< BPP_TUNED18_SHIFT_8411
) | BPP_PAD_MASK
;
200 if (voltage
== OUTPUT_3V3
) {
201 err
= rtsx_pci_write_register(pcr
,
202 SD30_DRIVE_SEL
, 0x07, pcr
->sd30_drive_sel_3v3
);
205 val
= (BPP_ASIC_3V3
<< BPP_TUNED18_SHIFT_8411
) | BPP_PAD_3V3
;
206 } else if (voltage
== OUTPUT_1V8
) {
207 err
= rtsx_pci_write_register(pcr
,
208 SD30_DRIVE_SEL
, 0x07, pcr
->sd30_drive_sel_1v8
);
211 val
= (BPP_ASIC_1V8
<< BPP_TUNED18_SHIFT_8411
) | BPP_PAD_1V8
;
216 return rtsx_pci_write_register(pcr
, LDO_CTL
, mask
, val
);
219 static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr
*pcr
)
221 unsigned int card_exist
;
223 card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
224 card_exist
&= CARD_EXIST
;
227 rtsx_pci_write_register(pcr
, CD_PAD_CTL
,
228 CD_DISABLE_MASK
, CD_ENABLE
);
229 /* Enable card interrupt */
230 rtsx_pci_write_register(pcr
, EFUSE_CONTENT
, 0xe0, 0x00);
234 if (hweight32(card_exist
) > 1) {
235 rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
236 BPP_POWER_MASK
, BPP_POWER_5_PERCENT_ON
);
239 card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
240 if (card_exist
& MS_EXIST
)
241 card_exist
= MS_EXIST
;
242 else if (card_exist
& SD_EXIST
)
243 card_exist
= SD_EXIST
;
247 rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
248 BPP_POWER_MASK
, BPP_POWER_OFF
);
250 dev_dbg(&(pcr
->pci
->dev
),
251 "After CD deglitch, card_exist = 0x%x\n",
255 if (card_exist
& MS_EXIST
) {
256 /* Disable SD interrupt */
257 rtsx_pci_write_register(pcr
, EFUSE_CONTENT
, 0xe0, 0x40);
258 rtsx_pci_write_register(pcr
, CD_PAD_CTL
,
259 CD_DISABLE_MASK
, MS_CD_EN_ONLY
);
260 } else if (card_exist
& SD_EXIST
) {
261 /* Disable MS interrupt */
262 rtsx_pci_write_register(pcr
, EFUSE_CONTENT
, 0xe0, 0x80);
263 rtsx_pci_write_register(pcr
, CD_PAD_CTL
,
264 CD_DISABLE_MASK
, SD_CD_EN_ONLY
);
270 static int rtl8411_conv_clk_and_div_n(int input
, int dir
)
274 if (dir
== CLK_TO_DIV_N
)
275 output
= input
* 4 / 5 - 2;
277 output
= (input
+ 2) * 5 / 4;
282 static const struct pcr_ops rtl8411_pcr_ops
= {
283 .fetch_vendor_settings
= rtl8411_fetch_vendor_settings
,
284 .extra_init_hw
= rtl8411_extra_init_hw
,
285 .optimize_phy
= NULL
,
286 .turn_on_led
= rtl8411_turn_on_led
,
287 .turn_off_led
= rtl8411_turn_off_led
,
288 .enable_auto_blink
= rtl8411_enable_auto_blink
,
289 .disable_auto_blink
= rtl8411_disable_auto_blink
,
290 .card_power_on
= rtl8411_card_power_on
,
291 .card_power_off
= rtl8411_card_power_off
,
292 .switch_output_voltage
= rtl8411_switch_output_voltage
,
293 .cd_deglitch
= rtl8411_cd_deglitch
,
294 .conv_clk_and_div_n
= rtl8411_conv_clk_and_div_n
,
295 .force_power_down
= rtl8411_force_power_down
,
298 static const struct pcr_ops rtl8411b_pcr_ops
= {
299 .fetch_vendor_settings
= rtl8411b_fetch_vendor_settings
,
300 .extra_init_hw
= rtl8411b_extra_init_hw
,
301 .optimize_phy
= NULL
,
302 .turn_on_led
= rtl8411_turn_on_led
,
303 .turn_off_led
= rtl8411_turn_off_led
,
304 .enable_auto_blink
= rtl8411_enable_auto_blink
,
305 .disable_auto_blink
= rtl8411_disable_auto_blink
,
306 .card_power_on
= rtl8411_card_power_on
,
307 .card_power_off
= rtl8411_card_power_off
,
308 .switch_output_voltage
= rtl8411_switch_output_voltage
,
309 .cd_deglitch
= rtl8411_cd_deglitch
,
310 .conv_clk_and_div_n
= rtl8411_conv_clk_and_div_n
,
311 .force_power_down
= rtl8411_force_power_down
,
314 /* SD Pull Control Enable:
315 * SD_DAT[3:0] ==> pull up
319 * SD_CLK ==> pull down
321 static const u32 rtl8411_sd_pull_ctl_enable_tbl
[] = {
322 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0xAA),
323 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0xAA),
324 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0xA9),
325 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09),
326 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x09),
327 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
331 /* SD Pull Control Disable:
332 * SD_DAT[3:0] ==> pull down
334 * SD_WP ==> pull down
335 * SD_CMD ==> pull down
336 * SD_CLK ==> pull down
338 static const u32 rtl8411_sd_pull_ctl_disable_tbl
[] = {
339 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
340 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
341 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x95),
342 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09),
343 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05),
344 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
348 /* MS Pull Control Enable:
350 * others ==> pull down
352 static const u32 rtl8411_ms_pull_ctl_enable_tbl
[] = {
353 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
354 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
355 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x95),
356 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x05),
357 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05),
358 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
362 /* MS Pull Control Disable:
364 * others ==> pull down
366 static const u32 rtl8411_ms_pull_ctl_disable_tbl
[] = {
367 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
368 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
369 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x95),
370 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09),
371 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05),
372 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
376 static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl
[] = {
377 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0xAA),
378 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0xAA),
379 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x09 | 0xD0),
380 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09 | 0x50),
381 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
382 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
386 static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl
[] = {
387 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0xAA),
388 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x69 | 0x90),
389 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x08 | 0x11),
393 static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl
[] = {
394 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
395 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
396 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x05 | 0xD0),
397 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09 | 0x50),
398 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
399 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
403 static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl
[] = {
404 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
405 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x65 | 0x90),
406 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
410 static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl
[] = {
411 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
412 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
413 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x05 | 0xD0),
414 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x05 | 0x50),
415 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
416 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
420 static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl
[] = {
421 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
422 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x65 | 0x90),
423 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
427 static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl
[] = {
428 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
429 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
430 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x05 | 0xD0),
431 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09 | 0x50),
432 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
433 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
437 static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl
[] = {
438 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
439 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x65 | 0x90),
440 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
444 void rtl8411_init_params(struct rtsx_pcr
*pcr
)
446 pcr
->extra_caps
= EXTRA_CAPS_SD_SDR50
| EXTRA_CAPS_SD_SDR104
;
448 pcr
->ops
= &rtl8411_pcr_ops
;
451 pcr
->card_drive_sel
= RTL8411_CARD_DRIVE_DEFAULT
;
452 pcr
->sd30_drive_sel_1v8
= DRIVER_TYPE_B
;
453 pcr
->sd30_drive_sel_3v3
= DRIVER_TYPE_D
;
454 pcr
->aspm_en
= ASPM_L1_EN
;
455 pcr
->tx_initial_phase
= SET_CLOCK_PHASE(23, 7, 14);
456 pcr
->rx_initial_phase
= SET_CLOCK_PHASE(4, 3, 10);
458 pcr
->ic_version
= rtl8411_get_ic_version(pcr
);
459 pcr
->sd_pull_ctl_enable_tbl
= rtl8411_sd_pull_ctl_enable_tbl
;
460 pcr
->sd_pull_ctl_disable_tbl
= rtl8411_sd_pull_ctl_disable_tbl
;
461 pcr
->ms_pull_ctl_enable_tbl
= rtl8411_ms_pull_ctl_enable_tbl
;
462 pcr
->ms_pull_ctl_disable_tbl
= rtl8411_ms_pull_ctl_disable_tbl
;
465 void rtl8411b_init_params(struct rtsx_pcr
*pcr
)
467 pcr
->extra_caps
= EXTRA_CAPS_SD_SDR50
| EXTRA_CAPS_SD_SDR104
;
469 pcr
->ops
= &rtl8411b_pcr_ops
;
472 pcr
->card_drive_sel
= RTL8411_CARD_DRIVE_DEFAULT
;
473 pcr
->sd30_drive_sel_1v8
= DRIVER_TYPE_B
;
474 pcr
->sd30_drive_sel_3v3
= DRIVER_TYPE_D
;
475 pcr
->aspm_en
= ASPM_L1_EN
;
476 pcr
->tx_initial_phase
= SET_CLOCK_PHASE(23, 7, 14);
477 pcr
->rx_initial_phase
= SET_CLOCK_PHASE(4, 3, 10);
479 pcr
->ic_version
= rtl8411_get_ic_version(pcr
);
481 if (rtl8411b_is_qfn48(pcr
)) {
482 pcr
->sd_pull_ctl_enable_tbl
=
483 rtl8411b_qfn48_sd_pull_ctl_enable_tbl
;
484 pcr
->sd_pull_ctl_disable_tbl
=
485 rtl8411b_qfn48_sd_pull_ctl_disable_tbl
;
486 pcr
->ms_pull_ctl_enable_tbl
=
487 rtl8411b_qfn48_ms_pull_ctl_enable_tbl
;
488 pcr
->ms_pull_ctl_disable_tbl
=
489 rtl8411b_qfn48_ms_pull_ctl_disable_tbl
;
491 pcr
->sd_pull_ctl_enable_tbl
=
492 rtl8411b_qfn64_sd_pull_ctl_enable_tbl
;
493 pcr
->sd_pull_ctl_disable_tbl
=
494 rtl8411b_qfn64_sd_pull_ctl_disable_tbl
;
495 pcr
->ms_pull_ctl_enable_tbl
=
496 rtl8411b_qfn64_ms_pull_ctl_enable_tbl
;
497 pcr
->ms_pull_ctl_disable_tbl
=
498 rtl8411b_qfn64_ms_pull_ctl_disable_tbl
;