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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / mfd / rtsx_pcr.c
blob6ed83feb0c52191430d7e699bfdef0d342c68b57
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <asm/unaligned.h>
34
35 #include "rtsx_pcr.h"
36
37 static bool msi_en = true;
38 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39 MODULE_PARM_DESC(msi_en, "Enable MSI");
40
41 static DEFINE_IDR(rtsx_pci_idr);
42 static DEFINE_SPINLOCK(rtsx_pci_lock);
43
44 static struct mfd_cell rtsx_pcr_cells[] = {
45 [RTSX_SD_CARD] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
47 },
48 [RTSX_MS_CARD] = {
49 .name = DRV_NAME_RTSX_PCI_MS,
50 },
51 };
52
53 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
60 { 0, }
61 };
62
63 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
64
65 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
66 {
67 /* If pci device removed, don't queue idle work any more */
68 if (pcr->remove_pci)
69 return;
70
71 if (pcr->state != PDEV_STAT_RUN) {
72 pcr->state = PDEV_STAT_RUN;
73 if (pcr->ops->enable_auto_blink)
74 pcr->ops->enable_auto_blink(pcr);
75
76 if (pcr->aspm_en)
77 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
78 }
79
80 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
81 }
82 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
83
84 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
85 {
86 int i;
87 u32 val = HAIMR_WRITE_START;
88
89 val |= (u32)(addr & 0x3FFF) << 16;
90 val |= (u32)mask << 8;
91 val |= (u32)data;
92
93 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
94
95 for (i = 0; i < MAX_RW_REG_CNT; i++) {
96 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
97 if ((val & HAIMR_TRANS_END) == 0) {
98 if (data != (u8)val)
99 return -EIO;
100 return 0;
101 }
102 }
103
104 return -ETIMEDOUT;
105 }
106 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
107
108 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
109 {
110 u32 val = HAIMR_READ_START;
111 int i;
112
113 val |= (u32)(addr & 0x3FFF) << 16;
114 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
115
116 for (i = 0; i < MAX_RW_REG_CNT; i++) {
117 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
118 if ((val & HAIMR_TRANS_END) == 0)
119 break;
120 }
121
122 if (i >= MAX_RW_REG_CNT)
123 return -ETIMEDOUT;
124
125 if (data)
126 *data = (u8)(val & 0xFF);
127
128 return 0;
129 }
130 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
131
132 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
133 {
134 int err, i, finished = 0;
135 u8 tmp;
136
137 rtsx_pci_init_cmd(pcr);
138
139 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
141 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
143
144 err = rtsx_pci_send_cmd(pcr, 100);
145 if (err < 0)
146 return err;
147
148 for (i = 0; i < 100000; i++) {
149 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
150 if (err < 0)
151 return err;
152
153 if (!(tmp & 0x80)) {
154 finished = 1;
155 break;
156 }
157 }
158
159 if (!finished)
160 return -ETIMEDOUT;
161
162 return 0;
163 }
164 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
165
166 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
167 {
168 int err, i, finished = 0;
169 u16 data;
170 u8 *ptr, tmp;
171
172 rtsx_pci_init_cmd(pcr);
173
174 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
176
177 err = rtsx_pci_send_cmd(pcr, 100);
178 if (err < 0)
179 return err;
180
181 for (i = 0; i < 100000; i++) {
182 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
183 if (err < 0)
184 return err;
185
186 if (!(tmp & 0x80)) {
187 finished = 1;
188 break;
189 }
190 }
191
192 if (!finished)
193 return -ETIMEDOUT;
194
195 rtsx_pci_init_cmd(pcr);
196
197 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
198 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
199
200 err = rtsx_pci_send_cmd(pcr, 100);
201 if (err < 0)
202 return err;
203
204 ptr = rtsx_pci_get_cmd_data(pcr);
205 data = ((u16)ptr[1] << 8) | ptr[0];
206
207 if (val)
208 *val = data;
209
210 return 0;
211 }
212 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
213
214 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
215 {
216 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
217 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
218
219 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
220 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
221 }
222 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
223
224 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
225 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
226 {
227 unsigned long flags;
228 u32 val = 0;
229 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
230
231 val |= (u32)(cmd_type & 0x03) << 30;
232 val |= (u32)(reg_addr & 0x3FFF) << 16;
233 val |= (u32)mask << 8;
234 val |= (u32)data;
235
236 spin_lock_irqsave(&pcr->lock, flags);
237 ptr += pcr->ci;
238 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
239 put_unaligned_le32(val, ptr);
240 ptr++;
241 pcr->ci++;
242 }
243 spin_unlock_irqrestore(&pcr->lock, flags);
244 }
245 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
246
247 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
248 {
249 u32 val = 1 << 31;
250
251 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
252
253 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
254 /* Hardware Auto Response */
255 val |= 0x40000000;
256 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
257 }
258 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
259
260 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
261 {
262 struct completion trans_done;
263 u32 val = 1 << 31;
264 long timeleft;
265 unsigned long flags;
266 int err = 0;
267
268 spin_lock_irqsave(&pcr->lock, flags);
269
270 /* set up data structures for the wakeup system */
271 pcr->done = &trans_done;
272 pcr->trans_result = TRANS_NOT_READY;
273 init_completion(&trans_done);
274
275 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
276
277 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
278 /* Hardware Auto Response */
279 val |= 0x40000000;
280 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
281
282 spin_unlock_irqrestore(&pcr->lock, flags);
283
284 /* Wait for TRANS_OK_INT */
285 timeleft = wait_for_completion_interruptible_timeout(
286 &trans_done, msecs_to_jiffies(timeout));
287 if (timeleft <= 0) {
288 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
289 __func__, __LINE__);
290 err = -ETIMEDOUT;
291 goto finish_send_cmd;
292 }
293
294 spin_lock_irqsave(&pcr->lock, flags);
295 if (pcr->trans_result == TRANS_RESULT_FAIL)
296 err = -EINVAL;
297 else if (pcr->trans_result == TRANS_RESULT_OK)
298 err = 0;
299 else if (pcr->trans_result == TRANS_NO_DEVICE)
300 err = -ENODEV;
301 spin_unlock_irqrestore(&pcr->lock, flags);
302
303 finish_send_cmd:
304 spin_lock_irqsave(&pcr->lock, flags);
305 pcr->done = NULL;
306 spin_unlock_irqrestore(&pcr->lock, flags);
307
308 if ((err < 0) && (err != -ENODEV))
309 rtsx_pci_stop_cmd(pcr);
310
311 if (pcr->finish_me)
312 complete(pcr->finish_me);
313
314 return err;
315 }
316 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
317
318 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
319 dma_addr_t addr, unsigned int len, int end)
320 {
321 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
322 u64 val;
323 u8 option = SG_VALID | SG_TRANS_DATA;
324
325 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
326 (unsigned int)addr, len);
327
328 if (end)
329 option |= SG_END;
330 val = ((u64)addr << 32) | ((u64)len << 12) | option;
331
332 put_unaligned_le64(val, ptr);
333 pcr->sgi++;
334 }
335
336 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
337 int num_sg, bool read, int timeout)
338 {
339 struct completion trans_done;
340 u8 dir;
341 int err = 0, i, count;
342 long timeleft;
343 unsigned long flags;
344 struct scatterlist *sg;
345 enum dma_data_direction dma_dir;
346 u32 val;
347 dma_addr_t addr;
348 unsigned int len;
349
350 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
351
352 /* don't transfer data during abort processing */
353 if (pcr->remove_pci)
354 return -EINVAL;
355
356 if ((sglist == NULL) || (num_sg <= 0))
357 return -EINVAL;
358
359 if (read) {
360 dir = DEVICE_TO_HOST;
361 dma_dir = DMA_FROM_DEVICE;
362 } else {
363 dir = HOST_TO_DEVICE;
364 dma_dir = DMA_TO_DEVICE;
365 }
366
367 count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
368 if (count < 1) {
369 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
370 return -EINVAL;
371 }
372 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
373
374 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
375 pcr->sgi = 0;
376 for_each_sg(sglist, sg, count, i) {
377 addr = sg_dma_address(sg);
378 len = sg_dma_len(sg);
379 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
380 }
381
382 spin_lock_irqsave(&pcr->lock, flags);
383
384 pcr->done = &trans_done;
385 pcr->trans_result = TRANS_NOT_READY;
386 init_completion(&trans_done);
387 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
388 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
389
390 spin_unlock_irqrestore(&pcr->lock, flags);
391
392 timeleft = wait_for_completion_interruptible_timeout(
393 &trans_done, msecs_to_jiffies(timeout));
394 if (timeleft <= 0) {
395 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
396 __func__, __LINE__);
397 err = -ETIMEDOUT;
398 goto out;
399 }
400
401 spin_lock_irqsave(&pcr->lock, flags);
402
403 if (pcr->trans_result == TRANS_RESULT_FAIL)
404 err = -EINVAL;
405 else if (pcr->trans_result == TRANS_NO_DEVICE)
406 err = -ENODEV;
407
408 spin_unlock_irqrestore(&pcr->lock, flags);
409
410 out:
411 spin_lock_irqsave(&pcr->lock, flags);
412 pcr->done = NULL;
413 spin_unlock_irqrestore(&pcr->lock, flags);
414
415 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
416
417 if ((err < 0) && (err != -ENODEV))
418 rtsx_pci_stop_cmd(pcr);
419
420 if (pcr->finish_me)
421 complete(pcr->finish_me);
422
423 return err;
424 }
425 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
426
427 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
428 {
429 int err;
430 int i, j;
431 u16 reg;
432 u8 *ptr;
433
434 if (buf_len > 512)
435 buf_len = 512;
436
437 ptr = buf;
438 reg = PPBUF_BASE2;
439 for (i = 0; i < buf_len / 256; i++) {
440 rtsx_pci_init_cmd(pcr);
441
442 for (j = 0; j < 256; j++)
443 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
444
445 err = rtsx_pci_send_cmd(pcr, 250);
446 if (err < 0)
447 return err;
448
449 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
450 ptr += 256;
451 }
452
453 if (buf_len % 256) {
454 rtsx_pci_init_cmd(pcr);
455
456 for (j = 0; j < buf_len % 256; j++)
457 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
458
459 err = rtsx_pci_send_cmd(pcr, 250);
460 if (err < 0)
461 return err;
462 }
463
464 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
465
466 return 0;
467 }
468 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
469
470 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
471 {
472 int err;
473 int i, j;
474 u16 reg;
475 u8 *ptr;
476
477 if (buf_len > 512)
478 buf_len = 512;
479
480 ptr = buf;
481 reg = PPBUF_BASE2;
482 for (i = 0; i < buf_len / 256; i++) {
483 rtsx_pci_init_cmd(pcr);
484
485 for (j = 0; j < 256; j++) {
486 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
487 reg++, 0xFF, *ptr);
488 ptr++;
489 }
490
491 err = rtsx_pci_send_cmd(pcr, 250);
492 if (err < 0)
493 return err;
494 }
495
496 if (buf_len % 256) {
497 rtsx_pci_init_cmd(pcr);
498
499 for (j = 0; j < buf_len % 256; j++) {
500 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
501 reg++, 0xFF, *ptr);
502 ptr++;
503 }
504
505 err = rtsx_pci_send_cmd(pcr, 250);
506 if (err < 0)
507 return err;
508 }
509
510 return 0;
511 }
512 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
513
514 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
515 {
516 int err;
517
518 rtsx_pci_init_cmd(pcr);
519
520 while (*tbl & 0xFFFF0000) {
521 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
522 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
523 tbl++;
524 }
525
526 err = rtsx_pci_send_cmd(pcr, 100);
527 if (err < 0)
528 return err;
529
530 return 0;
531 }
532
533 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
534 {
535 const u32 *tbl;
536
537 if (card == RTSX_SD_CARD)
538 tbl = pcr->sd_pull_ctl_enable_tbl;
539 else if (card == RTSX_MS_CARD)
540 tbl = pcr->ms_pull_ctl_enable_tbl;
541 else
542 return -EINVAL;
543
544 return rtsx_pci_set_pull_ctl(pcr, tbl);
545 }
546 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
547
548 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
549 {
550 const u32 *tbl;
551
552 if (card == RTSX_SD_CARD)
553 tbl = pcr->sd_pull_ctl_disable_tbl;
554 else if (card == RTSX_MS_CARD)
555 tbl = pcr->ms_pull_ctl_disable_tbl;
556 else
557 return -EINVAL;
558
559
560 return rtsx_pci_set_pull_ctl(pcr, tbl);
561 }
562 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
563
564 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
565 {
566 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
567
568 if (pcr->num_slots > 1)
569 pcr->bier |= MS_INT_EN;
570
571 /* Enable Bus Interrupt */
572 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
573
574 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
575 }
576
577 static inline u8 double_ssc_depth(u8 depth)
578 {
579 return ((depth > 1) ? (depth - 1) : depth);
580 }
581
582 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
583 {
584 if (div > CLK_DIV_1) {
585 if (ssc_depth > (div - 1))
586 ssc_depth -= (div - 1);
587 else
588 ssc_depth = SSC_DEPTH_4M;
589 }
590
591 return ssc_depth;
592 }
593
594 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
595 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
596 {
597 int err, clk;
598 u8 n, clk_divider, mcu_cnt, div;
599 u8 depth[] = {
600 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
601 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
602 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
603 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
604 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
605 };
606
607 if (initial_mode) {
608 /* We use 250k(around) here, in initial stage */
609 clk_divider = SD_CLK_DIVIDE_128;
610 card_clock = 30000000;
611 } else {
612 clk_divider = SD_CLK_DIVIDE_0;
613 }
614 err = rtsx_pci_write_register(pcr, SD_CFG1,
615 SD_CLK_DIVIDE_MASK, clk_divider);
616 if (err < 0)
617 return err;
618
619 card_clock /= 1000000;
620 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
621
622 clk = card_clock;
623 if (!initial_mode && double_clk)
624 clk = card_clock * 2;
625 dev_dbg(&(pcr->pci->dev),
626 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
627 clk, pcr->cur_clock);
628
629 if (clk == pcr->cur_clock)
630 return 0;
631
632 if (pcr->ops->conv_clk_and_div_n)
633 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
634 else
635 n = (u8)(clk - 2);
636 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
637 return -EINVAL;
638
639 mcu_cnt = (u8)(125/clk + 3);
640 if (mcu_cnt > 15)
641 mcu_cnt = 15;
642
643 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
644 div = CLK_DIV_1;
645 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
646 if (pcr->ops->conv_clk_and_div_n) {
647 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
648 DIV_N_TO_CLK) * 2;
649 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
650 CLK_TO_DIV_N);
651 } else {
652 n = (n + 2) * 2 - 2;
653 }
654 div++;
655 }
656 dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
657
658 ssc_depth = depth[ssc_depth];
659 if (double_clk)
660 ssc_depth = double_ssc_depth(ssc_depth);
661
662 ssc_depth = revise_ssc_depth(ssc_depth, div);
663 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
664
665 rtsx_pci_init_cmd(pcr);
666 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
667 CLK_LOW_FREQ, CLK_LOW_FREQ);
668 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
669 0xFF, (div << 4) | mcu_cnt);
670 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
671 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
672 SSC_DEPTH_MASK, ssc_depth);
673 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
674 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
675 if (vpclk) {
676 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
677 PHASE_NOT_RESET, 0);
678 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
679 PHASE_NOT_RESET, PHASE_NOT_RESET);
680 }
681
682 err = rtsx_pci_send_cmd(pcr, 2000);
683 if (err < 0)
684 return err;
685
686 /* Wait SSC clock stable */
687 udelay(10);
688 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
689 if (err < 0)
690 return err;
691
692 pcr->cur_clock = clk;
693 return 0;
694 }
695 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
696
697 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
698 {
699 if (pcr->ops->card_power_on)
700 return pcr->ops->card_power_on(pcr, card);
701
702 return 0;
703 }
704 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
705
706 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
707 {
708 if (pcr->ops->card_power_off)
709 return pcr->ops->card_power_off(pcr, card);
710
711 return 0;
712 }
713 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
714
715 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
716 {
717 unsigned int cd_mask[] = {
718 [RTSX_SD_CARD] = SD_EXIST,
719 [RTSX_MS_CARD] = MS_EXIST
720 };
721
722 if (!(pcr->flags & PCR_MS_PMOS)) {
723 /* When using single PMOS, accessing card is not permitted
724 * if the existing card is not the designated one.
725 */
726 if (pcr->card_exist & (~cd_mask[card]))
727 return -EIO;
728 }
729
730 return 0;
731 }
732 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
733
734 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
735 {
736 if (pcr->ops->switch_output_voltage)
737 return pcr->ops->switch_output_voltage(pcr, voltage);
738
739 return 0;
740 }
741 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
742
743 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
744 {
745 unsigned int val;
746
747 val = rtsx_pci_readl(pcr, RTSX_BIPR);
748 if (pcr->ops->cd_deglitch)
749 val = pcr->ops->cd_deglitch(pcr);
750
751 return val;
752 }
753 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
754
755 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
756 {
757 struct completion finish;
758
759 pcr->finish_me = &finish;
760 init_completion(&finish);
761
762 if (pcr->done)
763 complete(pcr->done);
764
765 if (!pcr->remove_pci)
766 rtsx_pci_stop_cmd(pcr);
767
768 wait_for_completion_interruptible_timeout(&finish,
769 msecs_to_jiffies(2));
770 pcr->finish_me = NULL;
771 }
772 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
773
774 static void rtsx_pci_card_detect(struct work_struct *work)
775 {
776 struct delayed_work *dwork;
777 struct rtsx_pcr *pcr;
778 unsigned long flags;
779 unsigned int card_detect = 0, card_inserted, card_removed;
780 u32 irq_status;
781
782 dwork = to_delayed_work(work);
783 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
784
785 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
786
787 mutex_lock(&pcr->pcr_mutex);
788 spin_lock_irqsave(&pcr->lock, flags);
789
790 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
791 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
792
793 irq_status &= CARD_EXIST;
794 card_inserted = pcr->card_inserted & irq_status;
795 card_removed = pcr->card_removed;
796 pcr->card_inserted = 0;
797 pcr->card_removed = 0;
798
799 spin_unlock_irqrestore(&pcr->lock, flags);
800
801 if (card_inserted || card_removed) {
802 dev_dbg(&(pcr->pci->dev),
803 "card_inserted: 0x%x, card_removed: 0x%x\n",
804 card_inserted, card_removed);
805
806 if (pcr->ops->cd_deglitch)
807 card_inserted = pcr->ops->cd_deglitch(pcr);
808
809 card_detect = card_inserted | card_removed;
810
811 pcr->card_exist |= card_inserted;
812 pcr->card_exist &= ~card_removed;
813 }
814
815 mutex_unlock(&pcr->pcr_mutex);
816
817 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
818 pcr->slots[RTSX_SD_CARD].card_event(
819 pcr->slots[RTSX_SD_CARD].p_dev);
820 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
821 pcr->slots[RTSX_MS_CARD].card_event(
822 pcr->slots[RTSX_MS_CARD].p_dev);
823 }
824
825 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
826 {
827 struct rtsx_pcr *pcr = dev_id;
828 u32 int_reg;
829
830 if (!pcr)
831 return IRQ_NONE;
832
833 spin_lock(&pcr->lock);
834
835 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
836 /* Clear interrupt flag */
837 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
838 if ((int_reg & pcr->bier) == 0) {
839 spin_unlock(&pcr->lock);
840 return IRQ_NONE;
841 }
842 if (int_reg == 0xFFFFFFFF) {
843 spin_unlock(&pcr->lock);
844 return IRQ_HANDLED;
845 }
846
847 int_reg &= (pcr->bier | 0x7FFFFF);
848
849 if (int_reg & SD_INT) {
850 if (int_reg & SD_EXIST) {
851 pcr->card_inserted |= SD_EXIST;
852 } else {
853 pcr->card_removed |= SD_EXIST;
854 pcr->card_inserted &= ~SD_EXIST;
855 }
856 }
857
858 if (int_reg & MS_INT) {
859 if (int_reg & MS_EXIST) {
860 pcr->card_inserted |= MS_EXIST;
861 } else {
862 pcr->card_removed |= MS_EXIST;
863 pcr->card_inserted &= ~MS_EXIST;
864 }
865 }
866
867 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
868 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
869 pcr->trans_result = TRANS_RESULT_FAIL;
870 if (pcr->done)
871 complete(pcr->done);
872 } else if (int_reg & TRANS_OK_INT) {
873 pcr->trans_result = TRANS_RESULT_OK;
874 if (pcr->done)
875 complete(pcr->done);
876 }
877 }
878
879 if (pcr->card_inserted || pcr->card_removed)
880 schedule_delayed_work(&pcr->carddet_work,
881 msecs_to_jiffies(200));
882
883 spin_unlock(&pcr->lock);
884 return IRQ_HANDLED;
885 }
886
887 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
888 {
889 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
890 __func__, pcr->msi_en, pcr->pci->irq);
891
892 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
893 pcr->msi_en ? 0 : IRQF_SHARED,
894 DRV_NAME_RTSX_PCI, pcr)) {
895 dev_err(&(pcr->pci->dev),
896 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
897 pcr->pci->irq);
898 return -1;
899 }
900
901 pcr->irq = pcr->pci->irq;
902 pci_intx(pcr->pci, !pcr->msi_en);
903
904 return 0;
905 }
906
907 static void rtsx_pci_idle_work(struct work_struct *work)
908 {
909 struct delayed_work *dwork = to_delayed_work(work);
910 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
911
912 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
913
914 mutex_lock(&pcr->pcr_mutex);
915
916 pcr->state = PDEV_STAT_IDLE;
917
918 if (pcr->ops->disable_auto_blink)
919 pcr->ops->disable_auto_blink(pcr);
920 if (pcr->ops->turn_off_led)
921 pcr->ops->turn_off_led(pcr);
922
923 if (pcr->aspm_en)
924 rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
925
926 mutex_unlock(&pcr->pcr_mutex);
927 }
928
929 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
930 {
931 if (pcr->ops->turn_off_led)
932 pcr->ops->turn_off_led(pcr);
933
934 rtsx_pci_writel(pcr, RTSX_BIER, 0);
935 pcr->bier = 0;
936
937 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
938 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
939
940 if (pcr->ops->force_power_down)
941 pcr->ops->force_power_down(pcr, pm_state);
942 }
943
944 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
945 {
946 int err;
947
948 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
949
950 rtsx_pci_enable_bus_int(pcr);
951
952 /* Power on SSC */
953 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
954 if (err < 0)
955 return err;
956
957 /* Wait SSC power stable */
958 udelay(200);
959
960 if (pcr->ops->optimize_phy) {
961 err = pcr->ops->optimize_phy(pcr);
962 if (err < 0)
963 return err;
964 }
965
966 rtsx_pci_init_cmd(pcr);
967
968 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
969 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
970
971 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
972 /* Disable card clock */
973 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
974 /* Reset delink mode */
975 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
976 /* Card driving select */
977 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
978 0xFF, pcr->card_drive_sel);
979 /* Enable SSC Clock */
980 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
981 0xFF, SSC_8X_EN | SSC_SEL_4M);
982 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
983 /* Disable cd_pwr_save */
984 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
985 /* Clear Link Ready Interrupt */
986 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
987 LINK_RDY_INT, LINK_RDY_INT);
988 /* Enlarge the estimation window of PERST# glitch
989 * to reduce the chance of invalid card interrupt
990 */
991 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
992 /* Update RC oscillator to 400k
993 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
994 * 1: 2M 0: 400k
995 */
996 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
997 /* Set interrupt write clear
998 * bit 1: U_elbi_if_rd_clr_en
999 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1000 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1001 */
1002 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1003
1004 err = rtsx_pci_send_cmd(pcr, 100);
1005 if (err < 0)
1006 return err;
1007
1008 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
1009
1010 /* Enable clk_request_n to enable clock power management */
1011 rtsx_pci_write_config_byte(pcr, 0x81, 1);
1012 /* Enter L1 when host tx idle */
1013 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1014
1015 if (pcr->ops->extra_init_hw) {
1016 err = pcr->ops->extra_init_hw(pcr);
1017 if (err < 0)
1018 return err;
1019 }
1020
1021 /* No CD interrupt if probing driver with card inserted.
1022 * So we need to initialize pcr->card_exist here.
1023 */
1024 if (pcr->ops->cd_deglitch)
1025 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1026 else
1027 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1028
1029 return 0;
1030 }
1031
1032 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1033 {
1034 int err;
1035
1036 spin_lock_init(&pcr->lock);
1037 mutex_init(&pcr->pcr_mutex);
1038
1039 switch (PCI_PID(pcr)) {
1040 default:
1041 case 0x5209:
1042 rts5209_init_params(pcr);
1043 break;
1044
1045 case 0x5229:
1046 rts5229_init_params(pcr);
1047 break;
1048
1049 case 0x5289:
1050 rtl8411_init_params(pcr);
1051 break;
1052
1053 case 0x5227:
1054 rts5227_init_params(pcr);
1055 break;
1056
1057 case 0x5249:
1058 rts5249_init_params(pcr);
1059 break;
1060
1061 case 0x5287:
1062 rtl8411b_init_params(pcr);
1063 break;
1064 }
1065
1066 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1067 PCI_PID(pcr), pcr->ic_version);
1068
1069 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1070 GFP_KERNEL);
1071 if (!pcr->slots)
1072 return -ENOMEM;
1073
1074 if (pcr->ops->fetch_vendor_settings)
1075 pcr->ops->fetch_vendor_settings(pcr);
1076
1077 dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1078 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1079 pcr->sd30_drive_sel_1v8);
1080 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1081 pcr->sd30_drive_sel_3v3);
1082 dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
1083 pcr->card_drive_sel);
1084 dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
1085
1086 pcr->state = PDEV_STAT_IDLE;
1087 err = rtsx_pci_init_hw(pcr);
1088 if (err < 0) {
1089 kfree(pcr->slots);
1090 return err;
1091 }
1092
1093 return 0;
1094 }
1095
1096 static int rtsx_pci_probe(struct pci_dev *pcidev,
1097 const struct pci_device_id *id)
1098 {
1099 struct rtsx_pcr *pcr;
1100 struct pcr_handle *handle;
1101 u32 base, len;
1102 int ret, i;
1103
1104 dev_dbg(&(pcidev->dev),
1105 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1106 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1107 (int)pcidev->revision);
1108
1109 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1110 if (ret < 0)
1111 return ret;
1112
1113 ret = pci_enable_device(pcidev);
1114 if (ret)
1115 return ret;
1116
1117 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1118 if (ret)
1119 goto disable;
1120
1121 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1122 if (!pcr) {
1123 ret = -ENOMEM;
1124 goto release_pci;
1125 }
1126
1127 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1128 if (!handle) {
1129 ret = -ENOMEM;
1130 goto free_pcr;
1131 }
1132 handle->pcr = pcr;
1133
1134 idr_preload(GFP_KERNEL);
1135 spin_lock(&rtsx_pci_lock);
1136 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1137 if (ret >= 0)
1138 pcr->id = ret;
1139 spin_unlock(&rtsx_pci_lock);
1140 idr_preload_end();
1141 if (ret < 0)
1142 goto free_handle;
1143
1144 pcr->pci = pcidev;
1145 dev_set_drvdata(&pcidev->dev, handle);
1146
1147 len = pci_resource_len(pcidev, 0);
1148 base = pci_resource_start(pcidev, 0);
1149 pcr->remap_addr = ioremap_nocache(base, len);
1150 if (!pcr->remap_addr) {
1151 ret = -ENOMEM;
1152 goto free_host;
1153 }
1154
1155 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1156 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1157 GFP_KERNEL);
1158 if (pcr->rtsx_resv_buf == NULL) {
1159 ret = -ENXIO;
1160 goto unmap;
1161 }
1162 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1163 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1164 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1165 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1166
1167 pcr->card_inserted = 0;
1168 pcr->card_removed = 0;
1169 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1170 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1171
1172 pcr->msi_en = msi_en;
1173 if (pcr->msi_en) {
1174 ret = pci_enable_msi(pcidev);
1175 if (ret < 0)
1176 pcr->msi_en = false;
1177 }
1178
1179 ret = rtsx_pci_acquire_irq(pcr);
1180 if (ret < 0)
1181 goto disable_msi;
1182
1183 pci_set_master(pcidev);
1184 synchronize_irq(pcr->irq);
1185
1186 ret = rtsx_pci_init_chip(pcr);
1187 if (ret < 0)
1188 goto disable_irq;
1189
1190 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1191 rtsx_pcr_cells[i].platform_data = handle;
1192 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1193 }
1194 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1195 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1196 if (ret < 0)
1197 goto disable_irq;
1198
1199 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1200
1201 return 0;
1202
1203 disable_irq:
1204 free_irq(pcr->irq, (void *)pcr);
1205 disable_msi:
1206 if (pcr->msi_en)
1207 pci_disable_msi(pcr->pci);
1208 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1209 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1210 unmap:
1211 iounmap(pcr->remap_addr);
1212 free_host:
1213 dev_set_drvdata(&pcidev->dev, NULL);
1214 free_handle:
1215 kfree(handle);
1216 free_pcr:
1217 kfree(pcr);
1218 release_pci:
1219 pci_release_regions(pcidev);
1220 disable:
1221 pci_disable_device(pcidev);
1222
1223 return ret;
1224 }
1225
1226 static void rtsx_pci_remove(struct pci_dev *pcidev)
1227 {
1228 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1229 struct rtsx_pcr *pcr = handle->pcr;
1230
1231 pcr->remove_pci = true;
1232
1233 /* Disable interrupts at the pcr level */
1234 spin_lock_irq(&pcr->lock);
1235 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1236 pcr->bier = 0;
1237 spin_unlock_irq(&pcr->lock);
1238
1239 cancel_delayed_work_sync(&pcr->carddet_work);
1240 cancel_delayed_work_sync(&pcr->idle_work);
1241
1242 mfd_remove_devices(&pcidev->dev);
1243
1244 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1245 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1246 free_irq(pcr->irq, (void *)pcr);
1247 if (pcr->msi_en)
1248 pci_disable_msi(pcr->pci);
1249 iounmap(pcr->remap_addr);
1250
1251 dev_set_drvdata(&pcidev->dev, NULL);
1252 pci_release_regions(pcidev);
1253 pci_disable_device(pcidev);
1254
1255 spin_lock(&rtsx_pci_lock);
1256 idr_remove(&rtsx_pci_idr, pcr->id);
1257 spin_unlock(&rtsx_pci_lock);
1258
1259 kfree(pcr->slots);
1260 kfree(pcr);
1261 kfree(handle);
1262
1263 dev_dbg(&(pcidev->dev),
1264 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1265 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1266 }
1267
1268 #ifdef CONFIG_PM
1269
1270 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1271 {
1272 struct pcr_handle *handle;
1273 struct rtsx_pcr *pcr;
1274
1275 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1276
1277 handle = pci_get_drvdata(pcidev);
1278 pcr = handle->pcr;
1279
1280 cancel_delayed_work(&pcr->carddet_work);
1281 cancel_delayed_work(&pcr->idle_work);
1282
1283 mutex_lock(&pcr->pcr_mutex);
1284
1285 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1286
1287 pci_save_state(pcidev);
1288 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1289 pci_disable_device(pcidev);
1290 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1291
1292 mutex_unlock(&pcr->pcr_mutex);
1293 return 0;
1294 }
1295
1296 static int rtsx_pci_resume(struct pci_dev *pcidev)
1297 {
1298 struct pcr_handle *handle;
1299 struct rtsx_pcr *pcr;
1300 int ret = 0;
1301
1302 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1303
1304 handle = pci_get_drvdata(pcidev);
1305 pcr = handle->pcr;
1306
1307 mutex_lock(&pcr->pcr_mutex);
1308
1309 pci_set_power_state(pcidev, PCI_D0);
1310 pci_restore_state(pcidev);
1311 ret = pci_enable_device(pcidev);
1312 if (ret)
1313 goto out;
1314 pci_set_master(pcidev);
1315
1316 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1317 if (ret)
1318 goto out;
1319
1320 ret = rtsx_pci_init_hw(pcr);
1321 if (ret)
1322 goto out;
1323
1324 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1325
1326 out:
1327 mutex_unlock(&pcr->pcr_mutex);
1328 return ret;
1329 }
1330
1331 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1332 {
1333 struct pcr_handle *handle;
1334 struct rtsx_pcr *pcr;
1335
1336 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1337
1338 handle = pci_get_drvdata(pcidev);
1339 pcr = handle->pcr;
1340 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1341
1342 pci_disable_device(pcidev);
1343 }
1344
1345 #else /* CONFIG_PM */
1346
1347 #define rtsx_pci_suspend NULL
1348 #define rtsx_pci_resume NULL
1349 #define rtsx_pci_shutdown NULL
1350
1351 #endif /* CONFIG_PM */
1352
1353 static struct pci_driver rtsx_pci_driver = {
1354 .name = DRV_NAME_RTSX_PCI,
1355 .id_table = rtsx_pci_ids,
1356 .probe = rtsx_pci_probe,
1357 .remove = rtsx_pci_remove,
1358 .suspend = rtsx_pci_suspend,
1359 .resume = rtsx_pci_resume,
1360 .shutdown = rtsx_pci_shutdown,
1361 };
1362 module_pci_driver(rtsx_pci_driver);
1363
1364 MODULE_LICENSE("GPL");
1365 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1366 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Linux with added FPC-III support