drivers/misc/mei/hw-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18
  19 #include <linux/kthread.h>
  20 #include <linux/interrupt.h>
  21
  22 #include "mei_dev.h"
  23 #include "hw-me.h"
  24
  25 #include "hbm.h"
  26
  27
  28 /**
  29  * mei_me_reg_read - Reads 32bit data from the mei device
  30  *
  31  * @dev: the device structure
  32  * @offset: offset from which to read the data
  33  *
  34  * returns register value (u32)
  35  */
  36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
  37                                unsigned long offset)
  38 {
  39         return ioread32(hw->mem_addr + offset);
  40 }
  41
  42
  43 /**
  44  * mei_me_reg_write - Writes 32bit data to the mei device
  45  *
  46  * @dev: the device structure
  47  * @offset: offset from which to write the data
  48  * @value: register value to write (u32)
  49  */
  50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
  51                                  unsigned long offset, u32 value)
  52 {
  53         iowrite32(value, hw->mem_addr + offset);
  54 }
  55
  56 /**
  57  * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
  58  *  read window register
  59  *
  60  * @dev: the device structure
  61  *
  62  * returns ME_CB_RW register value (u32)
  63  */
  64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
  65 {
  66         return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
  67 }
  68 /**
  69  * mei_me_mecsr_read - Reads 32bit data from the ME CSR
  70  *
  71  * @dev: the device structure
  72  *
  73  * returns ME_CSR_HA register value (u32)
  74  */
  75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
  76 {
  77         return mei_me_reg_read(hw, ME_CSR_HA);
  78 }
  79
  80 /**
  81  * mei_hcsr_read - Reads 32bit data from the host CSR
  82  *
  83  * @dev: the device structure
  84  *
  85  * returns H_CSR register value (u32)
  86  */
  87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
  88 {
  89         return mei_me_reg_read(hw, H_CSR);
  90 }
  91
  92 /**
  93  * mei_hcsr_set - writes H_CSR register to the mei device,
  94  * and ignores the H_IS bit for it is write-one-to-zero.
  95  *
  96  * @dev: the device structure
  97  */
  98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
  99 {
 100         hcsr &= ~H_IS;
 101         mei_me_reg_write(hw, H_CSR, hcsr);
 102 }
 103
 104
 105 /**
 106  * mei_me_hw_config - configure hw dependent settings
 107  *
 108  * @dev: mei device
 109  */
 110 static void mei_me_hw_config(struct mei_device *dev)
 111 {
 112         u32 hcsr = mei_hcsr_read(to_me_hw(dev));
 113         /* Doesn't change in runtime */
 114         dev->hbuf_depth = (hcsr & H_CBD) >> 24;
 115 }
 116 /**
 117  * mei_clear_interrupts - clear and stop interrupts
 118  *
 119  * @dev: the device structure
 120  */
 121 static void mei_me_intr_clear(struct mei_device *dev)
 122 {
 123         struct mei_me_hw *hw = to_me_hw(dev);
 124         u32 hcsr = mei_hcsr_read(hw);
 125         if ((hcsr & H_IS) == H_IS)
 126                 mei_me_reg_write(hw, H_CSR, hcsr);
 127 }
 128 /**
 129  * mei_me_intr_enable - enables mei device interrupts
 130  *
 131  * @dev: the device structure
 132  */
 133 static void mei_me_intr_enable(struct mei_device *dev)
 134 {
 135         struct mei_me_hw *hw = to_me_hw(dev);
 136         u32 hcsr = mei_hcsr_read(hw);
 137         hcsr |= H_IE;
 138         mei_hcsr_set(hw, hcsr);
 139 }
 140
 141 /**
 142  * mei_disable_interrupts - disables mei device interrupts
 143  *
 144  * @dev: the device structure
 145  */
 146 static void mei_me_intr_disable(struct mei_device *dev)
 147 {
 148         struct mei_me_hw *hw = to_me_hw(dev);
 149         u32 hcsr = mei_hcsr_read(hw);
 150         hcsr  &= ~H_IE;
 151         mei_hcsr_set(hw, hcsr);
 152 }
 153
 154 /**
 155  * mei_me_hw_reset_release - release device from the reset
 156  *
 157  * @dev: the device structure
 158  */
 159 static void mei_me_hw_reset_release(struct mei_device *dev)
 160 {
 161         struct mei_me_hw *hw = to_me_hw(dev);
 162         u32 hcsr = mei_hcsr_read(hw);
 163
 164         hcsr |= H_IG;
 165         hcsr &= ~H_RST;
 166         mei_hcsr_set(hw, hcsr);
 167
 168         /* complete this write before we set host ready on another CPU */
 169         mmiowb();
 170 }
 171 /**
 172  * mei_me_hw_reset - resets fw via mei csr register.
 173  *
 174  * @dev: the device structure
 175  * @intr_enable: if interrupt should be enabled after reset.
 176  */
 177 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 178 {
 179         struct mei_me_hw *hw = to_me_hw(dev);
 180         u32 hcsr = mei_hcsr_read(hw);
 181
 182         hcsr |= H_RST | H_IG | H_IS;
 183
 184         if (intr_enable)
 185                 hcsr |= H_IE;
 186         else
 187                 hcsr &= ~H_IE;
 188
 189         dev->recvd_hw_ready = false;
 190         mei_me_reg_write(hw, H_CSR, hcsr);
 191
 192         /*
 193          * Host reads the H_CSR once to ensure that the
 194          * posted write to H_CSR completes.
 195          */
 196         hcsr = mei_hcsr_read(hw);
 197
 198         if ((hcsr & H_RST) == 0)
 199                 dev_warn(&dev->pdev->dev, "H_RST is not set = 0x%08X", hcsr);
 200
 201         if ((hcsr & H_RDY) == H_RDY)
 202                 dev_warn(&dev->pdev->dev, "H_RDY is not cleared 0x%08X", hcsr);
 203
 204         if (intr_enable == false)
 205                 mei_me_hw_reset_release(dev);
 206
 207         return 0;
 208 }
 209
 210 /**
 211  * mei_me_host_set_ready - enable device
 212  *
 213  * @dev - mei device
 214  * returns bool
 215  */
 216
 217 static void mei_me_host_set_ready(struct mei_device *dev)
 218 {
 219         struct mei_me_hw *hw = to_me_hw(dev);
 220         hw->host_hw_state = mei_hcsr_read(hw);
 221         hw->host_hw_state |= H_IE | H_IG | H_RDY;
 222         mei_hcsr_set(hw, hw->host_hw_state);
 223 }
 224 /**
 225  * mei_me_host_is_ready - check whether the host has turned ready
 226  *
 227  * @dev - mei device
 228  * returns bool
 229  */
 230 static bool mei_me_host_is_ready(struct mei_device *dev)
 231 {
 232         struct mei_me_hw *hw = to_me_hw(dev);
 233         hw->host_hw_state = mei_hcsr_read(hw);
 234         return (hw->host_hw_state & H_RDY) == H_RDY;
 235 }
 236
 237 /**
 238  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
 239  *
 240  * @dev - mei device
 241  * returns bool
 242  */
 243 static bool mei_me_hw_is_ready(struct mei_device *dev)
 244 {
 245         struct mei_me_hw *hw = to_me_hw(dev);
 246         hw->me_hw_state = mei_me_mecsr_read(hw);
 247         return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
 248 }
 249
 250 static int mei_me_hw_ready_wait(struct mei_device *dev)
 251 {
 252         int err;
 253
 254         mutex_unlock(&dev->device_lock);
 255         err = wait_event_interruptible_timeout(dev->wait_hw_ready,
 256                         dev->recvd_hw_ready,
 257                         mei_secs_to_jiffies(MEI_INTEROP_TIMEOUT));
 258         mutex_lock(&dev->device_lock);
 259         if (!err && !dev->recvd_hw_ready) {
 260                 if (!err)
 261                         err = -ETIMEDOUT;
 262                 dev_err(&dev->pdev->dev,
 263                         "wait hw ready failed. status = %d\n", err);
 264                 return err;
 265         }
 266
 267         dev->recvd_hw_ready = false;
 268         return 0;
 269 }
 270
 271 static int mei_me_hw_start(struct mei_device *dev)
 272 {
 273         int ret = mei_me_hw_ready_wait(dev);
 274         if (ret)
 275                 return ret;
 276         dev_dbg(&dev->pdev->dev, "hw is ready\n");
 277
 278         mei_me_host_set_ready(dev);
 279         return ret;
 280 }
 281
 282
 283 /**
 284  * mei_hbuf_filled_slots - gets number of device filled buffer slots
 285  *
 286  * @dev: the device structure
 287  *
 288  * returns number of filled slots
 289  */
 290 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
 291 {
 292         struct mei_me_hw *hw = to_me_hw(dev);
 293         char read_ptr, write_ptr;
 294
 295         hw->host_hw_state = mei_hcsr_read(hw);
 296
 297         read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
 298         write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
 299
 300         return (unsigned char) (write_ptr - read_ptr);
 301 }
 302
 303 /**
 304  * mei_me_hbuf_is_empty - checks if host buffer is empty.
 305  *
 306  * @dev: the device structure
 307  *
 308  * returns true if empty, false - otherwise.
 309  */
 310 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
 311 {
 312         return mei_hbuf_filled_slots(dev) == 0;
 313 }
 314
 315 /**
 316  * mei_me_hbuf_empty_slots - counts write empty slots.
 317  *
 318  * @dev: the device structure
 319  *
 320  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
 321  */
 322 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
 323 {
 324         unsigned char filled_slots, empty_slots;
 325
 326         filled_slots = mei_hbuf_filled_slots(dev);
 327         empty_slots = dev->hbuf_depth - filled_slots;
 328
 329         /* check for overflow */
 330         if (filled_slots > dev->hbuf_depth)
 331                 return -EOVERFLOW;
 332
 333         return empty_slots;
 334 }
 335
 336 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
 337 {
 338         return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
 339 }
 340
 341
 342 /**
 343  * mei_write_message - writes a message to mei device.
 344  *
 345  * @dev: the device structure
 346  * @header: mei HECI header of message
 347  * @buf: message payload will be written
 348  *
 349  * This function returns -EIO if write has failed
 350  */
 351 static int mei_me_write_message(struct mei_device *dev,
 352                         struct mei_msg_hdr *header,
 353                         unsigned char *buf)
 354 {
 355         struct mei_me_hw *hw = to_me_hw(dev);
 356         unsigned long rem;
 357         unsigned long length = header->length;
 358         u32 *reg_buf = (u32 *)buf;
 359         u32 hcsr;
 360         u32 dw_cnt;
 361         int i;
 362         int empty_slots;
 363
 364         dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 365
 366         empty_slots = mei_hbuf_empty_slots(dev);
 367         dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
 368
 369         dw_cnt = mei_data2slots(length);
 370         if (empty_slots < 0 || dw_cnt > empty_slots)
 371                 return -EIO;
 372
 373         mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
 374
 375         for (i = 0; i < length / 4; i++)
 376                 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
 377
 378         rem = length & 0x3;
 379         if (rem > 0) {
 380                 u32 reg = 0;
 381                 memcpy(&reg, &buf[length - rem], rem);
 382                 mei_me_reg_write(hw, H_CB_WW, reg);
 383         }
 384
 385         hcsr = mei_hcsr_read(hw) | H_IG;
 386         mei_hcsr_set(hw, hcsr);
 387         if (!mei_me_hw_is_ready(dev))
 388                 return -EIO;
 389
 390         return 0;
 391 }
 392
 393 /**
 394  * mei_me_count_full_read_slots - counts read full slots.
 395  *
 396  * @dev: the device structure
 397  *
 398  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
 399  */
 400 static int mei_me_count_full_read_slots(struct mei_device *dev)
 401 {
 402         struct mei_me_hw *hw = to_me_hw(dev);
 403         char read_ptr, write_ptr;
 404         unsigned char buffer_depth, filled_slots;
 405
 406         hw->me_hw_state = mei_me_mecsr_read(hw);
 407         buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
 408         read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
 409         write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
 410         filled_slots = (unsigned char) (write_ptr - read_ptr);
 411
 412         /* check for overflow */
 413         if (filled_slots > buffer_depth)
 414                 return -EOVERFLOW;
 415
 416         dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
 417         return (int)filled_slots;
 418 }
 419
 420 /**
 421  * mei_me_read_slots - reads a message from mei device.
 422  *
 423  * @dev: the device structure
 424  * @buffer: message buffer will be written
 425  * @buffer_length: message size will be read
 426  */
 427 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
 428                     unsigned long buffer_length)
 429 {
 430         struct mei_me_hw *hw = to_me_hw(dev);
 431         u32 *reg_buf = (u32 *)buffer;
 432         u32 hcsr;
 433
 434         for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
 435                 *reg_buf++ = mei_me_mecbrw_read(dev);
 436
 437         if (buffer_length > 0) {
 438                 u32 reg = mei_me_mecbrw_read(dev);
 439                 memcpy(reg_buf, &reg, buffer_length);
 440         }
 441
 442         hcsr = mei_hcsr_read(hw) | H_IG;
 443         mei_hcsr_set(hw, hcsr);
 444         return 0;
 445 }
 446
 447 /**
 448  * mei_me_irq_quick_handler - The ISR of the MEI device
 449  *
 450  * @irq: The irq number
 451  * @dev_id: pointer to the device structure
 452  *
 453  * returns irqreturn_t
 454  */
 455
 456 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
 457 {
 458         struct mei_device *dev = (struct mei_device *) dev_id;
 459         struct mei_me_hw *hw = to_me_hw(dev);
 460         u32 csr_reg = mei_hcsr_read(hw);
 461
 462         if ((csr_reg & H_IS) != H_IS)
 463                 return IRQ_NONE;
 464
 465         /* clear H_IS bit in H_CSR */
 466         mei_me_reg_write(hw, H_CSR, csr_reg);
 467
 468         return IRQ_WAKE_THREAD;
 469 }
 470
 471 /**
 472  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 473  * processing.
 474  *
 475  * @irq: The irq number
 476  * @dev_id: pointer to the device structure
 477  *
 478  * returns irqreturn_t
 479  *
 480  */
 481 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 482 {
 483         struct mei_device *dev = (struct mei_device *) dev_id;
 484         struct mei_cl_cb complete_list;
 485         s32 slots;
 486         int rets;
 487
 488         dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
 489         /* initialize our complete list */
 490         mutex_lock(&dev->device_lock);
 491         mei_io_list_init(&complete_list);
 492
 493         /* Ack the interrupt here
 494          * In case of MSI we don't go through the quick handler */
 495         if (pci_dev_msi_enabled(dev->pdev))
 496                 mei_clear_interrupts(dev);
 497
 498         /* check if ME wants a reset */
 499         if (!mei_hw_is_ready(dev) &&
 500             dev->dev_state != MEI_DEV_RESETTING &&
 501             dev->dev_state != MEI_DEV_INITIALIZING &&
 502             dev->dev_state != MEI_DEV_POWER_DOWN &&
 503             dev->dev_state != MEI_DEV_POWER_UP) {
 504                 dev_dbg(&dev->pdev->dev, "FW not ready.\n");
 505                 mei_reset(dev, 1);
 506                 mutex_unlock(&dev->device_lock);
 507                 return IRQ_HANDLED;
 508         }
 509
 510         /*  check if we need to start the dev */
 511         if (!mei_host_is_ready(dev)) {
 512                 if (mei_hw_is_ready(dev)) {
 513                         mei_me_hw_reset_release(dev);
 514                         dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
 515
 516                         dev->recvd_hw_ready = true;
 517                         wake_up_interruptible(&dev->wait_hw_ready);
 518                 } else {
 519                         dev_dbg(&dev->pdev->dev, "Spurious Interrupt\n");
 520                 }
 521                 goto end;
 522         }
 523         /* check slots available for reading */
 524         slots = mei_count_full_read_slots(dev);
 525         while (slots > 0) {
 526                 /* we have urgent data to send so break the read */
 527                 if (dev->wr_ext_msg.hdr.length)
 528                         break;
 529                 dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots);
 530                 dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n");
 531                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
 532                 if (rets)
 533                         goto end;
 534         }
 535         rets = mei_irq_write_handler(dev, &complete_list);
 536 end:
 537         dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
 538         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 539
 540         mutex_unlock(&dev->device_lock);
 541
 542         mei_irq_compl_handler(dev, &complete_list);
 543
 544         return IRQ_HANDLED;
 545 }
 546 static const struct mei_hw_ops mei_me_hw_ops = {
 547
 548         .host_is_ready = mei_me_host_is_ready,
 549
 550         .hw_is_ready = mei_me_hw_is_ready,
 551         .hw_reset = mei_me_hw_reset,
 552         .hw_config = mei_me_hw_config,
 553         .hw_start = mei_me_hw_start,
 554
 555         .intr_clear = mei_me_intr_clear,
 556         .intr_enable = mei_me_intr_enable,
 557         .intr_disable = mei_me_intr_disable,
 558
 559         .hbuf_free_slots = mei_me_hbuf_empty_slots,
 560         .hbuf_is_ready = mei_me_hbuf_is_empty,
 561         .hbuf_max_len = mei_me_hbuf_max_len,
 562
 563         .write = mei_me_write_message,
 564
 565         .rdbuf_full_slots = mei_me_count_full_read_slots,
 566         .read_hdr = mei_me_mecbrw_read,
 567         .read = mei_me_read_slots
 568 };
 569
 570 /**
 571  * mei_me_dev_init - allocates and initializes the mei device structure
 572  *
 573  * @pdev: The pci device structure
 574  *
 575  * returns The mei_device_device pointer on success, NULL on failure.
 576  */
 577 struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
 578 {
 579         struct mei_device *dev;
 580
 581         dev = kzalloc(sizeof(struct mei_device) +
 582                          sizeof(struct mei_me_hw), GFP_KERNEL);
 583         if (!dev)
 584                 return NULL;
 585
 586         mei_device_init(dev);
 587
 588         dev->ops = &mei_me_hw_ops;
 589
 590         dev->pdev = pdev;
 591         return dev;
 592 }
 593