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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / mmc / host / atmel-mci.c
bloba0752e9ce977d47c15017d0d550e16ad3b6d2dc1
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/types.h>
31 #include <linux/platform_data/atmel.h>
32
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/sdio.h>
35
36 #include <mach/atmel-mci.h>
37 #include <linux/atmel-mci.h>
38 #include <linux/atmel_pdc.h>
39
40 #include <asm/io.h>
41 #include <asm/unaligned.h>
42
43 #include "atmel-mci-regs.h"
44
45 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
46 #define ATMCI_DMA_THRESHOLD 16
47
48 enum {
49 EVENT_CMD_RDY = 0,
50 EVENT_XFER_COMPLETE,
51 EVENT_NOTBUSY,
52 EVENT_DATA_ERROR,
53 };
54
55 enum atmel_mci_state {
56 STATE_IDLE = 0,
57 STATE_SENDING_CMD,
58 STATE_DATA_XFER,
59 STATE_WAITING_NOTBUSY,
60 STATE_SENDING_STOP,
61 STATE_END_REQUEST,
62 };
63
64 enum atmci_xfer_dir {
65 XFER_RECEIVE = 0,
66 XFER_TRANSMIT,
67 };
68
69 enum atmci_pdc_buf {
70 PDC_FIRST_BUF = 0,
71 PDC_SECOND_BUF,
72 };
73
74 struct atmel_mci_caps {
75 bool has_dma_conf_reg;
76 bool has_pdc;
77 bool has_cfg_reg;
78 bool has_cstor_reg;
79 bool has_highspeed;
80 bool has_rwproof;
81 bool has_odd_clk_div;
82 bool has_bad_data_ordering;
83 bool need_reset_after_xfer;
84 bool need_blksz_mul_4;
85 bool need_notbusy_for_read_ops;
86 };
87
88 struct atmel_mci_dma {
89 struct dma_chan *chan;
90 struct dma_async_tx_descriptor *data_desc;
91 };
92
93 /**
94 * struct atmel_mci - MMC controller state shared between all slots
95 * @lock: Spinlock protecting the queue and associated data.
96 * @regs: Pointer to MMIO registers.
97 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
98 * @pio_offset: Offset into the current scatterlist entry.
99 * @buffer: Buffer used if we don't have the r/w proof capability. We
100 * don't have the time to switch pdc buffers so we have to use only
101 * one buffer for the full transaction.
102 * @buf_size: size of the buffer.
103 * @phys_buf_addr: buffer address needed for pdc.
104 * @cur_slot: The slot which is currently using the controller.
105 * @mrq: The request currently being processed on @cur_slot,
106 * or NULL if the controller is idle.
107 * @cmd: The command currently being sent to the card, or NULL.
108 * @data: The data currently being transferred, or NULL if no data
109 * transfer is in progress.
110 * @data_size: just data->blocks * data->blksz.
111 * @dma: DMA client state.
112 * @data_chan: DMA channel being used for the current data transfer.
113 * @cmd_status: Snapshot of SR taken upon completion of the current
114 * command. Only valid when EVENT_CMD_COMPLETE is pending.
115 * @data_status: Snapshot of SR taken upon completion of the current
116 * data transfer. Only valid when EVENT_DATA_COMPLETE or
117 * EVENT_DATA_ERROR is pending.
118 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
119 * to be sent.
120 * @tasklet: Tasklet running the request state machine.
121 * @pending_events: Bitmask of events flagged by the interrupt handler
122 * to be processed by the tasklet.
123 * @completed_events: Bitmask of events which the state machine has
124 * processed.
125 * @state: Tasklet state.
126 * @queue: List of slots waiting for access to the controller.
127 * @need_clock_update: Update the clock rate before the next request.
128 * @need_reset: Reset controller before next request.
129 * @timer: Timer to balance the data timeout error flag which cannot rise.
130 * @mode_reg: Value of the MR register.
131 * @cfg_reg: Value of the CFG register.
132 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
133 * rate and timeout calculations.
134 * @mapbase: Physical address of the MMIO registers.
135 * @mck: The peripheral bus clock hooked up to the MMC controller.
136 * @pdev: Platform device associated with the MMC controller.
137 * @slot: Slots sharing this MMC controller.
138 * @caps: MCI capabilities depending on MCI version.
139 * @prepare_data: function to setup MCI before data transfer which
140 * depends on MCI capabilities.
141 * @submit_data: function to start data transfer which depends on MCI
142 * capabilities.
143 * @stop_transfer: function to stop data transfer which depends on MCI
144 * capabilities.
145 *
146 * Locking
147 * =======
148 *
149 * @lock is a softirq-safe spinlock protecting @queue as well as
150 * @cur_slot, @mrq and @state. These must always be updated
151 * at the same time while holding @lock.
152 *
153 * @lock also protects mode_reg and need_clock_update since these are
154 * used to synchronize mode register updates with the queue
155 * processing.
156 *
157 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
158 * and must always be written at the same time as the slot is added to
159 * @queue.
160 *
161 * @pending_events and @completed_events are accessed using atomic bit
162 * operations, so they don't need any locking.
163 *
164 * None of the fields touched by the interrupt handler need any
165 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
166 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
167 * interrupts must be disabled and @data_status updated with a
168 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
169 * CMDRDY interrupt must be disabled and @cmd_status updated with a
170 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
171 * bytes_xfered field of @data must be written. This is ensured by
172 * using barriers.
173 */
174 struct atmel_mci {
175 spinlock_t lock;
176 void __iomem *regs;
177
178 struct scatterlist *sg;
179 unsigned int sg_len;
180 unsigned int pio_offset;
181 unsigned int *buffer;
182 unsigned int buf_size;
183 dma_addr_t buf_phys_addr;
184
185 struct atmel_mci_slot *cur_slot;
186 struct mmc_request *mrq;
187 struct mmc_command *cmd;
188 struct mmc_data *data;
189 unsigned int data_size;
190
191 struct atmel_mci_dma dma;
192 struct dma_chan *data_chan;
193 struct dma_slave_config dma_conf;
194
195 u32 cmd_status;
196 u32 data_status;
197 u32 stop_cmdr;
198
199 struct tasklet_struct tasklet;
200 unsigned long pending_events;
201 unsigned long completed_events;
202 enum atmel_mci_state state;
203 struct list_head queue;
204
205 bool need_clock_update;
206 bool need_reset;
207 struct timer_list timer;
208 u32 mode_reg;
209 u32 cfg_reg;
210 unsigned long bus_hz;
211 unsigned long mapbase;
212 struct clk *mck;
213 struct platform_device *pdev;
214
215 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
216
217 struct atmel_mci_caps caps;
218
219 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
220 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
221 void (*stop_transfer)(struct atmel_mci *host);
222 };
223
224 /**
225 * struct atmel_mci_slot - MMC slot state
226 * @mmc: The mmc_host representing this slot.
227 * @host: The MMC controller this slot is using.
228 * @sdc_reg: Value of SDCR to be written before using this slot.
229 * @sdio_irq: SDIO irq mask for this slot.
230 * @mrq: mmc_request currently being processed or waiting to be
231 * processed, or NULL when the slot is idle.
232 * @queue_node: List node for placing this node in the @queue list of
233 * &struct atmel_mci.
234 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
235 * @flags: Random state bits associated with the slot.
236 * @detect_pin: GPIO pin used for card detection, or negative if not
237 * available.
238 * @wp_pin: GPIO pin used for card write protect sending, or negative
239 * if not available.
240 * @detect_is_active_high: The state of the detect pin when it is active.
241 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
242 */
243 struct atmel_mci_slot {
244 struct mmc_host *mmc;
245 struct atmel_mci *host;
246
247 u32 sdc_reg;
248 u32 sdio_irq;
249
250 struct mmc_request *mrq;
251 struct list_head queue_node;
252
253 unsigned int clock;
254 unsigned long flags;
255 #define ATMCI_CARD_PRESENT 0
256 #define ATMCI_CARD_NEED_INIT 1
257 #define ATMCI_SHUTDOWN 2
258 #define ATMCI_SUSPENDED 3
259
260 int detect_pin;
261 int wp_pin;
262 bool detect_is_active_high;
263
264 struct timer_list detect_timer;
265 };
266
267 #define atmci_test_and_clear_pending(host, event) \
268 test_and_clear_bit(event, &host->pending_events)
269 #define atmci_set_completed(host, event) \
270 set_bit(event, &host->completed_events)
271 #define atmci_set_pending(host, event) \
272 set_bit(event, &host->pending_events)
273
274 /*
275 * The debugfs stuff below is mostly optimized away when
276 * CONFIG_DEBUG_FS is not set.
277 */
278 static int atmci_req_show(struct seq_file *s, void *v)
279 {
280 struct atmel_mci_slot *slot = s->private;
281 struct mmc_request *mrq;
282 struct mmc_command *cmd;
283 struct mmc_command *stop;
284 struct mmc_data *data;
285
286 /* Make sure we get a consistent snapshot */
287 spin_lock_bh(&slot->host->lock);
288 mrq = slot->mrq;
289
290 if (mrq) {
291 cmd = mrq->cmd;
292 data = mrq->data;
293 stop = mrq->stop;
294
295 if (cmd)
296 seq_printf(s,
297 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
298 cmd->opcode, cmd->arg, cmd->flags,
299 cmd->resp[0], cmd->resp[1], cmd->resp[2],
300 cmd->resp[3], cmd->error);
301 if (data)
302 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
303 data->bytes_xfered, data->blocks,
304 data->blksz, data->flags, data->error);
305 if (stop)
306 seq_printf(s,
307 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
308 stop->opcode, stop->arg, stop->flags,
309 stop->resp[0], stop->resp[1], stop->resp[2],
310 stop->resp[3], stop->error);
311 }
312
313 spin_unlock_bh(&slot->host->lock);
314
315 return 0;
316 }
317
318 static int atmci_req_open(struct inode *inode, struct file *file)
319 {
320 return single_open(file, atmci_req_show, inode->i_private);
321 }
322
323 static const struct file_operations atmci_req_fops = {
324 .owner = THIS_MODULE,
325 .open = atmci_req_open,
326 .read = seq_read,
327 .llseek = seq_lseek,
328 .release = single_release,
329 };
330
331 static void atmci_show_status_reg(struct seq_file *s,
332 const char *regname, u32 value)
333 {
334 static const char *sr_bit[] = {
335 [0] = "CMDRDY",
336 [1] = "RXRDY",
337 [2] = "TXRDY",
338 [3] = "BLKE",
339 [4] = "DTIP",
340 [5] = "NOTBUSY",
341 [6] = "ENDRX",
342 [7] = "ENDTX",
343 [8] = "SDIOIRQA",
344 [9] = "SDIOIRQB",
345 [12] = "SDIOWAIT",
346 [14] = "RXBUFF",
347 [15] = "TXBUFE",
348 [16] = "RINDE",
349 [17] = "RDIRE",
350 [18] = "RCRCE",
351 [19] = "RENDE",
352 [20] = "RTOE",
353 [21] = "DCRCE",
354 [22] = "DTOE",
355 [23] = "CSTOE",
356 [24] = "BLKOVRE",
357 [25] = "DMADONE",
358 [26] = "FIFOEMPTY",
359 [27] = "XFRDONE",
360 [30] = "OVRE",
361 [31] = "UNRE",
362 };
363 unsigned int i;
364
365 seq_printf(s, "%s:\t0x%08x", regname, value);
366 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
367 if (value & (1 << i)) {
368 if (sr_bit[i])
369 seq_printf(s, " %s", sr_bit[i]);
370 else
371 seq_puts(s, " UNKNOWN");
372 }
373 }
374 seq_putc(s, '\n');
375 }
376
377 static int atmci_regs_show(struct seq_file *s, void *v)
378 {
379 struct atmel_mci *host = s->private;
380 u32 *buf;
381 int ret = 0;
382
383
384 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
385 if (!buf)
386 return -ENOMEM;
387
388 /*
389 * Grab a more or less consistent snapshot. Note that we're
390 * not disabling interrupts, so IMR and SR may not be
391 * consistent.
392 */
393 ret = clk_prepare_enable(host->mck);
394 if (ret)
395 goto out;
396
397 spin_lock_bh(&host->lock);
398 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
399 spin_unlock_bh(&host->lock);
400
401 clk_disable_unprepare(host->mck);
402
403 seq_printf(s, "MR:\t0x%08x%s%s ",
404 buf[ATMCI_MR / 4],
405 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
406 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
407 if (host->caps.has_odd_clk_div)
408 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
409 ((buf[ATMCI_MR / 4] & 0xff) << 1)
410 | ((buf[ATMCI_MR / 4] >> 16) & 1));
411 else
412 seq_printf(s, "CLKDIV=%u\n",
413 (buf[ATMCI_MR / 4] & 0xff));
414 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
415 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
416 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
417 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
418 buf[ATMCI_BLKR / 4],
419 buf[ATMCI_BLKR / 4] & 0xffff,
420 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
421 if (host->caps.has_cstor_reg)
422 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
423
424 /* Don't read RSPR and RDR; it will consume the data there */
425
426 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
427 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
428
429 if (host->caps.has_dma_conf_reg) {
430 u32 val;
431
432 val = buf[ATMCI_DMA / 4];
433 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
434 val, val & 3,
435 ((val >> 4) & 3) ?
436 1 << (((val >> 4) & 3) + 1) : 1,
437 val & ATMCI_DMAEN ? " DMAEN" : "");
438 }
439 if (host->caps.has_cfg_reg) {
440 u32 val;
441
442 val = buf[ATMCI_CFG / 4];
443 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
444 val,
445 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
446 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
447 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
448 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
449 }
450
451 out:
452 kfree(buf);
453
454 return ret;
455 }
456
457 static int atmci_regs_open(struct inode *inode, struct file *file)
458 {
459 return single_open(file, atmci_regs_show, inode->i_private);
460 }
461
462 static const struct file_operations atmci_regs_fops = {
463 .owner = THIS_MODULE,
464 .open = atmci_regs_open,
465 .read = seq_read,
466 .llseek = seq_lseek,
467 .release = single_release,
468 };
469
470 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
471 {
472 struct mmc_host *mmc = slot->mmc;
473 struct atmel_mci *host = slot->host;
474 struct dentry *root;
475 struct dentry *node;
476
477 root = mmc->debugfs_root;
478 if (!root)
479 return;
480
481 node = debugfs_create_file("regs", S_IRUSR, root, host,
482 &atmci_regs_fops);
483 if (IS_ERR(node))
484 return;
485 if (!node)
486 goto err;
487
488 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
489 if (!node)
490 goto err;
491
492 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
493 if (!node)
494 goto err;
495
496 node = debugfs_create_x32("pending_events", S_IRUSR, root,
497 (u32 *)&host->pending_events);
498 if (!node)
499 goto err;
500
501 node = debugfs_create_x32("completed_events", S_IRUSR, root,
502 (u32 *)&host->completed_events);
503 if (!node)
504 goto err;
505
506 return;
507
508 err:
509 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
510 }
511
512 #if defined(CONFIG_OF)
513 static const struct of_device_id atmci_dt_ids[] = {
514 { .compatible = "atmel,hsmci" },
515 { /* sentinel */ }
516 };
517
518 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
519
520 static struct mci_platform_data*
521 atmci_of_init(struct platform_device *pdev)
522 {
523 struct device_node *np = pdev->dev.of_node;
524 struct device_node *cnp;
525 struct mci_platform_data *pdata;
526 u32 slot_id;
527
528 if (!np) {
529 dev_err(&pdev->dev, "device node not found\n");
530 return ERR_PTR(-EINVAL);
531 }
532
533 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
534 if (!pdata) {
535 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
536 return ERR_PTR(-ENOMEM);
537 }
538
539 for_each_child_of_node(np, cnp) {
540 if (of_property_read_u32(cnp, "reg", &slot_id)) {
541 dev_warn(&pdev->dev, "reg property is missing for %s\n",
542 cnp->full_name);
543 continue;
544 }
545
546 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
547 dev_warn(&pdev->dev, "can't have more than %d slots\n",
548 ATMCI_MAX_NR_SLOTS);
549 break;
550 }
551
552 if (of_property_read_u32(cnp, "bus-width",
553 &pdata->slot[slot_id].bus_width))
554 pdata->slot[slot_id].bus_width = 1;
555
556 pdata->slot[slot_id].detect_pin =
557 of_get_named_gpio(cnp, "cd-gpios", 0);
558
559 pdata->slot[slot_id].detect_is_active_high =
560 of_property_read_bool(cnp, "cd-inverted");
561
562 pdata->slot[slot_id].wp_pin =
563 of_get_named_gpio(cnp, "wp-gpios", 0);
564 }
565
566 return pdata;
567 }
568 #else /* CONFIG_OF */
569 static inline struct mci_platform_data*
570 atmci_of_init(struct platform_device *dev)
571 {
572 return ERR_PTR(-EINVAL);
573 }
574 #endif
575
576 static inline unsigned int atmci_get_version(struct atmel_mci *host)
577 {
578 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
579 }
580
581 static void atmci_timeout_timer(unsigned long data)
582 {
583 struct atmel_mci *host;
584
585 host = (struct atmel_mci *)data;
586
587 dev_dbg(&host->pdev->dev, "software timeout\n");
588
589 if (host->mrq->cmd->data) {
590 host->mrq->cmd->data->error = -ETIMEDOUT;
591 host->data = NULL;
592 /*
593 * With some SDIO modules, sometimes DMA transfer hangs. If
594 * stop_transfer() is not called then the DMA request is not
595 * removed, following ones are queued and never computed.
596 */
597 if (host->state == STATE_DATA_XFER)
598 host->stop_transfer(host);
599 } else {
600 host->mrq->cmd->error = -ETIMEDOUT;
601 host->cmd = NULL;
602 }
603 host->need_reset = 1;
604 host->state = STATE_END_REQUEST;
605 smp_wmb();
606 tasklet_schedule(&host->tasklet);
607 }
608
609 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
610 unsigned int ns)
611 {
612 /*
613 * It is easier here to use us instead of ns for the timeout,
614 * it prevents from overflows during calculation.
615 */
616 unsigned int us = DIV_ROUND_UP(ns, 1000);
617
618 /* Maximum clock frequency is host->bus_hz/2 */
619 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
620 }
621
622 static void atmci_set_timeout(struct atmel_mci *host,
623 struct atmel_mci_slot *slot, struct mmc_data *data)
624 {
625 static unsigned dtomul_to_shift[] = {
626 0, 4, 7, 8, 10, 12, 16, 20
627 };
628 unsigned timeout;
629 unsigned dtocyc;
630 unsigned dtomul;
631
632 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
633 + data->timeout_clks;
634
635 for (dtomul = 0; dtomul < 8; dtomul++) {
636 unsigned shift = dtomul_to_shift[dtomul];
637 dtocyc = (timeout + (1 << shift) - 1) >> shift;
638 if (dtocyc < 15)
639 break;
640 }
641
642 if (dtomul >= 8) {
643 dtomul = 7;
644 dtocyc = 15;
645 }
646
647 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
648 dtocyc << dtomul_to_shift[dtomul]);
649 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
650 }
651
652 /*
653 * Return mask with command flags to be enabled for this command.
654 */
655 static u32 atmci_prepare_command(struct mmc_host *mmc,
656 struct mmc_command *cmd)
657 {
658 struct mmc_data *data;
659 u32 cmdr;
660
661 cmd->error = -EINPROGRESS;
662
663 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
664
665 if (cmd->flags & MMC_RSP_PRESENT) {
666 if (cmd->flags & MMC_RSP_136)
667 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
668 else
669 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
670 }
671
672 /*
673 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
674 * it's too difficult to determine whether this is an ACMD or
675 * not. Better make it 64.
676 */
677 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
678
679 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
680 cmdr |= ATMCI_CMDR_OPDCMD;
681
682 data = cmd->data;
683 if (data) {
684 cmdr |= ATMCI_CMDR_START_XFER;
685
686 if (cmd->opcode == SD_IO_RW_EXTENDED) {
687 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
688 } else {
689 if (data->flags & MMC_DATA_STREAM)
690 cmdr |= ATMCI_CMDR_STREAM;
691 else if (data->blocks > 1)
692 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
693 else
694 cmdr |= ATMCI_CMDR_BLOCK;
695 }
696
697 if (data->flags & MMC_DATA_READ)
698 cmdr |= ATMCI_CMDR_TRDIR_READ;
699 }
700
701 return cmdr;
702 }
703
704 static void atmci_send_command(struct atmel_mci *host,
705 struct mmc_command *cmd, u32 cmd_flags)
706 {
707 WARN_ON(host->cmd);
708 host->cmd = cmd;
709
710 dev_vdbg(&host->pdev->dev,
711 "start command: ARGR=0x%08x CMDR=0x%08x\n",
712 cmd->arg, cmd_flags);
713
714 atmci_writel(host, ATMCI_ARGR, cmd->arg);
715 atmci_writel(host, ATMCI_CMDR, cmd_flags);
716 }
717
718 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
719 {
720 dev_dbg(&host->pdev->dev, "send stop command\n");
721 atmci_send_command(host, data->stop, host->stop_cmdr);
722 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
723 }
724
725 /*
726 * Configure given PDC buffer taking care of alignement issues.
727 * Update host->data_size and host->sg.
728 */
729 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
730 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
731 {
732 u32 pointer_reg, counter_reg;
733 unsigned int buf_size;
734
735 if (dir == XFER_RECEIVE) {
736 pointer_reg = ATMEL_PDC_RPR;
737 counter_reg = ATMEL_PDC_RCR;
738 } else {
739 pointer_reg = ATMEL_PDC_TPR;
740 counter_reg = ATMEL_PDC_TCR;
741 }
742
743 if (buf_nb == PDC_SECOND_BUF) {
744 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
745 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
746 }
747
748 if (!host->caps.has_rwproof) {
749 buf_size = host->buf_size;
750 atmci_writel(host, pointer_reg, host->buf_phys_addr);
751 } else {
752 buf_size = sg_dma_len(host->sg);
753 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
754 }
755
756 if (host->data_size <= buf_size) {
757 if (host->data_size & 0x3) {
758 /* If size is different from modulo 4, transfer bytes */
759 atmci_writel(host, counter_reg, host->data_size);
760 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
761 } else {
762 /* Else transfer 32-bits words */
763 atmci_writel(host, counter_reg, host->data_size / 4);
764 }
765 host->data_size = 0;
766 } else {
767 /* We assume the size of a page is 32-bits aligned */
768 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
769 host->data_size -= sg_dma_len(host->sg);
770 if (host->data_size)
771 host->sg = sg_next(host->sg);
772 }
773 }
774
775 /*
776 * Configure PDC buffer according to the data size ie configuring one or two
777 * buffers. Don't use this function if you want to configure only the second
778 * buffer. In this case, use atmci_pdc_set_single_buf.
779 */
780 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
781 {
782 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
783 if (host->data_size)
784 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
785 }
786
787 /*
788 * Unmap sg lists, called when transfer is finished.
789 */
790 static void atmci_pdc_cleanup(struct atmel_mci *host)
791 {
792 struct mmc_data *data = host->data;
793
794 if (data)
795 dma_unmap_sg(&host->pdev->dev,
796 data->sg, data->sg_len,
797 ((data->flags & MMC_DATA_WRITE)
798 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
799 }
800
801 /*
802 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
803 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
804 * interrupt needed for both transfer directions.
805 */
806 static void atmci_pdc_complete(struct atmel_mci *host)
807 {
808 int transfer_size = host->data->blocks * host->data->blksz;
809 int i;
810
811 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
812
813 if ((!host->caps.has_rwproof)
814 && (host->data->flags & MMC_DATA_READ)) {
815 if (host->caps.has_bad_data_ordering)
816 for (i = 0; i < transfer_size; i++)
817 host->buffer[i] = swab32(host->buffer[i]);
818 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
819 host->buffer, transfer_size);
820 }
821
822 atmci_pdc_cleanup(host);
823
824 /*
825 * If the card was removed, data will be NULL. No point trying
826 * to send the stop command or waiting for NBUSY in this case.
827 */
828 if (host->data) {
829 dev_dbg(&host->pdev->dev,
830 "(%s) set pending xfer complete\n", __func__);
831 atmci_set_pending(host, EVENT_XFER_COMPLETE);
832 tasklet_schedule(&host->tasklet);
833 }
834 }
835
836 static void atmci_dma_cleanup(struct atmel_mci *host)
837 {
838 struct mmc_data *data = host->data;
839
840 if (data)
841 dma_unmap_sg(host->dma.chan->device->dev,
842 data->sg, data->sg_len,
843 ((data->flags & MMC_DATA_WRITE)
844 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
845 }
846
847 /*
848 * This function is called by the DMA driver from tasklet context.
849 */
850 static void atmci_dma_complete(void *arg)
851 {
852 struct atmel_mci *host = arg;
853 struct mmc_data *data = host->data;
854
855 dev_vdbg(&host->pdev->dev, "DMA complete\n");
856
857 if (host->caps.has_dma_conf_reg)
858 /* Disable DMA hardware handshaking on MCI */
859 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
860
861 atmci_dma_cleanup(host);
862
863 /*
864 * If the card was removed, data will be NULL. No point trying
865 * to send the stop command or waiting for NBUSY in this case.
866 */
867 if (data) {
868 dev_dbg(&host->pdev->dev,
869 "(%s) set pending xfer complete\n", __func__);
870 atmci_set_pending(host, EVENT_XFER_COMPLETE);
871 tasklet_schedule(&host->tasklet);
872
873 /*
874 * Regardless of what the documentation says, we have
875 * to wait for NOTBUSY even after block read
876 * operations.
877 *
878 * When the DMA transfer is complete, the controller
879 * may still be reading the CRC from the card, i.e.
880 * the data transfer is still in progress and we
881 * haven't seen all the potential error bits yet.
882 *
883 * The interrupt handler will schedule a different
884 * tasklet to finish things up when the data transfer
885 * is completely done.
886 *
887 * We may not complete the mmc request here anyway
888 * because the mmc layer may call back and cause us to
889 * violate the "don't submit new operations from the
890 * completion callback" rule of the dma engine
891 * framework.
892 */
893 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
894 }
895 }
896
897 /*
898 * Returns a mask of interrupt flags to be enabled after the whole
899 * request has been prepared.
900 */
901 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
902 {
903 u32 iflags;
904
905 data->error = -EINPROGRESS;
906
907 host->sg = data->sg;
908 host->sg_len = data->sg_len;
909 host->data = data;
910 host->data_chan = NULL;
911
912 iflags = ATMCI_DATA_ERROR_FLAGS;
913
914 /*
915 * Errata: MMC data write operation with less than 12
916 * bytes is impossible.
917 *
918 * Errata: MCI Transmit Data Register (TDR) FIFO
919 * corruption when length is not multiple of 4.
920 */
921 if (data->blocks * data->blksz < 12
922 || (data->blocks * data->blksz) & 3)
923 host->need_reset = true;
924
925 host->pio_offset = 0;
926 if (data->flags & MMC_DATA_READ)
927 iflags |= ATMCI_RXRDY;
928 else
929 iflags |= ATMCI_TXRDY;
930
931 return iflags;
932 }
933
934 /*
935 * Set interrupt flags and set block length into the MCI mode register even
936 * if this value is also accessible in the MCI block register. It seems to be
937 * necessary before the High Speed MCI version. It also map sg and configure
938 * PDC registers.
939 */
940 static u32
941 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
942 {
943 u32 iflags, tmp;
944 unsigned int sg_len;
945 enum dma_data_direction dir;
946 int i;
947
948 data->error = -EINPROGRESS;
949
950 host->data = data;
951 host->sg = data->sg;
952 iflags = ATMCI_DATA_ERROR_FLAGS;
953
954 /* Enable pdc mode */
955 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
956
957 if (data->flags & MMC_DATA_READ) {
958 dir = DMA_FROM_DEVICE;
959 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
960 } else {
961 dir = DMA_TO_DEVICE;
962 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
963 }
964
965 /* Set BLKLEN */
966 tmp = atmci_readl(host, ATMCI_MR);
967 tmp &= 0x0000ffff;
968 tmp |= ATMCI_BLKLEN(data->blksz);
969 atmci_writel(host, ATMCI_MR, tmp);
970
971 /* Configure PDC */
972 host->data_size = data->blocks * data->blksz;
973 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
974
975 if ((!host->caps.has_rwproof)
976 && (host->data->flags & MMC_DATA_WRITE)) {
977 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
978 host->buffer, host->data_size);
979 if (host->caps.has_bad_data_ordering)
980 for (i = 0; i < host->data_size; i++)
981 host->buffer[i] = swab32(host->buffer[i]);
982 }
983
984 if (host->data_size)
985 atmci_pdc_set_both_buf(host,
986 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
987
988 return iflags;
989 }
990
991 static u32
992 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
993 {
994 struct dma_chan *chan;
995 struct dma_async_tx_descriptor *desc;
996 struct scatterlist *sg;
997 unsigned int i;
998 enum dma_data_direction direction;
999 enum dma_transfer_direction slave_dirn;
1000 unsigned int sglen;
1001 u32 maxburst;
1002 u32 iflags;
1003
1004 data->error = -EINPROGRESS;
1005
1006 WARN_ON(host->data);
1007 host->sg = NULL;
1008 host->data = data;
1009
1010 iflags = ATMCI_DATA_ERROR_FLAGS;
1011
1012 /*
1013 * We don't do DMA on "complex" transfers, i.e. with
1014 * non-word-aligned buffers or lengths. Also, we don't bother
1015 * with all the DMA setup overhead for short transfers.
1016 */
1017 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1018 return atmci_prepare_data(host, data);
1019 if (data->blksz & 3)
1020 return atmci_prepare_data(host, data);
1021
1022 for_each_sg(data->sg, sg, data->sg_len, i) {
1023 if (sg->offset & 3 || sg->length & 3)
1024 return atmci_prepare_data(host, data);
1025 }
1026
1027 /* If we don't have a channel, we can't do DMA */
1028 chan = host->dma.chan;
1029 if (chan)
1030 host->data_chan = chan;
1031
1032 if (!chan)
1033 return -ENODEV;
1034
1035 if (data->flags & MMC_DATA_READ) {
1036 direction = DMA_FROM_DEVICE;
1037 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1038 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1039 } else {
1040 direction = DMA_TO_DEVICE;
1041 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1042 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1043 }
1044
1045 if (host->caps.has_dma_conf_reg)
1046 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1047 ATMCI_DMAEN);
1048
1049 sglen = dma_map_sg(chan->device->dev, data->sg,
1050 data->sg_len, direction);
1051
1052 dmaengine_slave_config(chan, &host->dma_conf);
1053 desc = dmaengine_prep_slave_sg(chan,
1054 data->sg, sglen, slave_dirn,
1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1056 if (!desc)
1057 goto unmap_exit;
1058
1059 host->dma.data_desc = desc;
1060 desc->callback = atmci_dma_complete;
1061 desc->callback_param = host;
1062
1063 return iflags;
1064 unmap_exit:
1065 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1066 return -ENOMEM;
1067 }
1068
1069 static void
1070 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1071 {
1072 return;
1073 }
1074
1075 /*
1076 * Start PDC according to transfer direction.
1077 */
1078 static void
1079 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1080 {
1081 if (data->flags & MMC_DATA_READ)
1082 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1083 else
1084 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1085 }
1086
1087 static void
1088 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1089 {
1090 struct dma_chan *chan = host->data_chan;
1091 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1092
1093 if (chan) {
1094 dmaengine_submit(desc);
1095 dma_async_issue_pending(chan);
1096 }
1097 }
1098
1099 static void atmci_stop_transfer(struct atmel_mci *host)
1100 {
1101 dev_dbg(&host->pdev->dev,
1102 "(%s) set pending xfer complete\n", __func__);
1103 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1104 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1105 }
1106
1107 /*
1108 * Stop data transfer because error(s) occurred.
1109 */
1110 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1111 {
1112 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1113 }
1114
1115 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1116 {
1117 struct dma_chan *chan = host->data_chan;
1118
1119 if (chan) {
1120 dmaengine_terminate_all(chan);
1121 atmci_dma_cleanup(host);
1122 } else {
1123 /* Data transfer was stopped by the interrupt handler */
1124 dev_dbg(&host->pdev->dev,
1125 "(%s) set pending xfer complete\n", __func__);
1126 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1127 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1128 }
1129 }
1130
1131 /*
1132 * Start a request: prepare data if needed, prepare the command and activate
1133 * interrupts.
1134 */
1135 static void atmci_start_request(struct atmel_mci *host,
1136 struct atmel_mci_slot *slot)
1137 {
1138 struct mmc_request *mrq;
1139 struct mmc_command *cmd;
1140 struct mmc_data *data;
1141 u32 iflags;
1142 u32 cmdflags;
1143
1144 mrq = slot->mrq;
1145 host->cur_slot = slot;
1146 host->mrq = mrq;
1147
1148 host->pending_events = 0;
1149 host->completed_events = 0;
1150 host->cmd_status = 0;
1151 host->data_status = 0;
1152
1153 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1154
1155 if (host->need_reset || host->caps.need_reset_after_xfer) {
1156 iflags = atmci_readl(host, ATMCI_IMR);
1157 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1158 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1159 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1160 atmci_writel(host, ATMCI_MR, host->mode_reg);
1161 if (host->caps.has_cfg_reg)
1162 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1163 atmci_writel(host, ATMCI_IER, iflags);
1164 host->need_reset = false;
1165 }
1166 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1167
1168 iflags = atmci_readl(host, ATMCI_IMR);
1169 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1170 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1171 iflags);
1172
1173 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1174 /* Send init sequence (74 clock cycles) */
1175 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1176 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1177 cpu_relax();
1178 }
1179 iflags = 0;
1180 data = mrq->data;
1181 if (data) {
1182 atmci_set_timeout(host, slot, data);
1183
1184 /* Must set block count/size before sending command */
1185 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1186 | ATMCI_BLKLEN(data->blksz));
1187 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1188 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1189
1190 iflags |= host->prepare_data(host, data);
1191 }
1192
1193 iflags |= ATMCI_CMDRDY;
1194 cmd = mrq->cmd;
1195 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1196
1197 /*
1198 * DMA transfer should be started before sending the command to avoid
1199 * unexpected errors especially for read operations in SDIO mode.
1200 * Unfortunately, in PDC mode, command has to be sent before starting
1201 * the transfer.
1202 */
1203 if (host->submit_data != &atmci_submit_data_dma)
1204 atmci_send_command(host, cmd, cmdflags);
1205
1206 if (data)
1207 host->submit_data(host, data);
1208
1209 if (host->submit_data == &atmci_submit_data_dma)
1210 atmci_send_command(host, cmd, cmdflags);
1211
1212 if (mrq->stop) {
1213 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1214 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1215 if (!(data->flags & MMC_DATA_WRITE))
1216 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1217 if (data->flags & MMC_DATA_STREAM)
1218 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1219 else
1220 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1221 }
1222
1223 /*
1224 * We could have enabled interrupts earlier, but I suspect
1225 * that would open up a nice can of interesting race
1226 * conditions (e.g. command and data complete, but stop not
1227 * prepared yet.)
1228 */
1229 atmci_writel(host, ATMCI_IER, iflags);
1230
1231 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1232 }
1233
1234 static void atmci_queue_request(struct atmel_mci *host,
1235 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1236 {
1237 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1238 host->state);
1239
1240 spin_lock_bh(&host->lock);
1241 slot->mrq = mrq;
1242 if (host->state == STATE_IDLE) {
1243 host->state = STATE_SENDING_CMD;
1244 atmci_start_request(host, slot);
1245 } else {
1246 dev_dbg(&host->pdev->dev, "queue request\n");
1247 list_add_tail(&slot->queue_node, &host->queue);
1248 }
1249 spin_unlock_bh(&host->lock);
1250 }
1251
1252 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1253 {
1254 struct atmel_mci_slot *slot = mmc_priv(mmc);
1255 struct atmel_mci *host = slot->host;
1256 struct mmc_data *data;
1257
1258 WARN_ON(slot->mrq);
1259 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1260
1261 /*
1262 * We may "know" the card is gone even though there's still an
1263 * electrical connection. If so, we really need to communicate
1264 * this to the MMC core since there won't be any more
1265 * interrupts as the card is completely removed. Otherwise,
1266 * the MMC core might believe the card is still there even
1267 * though the card was just removed very slowly.
1268 */
1269 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1270 mrq->cmd->error = -ENOMEDIUM;
1271 mmc_request_done(mmc, mrq);
1272 return;
1273 }
1274
1275 /* We don't support multiple blocks of weird lengths. */
1276 data = mrq->data;
1277 if (data && data->blocks > 1 && data->blksz & 3) {
1278 mrq->cmd->error = -EINVAL;
1279 mmc_request_done(mmc, mrq);
1280 }
1281
1282 atmci_queue_request(host, slot, mrq);
1283 }
1284
1285 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1286 {
1287 struct atmel_mci_slot *slot = mmc_priv(mmc);
1288 struct atmel_mci *host = slot->host;
1289 unsigned int i;
1290 bool unprepare_clk;
1291
1292 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1293 switch (ios->bus_width) {
1294 case MMC_BUS_WIDTH_1:
1295 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1296 break;
1297 case MMC_BUS_WIDTH_4:
1298 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1299 break;
1300 }
1301
1302 if (ios->clock) {
1303 unsigned int clock_min = ~0U;
1304 u32 clkdiv;
1305
1306 clk_prepare(host->mck);
1307 unprepare_clk = true;
1308
1309 spin_lock_bh(&host->lock);
1310 if (!host->mode_reg) {
1311 clk_enable(host->mck);
1312 unprepare_clk = false;
1313 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1314 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1315 if (host->caps.has_cfg_reg)
1316 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1317 }
1318
1319 /*
1320 * Use mirror of ios->clock to prevent race with mmc
1321 * core ios update when finding the minimum.
1322 */
1323 slot->clock = ios->clock;
1324 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1325 if (host->slot[i] && host->slot[i]->clock
1326 && host->slot[i]->clock < clock_min)
1327 clock_min = host->slot[i]->clock;
1328 }
1329
1330 /* Calculate clock divider */
1331 if (host->caps.has_odd_clk_div) {
1332 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1333 if (clkdiv > 511) {
1334 dev_warn(&mmc->class_dev,
1335 "clock %u too slow; using %lu\n",
1336 clock_min, host->bus_hz / (511 + 2));
1337 clkdiv = 511;
1338 }
1339 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1340 | ATMCI_MR_CLKODD(clkdiv & 1);
1341 } else {
1342 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1343 if (clkdiv > 255) {
1344 dev_warn(&mmc->class_dev,
1345 "clock %u too slow; using %lu\n",
1346 clock_min, host->bus_hz / (2 * 256));
1347 clkdiv = 255;
1348 }
1349 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1350 }
1351
1352 /*
1353 * WRPROOF and RDPROOF prevent overruns/underruns by
1354 * stopping the clock when the FIFO is full/empty.
1355 * This state is not expected to last for long.
1356 */
1357 if (host->caps.has_rwproof)
1358 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1359
1360 if (host->caps.has_cfg_reg) {
1361 /* setup High Speed mode in relation with card capacity */
1362 if (ios->timing == MMC_TIMING_SD_HS)
1363 host->cfg_reg |= ATMCI_CFG_HSMODE;
1364 else
1365 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1366 }
1367
1368 if (list_empty(&host->queue)) {
1369 atmci_writel(host, ATMCI_MR, host->mode_reg);
1370 if (host->caps.has_cfg_reg)
1371 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1372 } else {
1373 host->need_clock_update = true;
1374 }
1375
1376 spin_unlock_bh(&host->lock);
1377 } else {
1378 bool any_slot_active = false;
1379
1380 unprepare_clk = false;
1381
1382 spin_lock_bh(&host->lock);
1383 slot->clock = 0;
1384 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1385 if (host->slot[i] && host->slot[i]->clock) {
1386 any_slot_active = true;
1387 break;
1388 }
1389 }
1390 if (!any_slot_active) {
1391 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1392 if (host->mode_reg) {
1393 atmci_readl(host, ATMCI_MR);
1394 clk_disable(host->mck);
1395 unprepare_clk = true;
1396 }
1397 host->mode_reg = 0;
1398 }
1399 spin_unlock_bh(&host->lock);
1400 }
1401
1402 if (unprepare_clk)
1403 clk_unprepare(host->mck);
1404
1405 switch (ios->power_mode) {
1406 case MMC_POWER_UP:
1407 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1408 break;
1409 default:
1410 /*
1411 * TODO: None of the currently available AVR32-based
1412 * boards allow MMC power to be turned off. Implement
1413 * power control when this can be tested properly.
1414 *
1415 * We also need to hook this into the clock management
1416 * somehow so that newly inserted cards aren't
1417 * subjected to a fast clock before we have a chance
1418 * to figure out what the maximum rate is. Currently,
1419 * there's no way to avoid this, and there never will
1420 * be for boards that don't support power control.
1421 */
1422 break;
1423 }
1424 }
1425
1426 static int atmci_get_ro(struct mmc_host *mmc)
1427 {
1428 int read_only = -ENOSYS;
1429 struct atmel_mci_slot *slot = mmc_priv(mmc);
1430
1431 if (gpio_is_valid(slot->wp_pin)) {
1432 read_only = gpio_get_value(slot->wp_pin);
1433 dev_dbg(&mmc->class_dev, "card is %s\n",
1434 read_only ? "read-only" : "read-write");
1435 }
1436
1437 return read_only;
1438 }
1439
1440 static int atmci_get_cd(struct mmc_host *mmc)
1441 {
1442 int present = -ENOSYS;
1443 struct atmel_mci_slot *slot = mmc_priv(mmc);
1444
1445 if (gpio_is_valid(slot->detect_pin)) {
1446 present = !(gpio_get_value(slot->detect_pin) ^
1447 slot->detect_is_active_high);
1448 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1449 present ? "" : "not ");
1450 }
1451
1452 return present;
1453 }
1454
1455 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1456 {
1457 struct atmel_mci_slot *slot = mmc_priv(mmc);
1458 struct atmel_mci *host = slot->host;
1459
1460 if (enable)
1461 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1462 else
1463 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1464 }
1465
1466 static const struct mmc_host_ops atmci_ops = {
1467 .request = atmci_request,
1468 .set_ios = atmci_set_ios,
1469 .get_ro = atmci_get_ro,
1470 .get_cd = atmci_get_cd,
1471 .enable_sdio_irq = atmci_enable_sdio_irq,
1472 };
1473
1474 /* Called with host->lock held */
1475 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1476 __releases(&host->lock)
1477 __acquires(&host->lock)
1478 {
1479 struct atmel_mci_slot *slot = NULL;
1480 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1481
1482 WARN_ON(host->cmd || host->data);
1483
1484 /*
1485 * Update the MMC clock rate if necessary. This may be
1486 * necessary if set_ios() is called when a different slot is
1487 * busy transferring data.
1488 */
1489 if (host->need_clock_update) {
1490 atmci_writel(host, ATMCI_MR, host->mode_reg);
1491 if (host->caps.has_cfg_reg)
1492 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1493 }
1494
1495 host->cur_slot->mrq = NULL;
1496 host->mrq = NULL;
1497 if (!list_empty(&host->queue)) {
1498 slot = list_entry(host->queue.next,
1499 struct atmel_mci_slot, queue_node);
1500 list_del(&slot->queue_node);
1501 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1502 mmc_hostname(slot->mmc));
1503 host->state = STATE_SENDING_CMD;
1504 atmci_start_request(host, slot);
1505 } else {
1506 dev_vdbg(&host->pdev->dev, "list empty\n");
1507 host->state = STATE_IDLE;
1508 }
1509
1510 del_timer(&host->timer);
1511
1512 spin_unlock(&host->lock);
1513 mmc_request_done(prev_mmc, mrq);
1514 spin_lock(&host->lock);
1515 }
1516
1517 static void atmci_command_complete(struct atmel_mci *host,
1518 struct mmc_command *cmd)
1519 {
1520 u32 status = host->cmd_status;
1521
1522 /* Read the response from the card (up to 16 bytes) */
1523 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1524 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1525 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1526 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1527
1528 if (status & ATMCI_RTOE)
1529 cmd->error = -ETIMEDOUT;
1530 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1531 cmd->error = -EILSEQ;
1532 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1533 cmd->error = -EIO;
1534 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1535 if (host->caps.need_blksz_mul_4) {
1536 cmd->error = -EINVAL;
1537 host->need_reset = 1;
1538 }
1539 } else
1540 cmd->error = 0;
1541 }
1542
1543 static void atmci_detect_change(unsigned long data)
1544 {
1545 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1546 bool present;
1547 bool present_old;
1548
1549 /*
1550 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1551 * freeing the interrupt. We must not re-enable the interrupt
1552 * if it has been freed, and if we're shutting down, it
1553 * doesn't really matter whether the card is present or not.
1554 */
1555 smp_rmb();
1556 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1557 return;
1558
1559 enable_irq(gpio_to_irq(slot->detect_pin));
1560 present = !(gpio_get_value(slot->detect_pin) ^
1561 slot->detect_is_active_high);
1562 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1563
1564 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1565 present, present_old);
1566
1567 if (present != present_old) {
1568 struct atmel_mci *host = slot->host;
1569 struct mmc_request *mrq;
1570
1571 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1572 present ? "inserted" : "removed");
1573
1574 spin_lock(&host->lock);
1575
1576 if (!present)
1577 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1578 else
1579 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1580
1581 /* Clean up queue if present */
1582 mrq = slot->mrq;
1583 if (mrq) {
1584 if (mrq == host->mrq) {
1585 /*
1586 * Reset controller to terminate any ongoing
1587 * commands or data transfers.
1588 */
1589 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1590 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1591 atmci_writel(host, ATMCI_MR, host->mode_reg);
1592 if (host->caps.has_cfg_reg)
1593 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1594
1595 host->data = NULL;
1596 host->cmd = NULL;
1597
1598 switch (host->state) {
1599 case STATE_IDLE:
1600 break;
1601 case STATE_SENDING_CMD:
1602 mrq->cmd->error = -ENOMEDIUM;
1603 if (mrq->data)
1604 host->stop_transfer(host);
1605 break;
1606 case STATE_DATA_XFER:
1607 mrq->data->error = -ENOMEDIUM;
1608 host->stop_transfer(host);
1609 break;
1610 case STATE_WAITING_NOTBUSY:
1611 mrq->data->error = -ENOMEDIUM;
1612 break;
1613 case STATE_SENDING_STOP:
1614 mrq->stop->error = -ENOMEDIUM;
1615 break;
1616 case STATE_END_REQUEST:
1617 break;
1618 }
1619
1620 atmci_request_end(host, mrq);
1621 } else {
1622 list_del(&slot->queue_node);
1623 mrq->cmd->error = -ENOMEDIUM;
1624 if (mrq->data)
1625 mrq->data->error = -ENOMEDIUM;
1626 if (mrq->stop)
1627 mrq->stop->error = -ENOMEDIUM;
1628
1629 spin_unlock(&host->lock);
1630 mmc_request_done(slot->mmc, mrq);
1631 spin_lock(&host->lock);
1632 }
1633 }
1634 spin_unlock(&host->lock);
1635
1636 mmc_detect_change(slot->mmc, 0);
1637 }
1638 }
1639
1640 static void atmci_tasklet_func(unsigned long priv)
1641 {
1642 struct atmel_mci *host = (struct atmel_mci *)priv;
1643 struct mmc_request *mrq = host->mrq;
1644 struct mmc_data *data = host->data;
1645 enum atmel_mci_state state = host->state;
1646 enum atmel_mci_state prev_state;
1647 u32 status;
1648
1649 spin_lock(&host->lock);
1650
1651 state = host->state;
1652
1653 dev_vdbg(&host->pdev->dev,
1654 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1655 state, host->pending_events, host->completed_events,
1656 atmci_readl(host, ATMCI_IMR));
1657
1658 do {
1659 prev_state = state;
1660 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1661
1662 switch (state) {
1663 case STATE_IDLE:
1664 break;
1665
1666 case STATE_SENDING_CMD:
1667 /*
1668 * Command has been sent, we are waiting for command
1669 * ready. Then we have three next states possible:
1670 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1671 * command needing it or DATA_XFER if there is data.
1672 */
1673 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1674 if (!atmci_test_and_clear_pending(host,
1675 EVENT_CMD_RDY))
1676 break;
1677
1678 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1679 host->cmd = NULL;
1680 atmci_set_completed(host, EVENT_CMD_RDY);
1681 atmci_command_complete(host, mrq->cmd);
1682 if (mrq->data) {
1683 dev_dbg(&host->pdev->dev,
1684 "command with data transfer");
1685 /*
1686 * If there is a command error don't start
1687 * data transfer.
1688 */
1689 if (mrq->cmd->error) {
1690 host->stop_transfer(host);
1691 host->data = NULL;
1692 atmci_writel(host, ATMCI_IDR,
1693 ATMCI_TXRDY | ATMCI_RXRDY
1694 | ATMCI_DATA_ERROR_FLAGS);
1695 state = STATE_END_REQUEST;
1696 } else
1697 state = STATE_DATA_XFER;
1698 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1699 dev_dbg(&host->pdev->dev,
1700 "command response need waiting notbusy");
1701 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1702 state = STATE_WAITING_NOTBUSY;
1703 } else
1704 state = STATE_END_REQUEST;
1705
1706 break;
1707
1708 case STATE_DATA_XFER:
1709 if (atmci_test_and_clear_pending(host,
1710 EVENT_DATA_ERROR)) {
1711 dev_dbg(&host->pdev->dev, "set completed data error\n");
1712 atmci_set_completed(host, EVENT_DATA_ERROR);
1713 state = STATE_END_REQUEST;
1714 break;
1715 }
1716
1717 /*
1718 * A data transfer is in progress. The event expected
1719 * to move to the next state depends of data transfer
1720 * type (PDC or DMA). Once transfer done we can move
1721 * to the next step which is WAITING_NOTBUSY in write
1722 * case and directly SENDING_STOP in read case.
1723 */
1724 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1725 if (!atmci_test_and_clear_pending(host,
1726 EVENT_XFER_COMPLETE))
1727 break;
1728
1729 dev_dbg(&host->pdev->dev,
1730 "(%s) set completed xfer complete\n",
1731 __func__);
1732 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1733
1734 if (host->caps.need_notbusy_for_read_ops ||
1735 (host->data->flags & MMC_DATA_WRITE)) {
1736 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1737 state = STATE_WAITING_NOTBUSY;
1738 } else if (host->mrq->stop) {
1739 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1740 atmci_send_stop_cmd(host, data);
1741 state = STATE_SENDING_STOP;
1742 } else {
1743 host->data = NULL;
1744 data->bytes_xfered = data->blocks * data->blksz;
1745 data->error = 0;
1746 state = STATE_END_REQUEST;
1747 }
1748 break;
1749
1750 case STATE_WAITING_NOTBUSY:
1751 /*
1752 * We can be in the state for two reasons: a command
1753 * requiring waiting not busy signal (stop command
1754 * included) or a write operation. In the latest case,
1755 * we need to send a stop command.
1756 */
1757 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1758 if (!atmci_test_and_clear_pending(host,
1759 EVENT_NOTBUSY))
1760 break;
1761
1762 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1763 atmci_set_completed(host, EVENT_NOTBUSY);
1764
1765 if (host->data) {
1766 /*
1767 * For some commands such as CMD53, even if
1768 * there is data transfer, there is no stop
1769 * command to send.
1770 */
1771 if (host->mrq->stop) {
1772 atmci_writel(host, ATMCI_IER,
1773 ATMCI_CMDRDY);
1774 atmci_send_stop_cmd(host, data);
1775 state = STATE_SENDING_STOP;
1776 } else {
1777 host->data = NULL;
1778 data->bytes_xfered = data->blocks
1779 * data->blksz;
1780 data->error = 0;
1781 state = STATE_END_REQUEST;
1782 }
1783 } else
1784 state = STATE_END_REQUEST;
1785 break;
1786
1787 case STATE_SENDING_STOP:
1788 /*
1789 * In this state, it is important to set host->data to
1790 * NULL (which is tested in the waiting notbusy state)
1791 * in order to go to the end request state instead of
1792 * sending stop again.
1793 */
1794 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1795 if (!atmci_test_and_clear_pending(host,
1796 EVENT_CMD_RDY))
1797 break;
1798
1799 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1800 host->cmd = NULL;
1801 data->bytes_xfered = data->blocks * data->blksz;
1802 data->error = 0;
1803 atmci_command_complete(host, mrq->stop);
1804 if (mrq->stop->error) {
1805 host->stop_transfer(host);
1806 atmci_writel(host, ATMCI_IDR,
1807 ATMCI_TXRDY | ATMCI_RXRDY
1808 | ATMCI_DATA_ERROR_FLAGS);
1809 state = STATE_END_REQUEST;
1810 } else {
1811 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1812 state = STATE_WAITING_NOTBUSY;
1813 }
1814 host->data = NULL;
1815 break;
1816
1817 case STATE_END_REQUEST:
1818 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1819 | ATMCI_DATA_ERROR_FLAGS);
1820 status = host->data_status;
1821 if (unlikely(status)) {
1822 host->stop_transfer(host);
1823 host->data = NULL;
1824 if (data) {
1825 if (status & ATMCI_DTOE) {
1826 data->error = -ETIMEDOUT;
1827 } else if (status & ATMCI_DCRCE) {
1828 data->error = -EILSEQ;
1829 } else {
1830 data->error = -EIO;
1831 }
1832 }
1833 }
1834
1835 atmci_request_end(host, host->mrq);
1836 state = STATE_IDLE;
1837 break;
1838 }
1839 } while (state != prev_state);
1840
1841 host->state = state;
1842
1843 spin_unlock(&host->lock);
1844 }
1845
1846 static void atmci_read_data_pio(struct atmel_mci *host)
1847 {
1848 struct scatterlist *sg = host->sg;
1849 void *buf = sg_virt(sg);
1850 unsigned int offset = host->pio_offset;
1851 struct mmc_data *data = host->data;
1852 u32 value;
1853 u32 status;
1854 unsigned int nbytes = 0;
1855
1856 do {
1857 value = atmci_readl(host, ATMCI_RDR);
1858 if (likely(offset + 4 <= sg->length)) {
1859 put_unaligned(value, (u32 *)(buf + offset));
1860
1861 offset += 4;
1862 nbytes += 4;
1863
1864 if (offset == sg->length) {
1865 flush_dcache_page(sg_page(sg));
1866 host->sg = sg = sg_next(sg);
1867 host->sg_len--;
1868 if (!sg || !host->sg_len)
1869 goto done;
1870
1871 offset = 0;
1872 buf = sg_virt(sg);
1873 }
1874 } else {
1875 unsigned int remaining = sg->length - offset;
1876 memcpy(buf + offset, &value, remaining);
1877 nbytes += remaining;
1878
1879 flush_dcache_page(sg_page(sg));
1880 host->sg = sg = sg_next(sg);
1881 host->sg_len--;
1882 if (!sg || !host->sg_len)
1883 goto done;
1884
1885 offset = 4 - remaining;
1886 buf = sg_virt(sg);
1887 memcpy(buf, (u8 *)&value + remaining, offset);
1888 nbytes += offset;
1889 }
1890
1891 status = atmci_readl(host, ATMCI_SR);
1892 if (status & ATMCI_DATA_ERROR_FLAGS) {
1893 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1894 | ATMCI_DATA_ERROR_FLAGS));
1895 host->data_status = status;
1896 data->bytes_xfered += nbytes;
1897 return;
1898 }
1899 } while (status & ATMCI_RXRDY);
1900
1901 host->pio_offset = offset;
1902 data->bytes_xfered += nbytes;
1903
1904 return;
1905
1906 done:
1907 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1908 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1909 data->bytes_xfered += nbytes;
1910 smp_wmb();
1911 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1912 }
1913
1914 static void atmci_write_data_pio(struct atmel_mci *host)
1915 {
1916 struct scatterlist *sg = host->sg;
1917 void *buf = sg_virt(sg);
1918 unsigned int offset = host->pio_offset;
1919 struct mmc_data *data = host->data;
1920 u32 value;
1921 u32 status;
1922 unsigned int nbytes = 0;
1923
1924 do {
1925 if (likely(offset + 4 <= sg->length)) {
1926 value = get_unaligned((u32 *)(buf + offset));
1927 atmci_writel(host, ATMCI_TDR, value);
1928
1929 offset += 4;
1930 nbytes += 4;
1931 if (offset == sg->length) {
1932 host->sg = sg = sg_next(sg);
1933 host->sg_len--;
1934 if (!sg || !host->sg_len)
1935 goto done;
1936
1937 offset = 0;
1938 buf = sg_virt(sg);
1939 }
1940 } else {
1941 unsigned int remaining = sg->length - offset;
1942
1943 value = 0;
1944 memcpy(&value, buf + offset, remaining);
1945 nbytes += remaining;
1946
1947 host->sg = sg = sg_next(sg);
1948 host->sg_len--;
1949 if (!sg || !host->sg_len) {
1950 atmci_writel(host, ATMCI_TDR, value);
1951 goto done;
1952 }
1953
1954 offset = 4 - remaining;
1955 buf = sg_virt(sg);
1956 memcpy((u8 *)&value + remaining, buf, offset);
1957 atmci_writel(host, ATMCI_TDR, value);
1958 nbytes += offset;
1959 }
1960
1961 status = atmci_readl(host, ATMCI_SR);
1962 if (status & ATMCI_DATA_ERROR_FLAGS) {
1963 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1964 | ATMCI_DATA_ERROR_FLAGS));
1965 host->data_status = status;
1966 data->bytes_xfered += nbytes;
1967 return;
1968 }
1969 } while (status & ATMCI_TXRDY);
1970
1971 host->pio_offset = offset;
1972 data->bytes_xfered += nbytes;
1973
1974 return;
1975
1976 done:
1977 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1978 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1979 data->bytes_xfered += nbytes;
1980 smp_wmb();
1981 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1982 }
1983
1984 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1985 {
1986 int i;
1987
1988 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1989 struct atmel_mci_slot *slot = host->slot[i];
1990 if (slot && (status & slot->sdio_irq)) {
1991 mmc_signal_sdio_irq(slot->mmc);
1992 }
1993 }
1994 }
1995
1996
1997 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1998 {
1999 struct atmel_mci *host = dev_id;
2000 u32 status, mask, pending;
2001 unsigned int pass_count = 0;
2002
2003 do {
2004 status = atmci_readl(host, ATMCI_SR);
2005 mask = atmci_readl(host, ATMCI_IMR);
2006 pending = status & mask;
2007 if (!pending)
2008 break;
2009
2010 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2011 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2012 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2013 | ATMCI_RXRDY | ATMCI_TXRDY
2014 | ATMCI_ENDRX | ATMCI_ENDTX
2015 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2016
2017 host->data_status = status;
2018 dev_dbg(&host->pdev->dev, "set pending data error\n");
2019 smp_wmb();
2020 atmci_set_pending(host, EVENT_DATA_ERROR);
2021 tasklet_schedule(&host->tasklet);
2022 }
2023
2024 if (pending & ATMCI_TXBUFE) {
2025 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2026 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2027 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2028 /*
2029 * We can receive this interruption before having configured
2030 * the second pdc buffer, so we need to reconfigure first and
2031 * second buffers again
2032 */
2033 if (host->data_size) {
2034 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2035 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2036 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2037 } else {
2038 atmci_pdc_complete(host);
2039 }
2040 } else if (pending & ATMCI_ENDTX) {
2041 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2042 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2043
2044 if (host->data_size) {
2045 atmci_pdc_set_single_buf(host,
2046 XFER_TRANSMIT, PDC_SECOND_BUF);
2047 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2048 }
2049 }
2050
2051 if (pending & ATMCI_RXBUFF) {
2052 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2053 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2054 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2055 /*
2056 * We can receive this interruption before having configured
2057 * the second pdc buffer, so we need to reconfigure first and
2058 * second buffers again
2059 */
2060 if (host->data_size) {
2061 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2062 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2063 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2064 } else {
2065 atmci_pdc_complete(host);
2066 }
2067 } else if (pending & ATMCI_ENDRX) {
2068 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2069 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2070
2071 if (host->data_size) {
2072 atmci_pdc_set_single_buf(host,
2073 XFER_RECEIVE, PDC_SECOND_BUF);
2074 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2075 }
2076 }
2077
2078 /*
2079 * First mci IPs, so mainly the ones having pdc, have some
2080 * issues with the notbusy signal. You can't get it after
2081 * data transmission if you have not sent a stop command.
2082 * The appropriate workaround is to use the BLKE signal.
2083 */
2084 if (pending & ATMCI_BLKE) {
2085 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2086 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2087 smp_wmb();
2088 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2089 atmci_set_pending(host, EVENT_NOTBUSY);
2090 tasklet_schedule(&host->tasklet);
2091 }
2092
2093 if (pending & ATMCI_NOTBUSY) {
2094 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2095 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2096 smp_wmb();
2097 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2098 atmci_set_pending(host, EVENT_NOTBUSY);
2099 tasklet_schedule(&host->tasklet);
2100 }
2101
2102 if (pending & ATMCI_RXRDY)
2103 atmci_read_data_pio(host);
2104 if (pending & ATMCI_TXRDY)
2105 atmci_write_data_pio(host);
2106
2107 if (pending & ATMCI_CMDRDY) {
2108 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2109 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2110 host->cmd_status = status;
2111 smp_wmb();
2112 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2113 atmci_set_pending(host, EVENT_CMD_RDY);
2114 tasklet_schedule(&host->tasklet);
2115 }
2116
2117 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2118 atmci_sdio_interrupt(host, status);
2119
2120 } while (pass_count++ < 5);
2121
2122 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2123 }
2124
2125 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2126 {
2127 struct atmel_mci_slot *slot = dev_id;
2128
2129 /*
2130 * Disable interrupts until the pin has stabilized and check
2131 * the state then. Use mod_timer() since we may be in the
2132 * middle of the timer routine when this interrupt triggers.
2133 */
2134 disable_irq_nosync(irq);
2135 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2136
2137 return IRQ_HANDLED;
2138 }
2139
2140 static int __init atmci_init_slot(struct atmel_mci *host,
2141 struct mci_slot_pdata *slot_data, unsigned int id,
2142 u32 sdc_reg, u32 sdio_irq)
2143 {
2144 struct mmc_host *mmc;
2145 struct atmel_mci_slot *slot;
2146
2147 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2148 if (!mmc)
2149 return -ENOMEM;
2150
2151 slot = mmc_priv(mmc);
2152 slot->mmc = mmc;
2153 slot->host = host;
2154 slot->detect_pin = slot_data->detect_pin;
2155 slot->wp_pin = slot_data->wp_pin;
2156 slot->detect_is_active_high = slot_data->detect_is_active_high;
2157 slot->sdc_reg = sdc_reg;
2158 slot->sdio_irq = sdio_irq;
2159
2160 dev_dbg(&mmc->class_dev,
2161 "slot[%u]: bus_width=%u, detect_pin=%d, "
2162 "detect_is_active_high=%s, wp_pin=%d\n",
2163 id, slot_data->bus_width, slot_data->detect_pin,
2164 slot_data->detect_is_active_high ? "true" : "false",
2165 slot_data->wp_pin);
2166
2167 mmc->ops = &atmci_ops;
2168 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2169 mmc->f_max = host->bus_hz / 2;
2170 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2171 if (sdio_irq)
2172 mmc->caps |= MMC_CAP_SDIO_IRQ;
2173 if (host->caps.has_highspeed)
2174 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2175 /*
2176 * Without the read/write proof capability, it is strongly suggested to
2177 * use only one bit for data to prevent fifo underruns and overruns
2178 * which will corrupt data.
2179 */
2180 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2181 mmc->caps |= MMC_CAP_4_BIT_DATA;
2182
2183 if (atmci_get_version(host) < 0x200) {
2184 mmc->max_segs = 256;
2185 mmc->max_blk_size = 4095;
2186 mmc->max_blk_count = 256;
2187 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2188 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2189 } else {
2190 mmc->max_segs = 64;
2191 mmc->max_req_size = 32768 * 512;
2192 mmc->max_blk_size = 32768;
2193 mmc->max_blk_count = 512;
2194 }
2195
2196 /* Assume card is present initially */
2197 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2198 if (gpio_is_valid(slot->detect_pin)) {
2199 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2200 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2201 slot->detect_pin = -EBUSY;
2202 } else if (gpio_get_value(slot->detect_pin) ^
2203 slot->detect_is_active_high) {
2204 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2205 }
2206 }
2207
2208 if (!gpio_is_valid(slot->detect_pin))
2209 mmc->caps |= MMC_CAP_NEEDS_POLL;
2210
2211 if (gpio_is_valid(slot->wp_pin)) {
2212 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2213 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2214 slot->wp_pin = -EBUSY;
2215 }
2216 }
2217
2218 host->slot[id] = slot;
2219 mmc_add_host(mmc);
2220
2221 if (gpio_is_valid(slot->detect_pin)) {
2222 int ret;
2223
2224 setup_timer(&slot->detect_timer, atmci_detect_change,
2225 (unsigned long)slot);
2226
2227 ret = request_irq(gpio_to_irq(slot->detect_pin),
2228 atmci_detect_interrupt,
2229 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2230 "mmc-detect", slot);
2231 if (ret) {
2232 dev_dbg(&mmc->class_dev,
2233 "could not request IRQ %d for detect pin\n",
2234 gpio_to_irq(slot->detect_pin));
2235 gpio_free(slot->detect_pin);
2236 slot->detect_pin = -EBUSY;
2237 }
2238 }
2239
2240 atmci_init_debugfs(slot);
2241
2242 return 0;
2243 }
2244
2245 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2246 unsigned int id)
2247 {
2248 /* Debugfs stuff is cleaned up by mmc core */
2249
2250 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2251 smp_wmb();
2252
2253 mmc_remove_host(slot->mmc);
2254
2255 if (gpio_is_valid(slot->detect_pin)) {
2256 int pin = slot->detect_pin;
2257
2258 free_irq(gpio_to_irq(pin), slot);
2259 del_timer_sync(&slot->detect_timer);
2260 gpio_free(pin);
2261 }
2262 if (gpio_is_valid(slot->wp_pin))
2263 gpio_free(slot->wp_pin);
2264
2265 slot->host->slot[id] = NULL;
2266 mmc_free_host(slot->mmc);
2267 }
2268
2269 static bool atmci_filter(struct dma_chan *chan, void *pdata)
2270 {
2271 struct mci_platform_data *sl_pdata = pdata;
2272 struct mci_dma_data *sl;
2273
2274 if (!sl_pdata)
2275 return false;
2276
2277 sl = sl_pdata->dma_slave;
2278 if (sl && find_slave_dev(sl) == chan->device->dev) {
2279 chan->private = slave_data_ptr(sl);
2280 return true;
2281 } else {
2282 return false;
2283 }
2284 }
2285
2286 static bool atmci_configure_dma(struct atmel_mci *host)
2287 {
2288 struct mci_platform_data *pdata;
2289 dma_cap_mask_t mask;
2290
2291 if (host == NULL)
2292 return false;
2293
2294 pdata = host->pdev->dev.platform_data;
2295
2296 dma_cap_zero(mask);
2297 dma_cap_set(DMA_SLAVE, mask);
2298
2299 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
2300 &host->pdev->dev, "rxtx");
2301 if (!host->dma.chan) {
2302 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2303 return false;
2304 } else {
2305 dev_info(&host->pdev->dev,
2306 "using %s for DMA transfers\n",
2307 dma_chan_name(host->dma.chan));
2308
2309 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2310 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2311 host->dma_conf.src_maxburst = 1;
2312 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2313 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2314 host->dma_conf.dst_maxburst = 1;
2315 host->dma_conf.device_fc = false;
2316 return true;
2317 }
2318 }
2319
2320 /*
2321 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2322 * HSMCI provides DMA support and a new config register but no more supports
2323 * PDC.
2324 */
2325 static void __init atmci_get_cap(struct atmel_mci *host)
2326 {
2327 unsigned int version;
2328
2329 version = atmci_get_version(host);
2330 dev_info(&host->pdev->dev,
2331 "version: 0x%x\n", version);
2332
2333 host->caps.has_dma_conf_reg = 0;
2334 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2335 host->caps.has_cfg_reg = 0;
2336 host->caps.has_cstor_reg = 0;
2337 host->caps.has_highspeed = 0;
2338 host->caps.has_rwproof = 0;
2339 host->caps.has_odd_clk_div = 0;
2340 host->caps.has_bad_data_ordering = 1;
2341 host->caps.need_reset_after_xfer = 1;
2342 host->caps.need_blksz_mul_4 = 1;
2343 host->caps.need_notbusy_for_read_ops = 0;
2344
2345 /* keep only major version number */
2346 switch (version & 0xf00) {
2347 case 0x500:
2348 host->caps.has_odd_clk_div = 1;
2349 case 0x400:
2350 case 0x300:
2351 host->caps.has_dma_conf_reg = 1;
2352 host->caps.has_pdc = 0;
2353 host->caps.has_cfg_reg = 1;
2354 host->caps.has_cstor_reg = 1;
2355 host->caps.has_highspeed = 1;
2356 case 0x200:
2357 host->caps.has_rwproof = 1;
2358 host->caps.need_blksz_mul_4 = 0;
2359 host->caps.need_notbusy_for_read_ops = 1;
2360 case 0x100:
2361 host->caps.has_bad_data_ordering = 0;
2362 host->caps.need_reset_after_xfer = 0;
2363 case 0x0:
2364 break;
2365 default:
2366 host->caps.has_pdc = 0;
2367 dev_warn(&host->pdev->dev,
2368 "Unmanaged mci version, set minimum capabilities\n");
2369 break;
2370 }
2371 }
2372
2373 static int __init atmci_probe(struct platform_device *pdev)
2374 {
2375 struct mci_platform_data *pdata;
2376 struct atmel_mci *host;
2377 struct resource *regs;
2378 unsigned int nr_slots;
2379 int irq;
2380 int ret;
2381
2382 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2383 if (!regs)
2384 return -ENXIO;
2385 pdata = pdev->dev.platform_data;
2386 if (!pdata) {
2387 pdata = atmci_of_init(pdev);
2388 if (IS_ERR(pdata)) {
2389 dev_err(&pdev->dev, "platform data not available\n");
2390 return PTR_ERR(pdata);
2391 }
2392 }
2393
2394 irq = platform_get_irq(pdev, 0);
2395 if (irq < 0)
2396 return irq;
2397
2398 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2399 if (!host)
2400 return -ENOMEM;
2401
2402 host->pdev = pdev;
2403 spin_lock_init(&host->lock);
2404 INIT_LIST_HEAD(&host->queue);
2405
2406 host->mck = clk_get(&pdev->dev, "mci_clk");
2407 if (IS_ERR(host->mck)) {
2408 ret = PTR_ERR(host->mck);
2409 goto err_clk_get;
2410 }
2411
2412 ret = -ENOMEM;
2413 host->regs = ioremap(regs->start, resource_size(regs));
2414 if (!host->regs)
2415 goto err_ioremap;
2416
2417 ret = clk_prepare_enable(host->mck);
2418 if (ret)
2419 goto err_request_irq;
2420 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2421 host->bus_hz = clk_get_rate(host->mck);
2422 clk_disable_unprepare(host->mck);
2423
2424 host->mapbase = regs->start;
2425
2426 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2427
2428 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2429 if (ret)
2430 goto err_request_irq;
2431
2432 /* Get MCI capabilities and set operations according to it */
2433 atmci_get_cap(host);
2434 if (atmci_configure_dma(host)) {
2435 host->prepare_data = &atmci_prepare_data_dma;
2436 host->submit_data = &atmci_submit_data_dma;
2437 host->stop_transfer = &atmci_stop_transfer_dma;
2438 } else if (host->caps.has_pdc) {
2439 dev_info(&pdev->dev, "using PDC\n");
2440 host->prepare_data = &atmci_prepare_data_pdc;
2441 host->submit_data = &atmci_submit_data_pdc;
2442 host->stop_transfer = &atmci_stop_transfer_pdc;
2443 } else {
2444 dev_info(&pdev->dev, "using PIO\n");
2445 host->prepare_data = &atmci_prepare_data;
2446 host->submit_data = &atmci_submit_data;
2447 host->stop_transfer = &atmci_stop_transfer;
2448 }
2449
2450 platform_set_drvdata(pdev, host);
2451
2452 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2453
2454 /* We need at least one slot to succeed */
2455 nr_slots = 0;
2456 ret = -ENODEV;
2457 if (pdata->slot[0].bus_width) {
2458 ret = atmci_init_slot(host, &pdata->slot[0],
2459 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2460 if (!ret) {
2461 nr_slots++;
2462 host->buf_size = host->slot[0]->mmc->max_req_size;
2463 }
2464 }
2465 if (pdata->slot[1].bus_width) {
2466 ret = atmci_init_slot(host, &pdata->slot[1],
2467 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2468 if (!ret) {
2469 nr_slots++;
2470 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2471 host->buf_size =
2472 host->slot[1]->mmc->max_req_size;
2473 }
2474 }
2475
2476 if (!nr_slots) {
2477 dev_err(&pdev->dev, "init failed: no slot defined\n");
2478 goto err_init_slot;
2479 }
2480
2481 if (!host->caps.has_rwproof) {
2482 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2483 &host->buf_phys_addr,
2484 GFP_KERNEL);
2485 if (!host->buffer) {
2486 ret = -ENOMEM;
2487 dev_err(&pdev->dev, "buffer allocation failed\n");
2488 goto err_init_slot;
2489 }
2490 }
2491
2492 dev_info(&pdev->dev,
2493 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2494 host->mapbase, irq, nr_slots);
2495
2496 return 0;
2497
2498 err_init_slot:
2499 if (host->dma.chan)
2500 dma_release_channel(host->dma.chan);
2501 free_irq(irq, host);
2502 err_request_irq:
2503 iounmap(host->regs);
2504 err_ioremap:
2505 clk_put(host->mck);
2506 err_clk_get:
2507 kfree(host);
2508 return ret;
2509 }
2510
2511 static int __exit atmci_remove(struct platform_device *pdev)
2512 {
2513 struct atmel_mci *host = platform_get_drvdata(pdev);
2514 unsigned int i;
2515
2516 if (host->buffer)
2517 dma_free_coherent(&pdev->dev, host->buf_size,
2518 host->buffer, host->buf_phys_addr);
2519
2520 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2521 if (host->slot[i])
2522 atmci_cleanup_slot(host->slot[i], i);
2523 }
2524
2525 clk_prepare_enable(host->mck);
2526 atmci_writel(host, ATMCI_IDR, ~0UL);
2527 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2528 atmci_readl(host, ATMCI_SR);
2529 clk_disable_unprepare(host->mck);
2530
2531 if (host->dma.chan)
2532 dma_release_channel(host->dma.chan);
2533
2534 free_irq(platform_get_irq(pdev, 0), host);
2535 iounmap(host->regs);
2536
2537 clk_put(host->mck);
2538 kfree(host);
2539
2540 return 0;
2541 }
2542
2543 #ifdef CONFIG_PM_SLEEP
2544 static int atmci_suspend(struct device *dev)
2545 {
2546 struct atmel_mci *host = dev_get_drvdata(dev);
2547 int i;
2548
2549 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2550 struct atmel_mci_slot *slot = host->slot[i];
2551 int ret;
2552
2553 if (!slot)
2554 continue;
2555 ret = mmc_suspend_host(slot->mmc);
2556 if (ret < 0) {
2557 while (--i >= 0) {
2558 slot = host->slot[i];
2559 if (slot
2560 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2561 mmc_resume_host(host->slot[i]->mmc);
2562 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2563 }
2564 }
2565 return ret;
2566 } else {
2567 set_bit(ATMCI_SUSPENDED, &slot->flags);
2568 }
2569 }
2570
2571 return 0;
2572 }
2573
2574 static int atmci_resume(struct device *dev)
2575 {
2576 struct atmel_mci *host = dev_get_drvdata(dev);
2577 int i;
2578 int ret = 0;
2579
2580 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2581 struct atmel_mci_slot *slot = host->slot[i];
2582 int err;
2583
2584 slot = host->slot[i];
2585 if (!slot)
2586 continue;
2587 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2588 continue;
2589 err = mmc_resume_host(slot->mmc);
2590 if (err < 0)
2591 ret = err;
2592 else
2593 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2594 }
2595
2596 return ret;
2597 }
2598 #endif
2599
2600 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2601
2602 static struct platform_driver atmci_driver = {
2603 .remove = __exit_p(atmci_remove),
2604 .driver = {
2605 .name = "atmel_mci",
2606 .pm = &atmci_pm,
2607 .of_match_table = of_match_ptr(atmci_dt_ids),
2608 },
2609 };
2610
2611 static int __init atmci_init(void)
2612 {
2613 return platform_driver_probe(&atmci_driver, atmci_probe);
2614 }
2615
2616 static void __exit atmci_exit(void)
2617 {
2618 platform_driver_unregister(&atmci_driver);
2619 }
2620
2621 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2622 module_exit(atmci_exit);
2623
2624 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2625 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2626 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support