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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / mmc / host / omap_hsmmc.c
blob6ac63df645c405b0bd6586c7f8d993d940f8c1af
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
31 #include <linux/of.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_device.h>
34 #include <linux/omap-dma.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/core.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/io.h>
39 #include <linux/gpio.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/platform_data/mmc-omap.h>
44
45 /* OMAP HSMMC Host Controller Registers */
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_BLK 0x0104
49 #define OMAP_HSMMC_ARG 0x0108
50 #define OMAP_HSMMC_CMD 0x010C
51 #define OMAP_HSMMC_RSP10 0x0110
52 #define OMAP_HSMMC_RSP32 0x0114
53 #define OMAP_HSMMC_RSP54 0x0118
54 #define OMAP_HSMMC_RSP76 0x011C
55 #define OMAP_HSMMC_DATA 0x0120
56 #define OMAP_HSMMC_HCTL 0x0128
57 #define OMAP_HSMMC_SYSCTL 0x012C
58 #define OMAP_HSMMC_STAT 0x0130
59 #define OMAP_HSMMC_IE 0x0134
60 #define OMAP_HSMMC_ISE 0x0138
61 #define OMAP_HSMMC_CAPA 0x0140
62
63 #define VS18 (1 << 26)
64 #define VS30 (1 << 25)
65 #define HSS (1 << 21)
66 #define SDVS18 (0x5 << 9)
67 #define SDVS30 (0x6 << 9)
68 #define SDVS33 (0x7 << 9)
69 #define SDVS_MASK 0x00000E00
70 #define SDVSCLR 0xFFFFF1FF
71 #define SDVSDET 0x00000400
72 #define AUTOIDLE 0x1
73 #define SDBP (1 << 8)
74 #define DTO 0xe
75 #define ICE 0x1
76 #define ICS 0x2
77 #define CEN (1 << 2)
78 #define CLKD_MASK 0x0000FFC0
79 #define CLKD_SHIFT 6
80 #define DTO_MASK 0x000F0000
81 #define DTO_SHIFT 16
82 #define INIT_STREAM (1 << 1)
83 #define DP_SELECT (1 << 21)
84 #define DDIR (1 << 4)
85 #define DMAE 0x1
86 #define MSBS (1 << 5)
87 #define BCE (1 << 1)
88 #define FOUR_BIT (1 << 1)
89 #define HSPE (1 << 2)
90 #define DDR (1 << 19)
91 #define DW8 (1 << 5)
92 #define OD 0x1
93 #define STAT_CLEAR 0xFFFFFFFF
94 #define INIT_STREAM_CMD 0x00000000
95 #define DUAL_VOLT_OCR_BIT 7
96 #define SRC (1 << 25)
97 #define SRD (1 << 26)
98 #define SOFTRESET (1 << 1)
99 #define RESETDONE (1 << 0)
100
101 /* Interrupt masks for IE and ISE register */
102 #define CC_EN (1 << 0)
103 #define TC_EN (1 << 1)
104 #define BWR_EN (1 << 4)
105 #define BRR_EN (1 << 5)
106 #define ERR_EN (1 << 15)
107 #define CTO_EN (1 << 16)
108 #define CCRC_EN (1 << 17)
109 #define CEB_EN (1 << 18)
110 #define CIE_EN (1 << 19)
111 #define DTO_EN (1 << 20)
112 #define DCRC_EN (1 << 21)
113 #define DEB_EN (1 << 22)
114 #define CERR_EN (1 << 28)
115 #define BADA_EN (1 << 29)
116
117 #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
118 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
119 BRR_EN | BWR_EN | TC_EN | CC_EN)
120
121 #define MMC_AUTOSUSPEND_DELAY 100
122 #define MMC_TIMEOUT_MS 20
123 #define OMAP_MMC_MIN_CLOCK 400000
124 #define OMAP_MMC_MAX_CLOCK 52000000
125 #define DRIVER_NAME "omap_hsmmc"
126
127 /*
128 * One controller can have multiple slots, like on some omap boards using
129 * omap.c controller driver. Luckily this is not currently done on any known
130 * omap_hsmmc.c device.
131 */
132 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
133
134 /*
135 * MMC Host controller read/write API's
136 */
137 #define OMAP_HSMMC_READ(base, reg) \
138 __raw_readl((base) + OMAP_HSMMC_##reg)
139
140 #define OMAP_HSMMC_WRITE(base, reg, val) \
141 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142
143 struct omap_hsmmc_next {
144 unsigned int dma_len;
145 s32 cookie;
146 };
147
148 struct omap_hsmmc_host {
149 struct device *dev;
150 struct mmc_host *mmc;
151 struct mmc_request *mrq;
152 struct mmc_command *cmd;
153 struct mmc_data *data;
154 struct clk *fclk;
155 struct clk *dbclk;
156 /*
157 * vcc == configured supply
158 * vcc_aux == optional
159 * - MMC1, supply for DAT4..DAT7
160 * - MMC2/MMC2, external level shifter voltage supply, for
161 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
162 */
163 struct regulator *vcc;
164 struct regulator *vcc_aux;
165 int pbias_disable;
166 void __iomem *base;
167 resource_size_t mapbase;
168 spinlock_t irq_lock; /* Prevent races with irq handler */
169 unsigned int dma_len;
170 unsigned int dma_sg_idx;
171 unsigned char bus_mode;
172 unsigned char power_mode;
173 int suspended;
174 int irq;
175 int use_dma, dma_ch;
176 struct dma_chan *tx_chan;
177 struct dma_chan *rx_chan;
178 int slot_id;
179 int response_busy;
180 int context_loss;
181 int protect_card;
182 int reqs_blocked;
183 int use_reg;
184 int req_in_progress;
185 struct omap_hsmmc_next next_data;
186
187 struct omap_mmc_platform_data *pdata;
188 };
189
190 static int omap_hsmmc_card_detect(struct device *dev, int slot)
191 {
192 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
193 struct omap_mmc_platform_data *mmc = host->pdata;
194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197 }
198
199 static int omap_hsmmc_get_wp(struct device *dev, int slot)
200 {
201 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
202 struct omap_mmc_platform_data *mmc = host->pdata;
203
204 /* NOTE: assumes write protect signal is active-high */
205 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
206 }
207
208 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
209 {
210 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
211 struct omap_mmc_platform_data *mmc = host->pdata;
212
213 /* NOTE: assumes card detect signal is active-low */
214 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
215 }
216
217 #ifdef CONFIG_PM
218
219 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
220 {
221 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
222 struct omap_mmc_platform_data *mmc = host->pdata;
223
224 disable_irq(mmc->slots[0].card_detect_irq);
225 return 0;
226 }
227
228 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
229 {
230 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
231 struct omap_mmc_platform_data *mmc = host->pdata;
232
233 enable_irq(mmc->slots[0].card_detect_irq);
234 return 0;
235 }
236
237 #else
238
239 #define omap_hsmmc_suspend_cdirq NULL
240 #define omap_hsmmc_resume_cdirq NULL
241
242 #endif
243
244 #ifdef CONFIG_REGULATOR
245
246 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
247 int vdd)
248 {
249 struct omap_hsmmc_host *host =
250 platform_get_drvdata(to_platform_device(dev));
251 int ret = 0;
252
253 /*
254 * If we don't see a Vcc regulator, assume it's a fixed
255 * voltage always-on regulator.
256 */
257 if (!host->vcc)
258 return 0;
259 /*
260 * With DT, never turn OFF the regulator for MMC1. This is because
261 * the pbias cell programming support is still missing when
262 * booting with Device tree
263 */
264 if (host->pbias_disable && !vdd)
265 return 0;
266
267 if (mmc_slot(host).before_set_reg)
268 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
269
270 /*
271 * Assume Vcc regulator is used only to power the card ... OMAP
272 * VDDS is used to power the pins, optionally with a transceiver to
273 * support cards using voltages other than VDDS (1.8V nominal). When a
274 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
275 *
276 * In some cases this regulator won't support enable/disable;
277 * e.g. it's a fixed rail for a WLAN chip.
278 *
279 * In other cases vcc_aux switches interface power. Example, for
280 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
281 * chips/cards need an interface voltage rail too.
282 */
283 if (power_on) {
284 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
285 /* Enable interface voltage rail, if needed */
286 if (ret == 0 && host->vcc_aux) {
287 ret = regulator_enable(host->vcc_aux);
288 if (ret < 0)
289 ret = mmc_regulator_set_ocr(host->mmc,
290 host->vcc, 0);
291 }
292 } else {
293 /* Shut down the rail */
294 if (host->vcc_aux)
295 ret = regulator_disable(host->vcc_aux);
296 if (!ret) {
297 /* Then proceed to shut down the local regulator */
298 ret = mmc_regulator_set_ocr(host->mmc,
299 host->vcc, 0);
300 }
301 }
302
303 if (mmc_slot(host).after_set_reg)
304 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
305
306 return ret;
307 }
308
309 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
310 {
311 struct regulator *reg;
312 int ocr_value = 0;
313
314 reg = regulator_get(host->dev, "vmmc");
315 if (IS_ERR(reg)) {
316 dev_err(host->dev, "vmmc regulator missing\n");
317 return PTR_ERR(reg);
318 } else {
319 mmc_slot(host).set_power = omap_hsmmc_set_power;
320 host->vcc = reg;
321 ocr_value = mmc_regulator_get_ocrmask(reg);
322 if (!mmc_slot(host).ocr_mask) {
323 mmc_slot(host).ocr_mask = ocr_value;
324 } else {
325 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
326 dev_err(host->dev, "ocrmask %x is not supported\n",
327 mmc_slot(host).ocr_mask);
328 mmc_slot(host).ocr_mask = 0;
329 return -EINVAL;
330 }
331 }
332
333 /* Allow an aux regulator */
334 reg = regulator_get(host->dev, "vmmc_aux");
335 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
336
337 /* For eMMC do not power off when not in sleep state */
338 if (mmc_slot(host).no_regulator_off_init)
339 return 0;
340 /*
341 * UGLY HACK: workaround regulator framework bugs.
342 * When the bootloader leaves a supply active, it's
343 * initialized with zero usecount ... and we can't
344 * disable it without first enabling it. Until the
345 * framework is fixed, we need a workaround like this
346 * (which is safe for MMC, but not in general).
347 */
348 if (regulator_is_enabled(host->vcc) > 0 ||
349 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
350 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
351
352 mmc_slot(host).set_power(host->dev, host->slot_id,
353 1, vdd);
354 mmc_slot(host).set_power(host->dev, host->slot_id,
355 0, 0);
356 }
357 }
358
359 return 0;
360 }
361
362 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
363 {
364 regulator_put(host->vcc);
365 regulator_put(host->vcc_aux);
366 mmc_slot(host).set_power = NULL;
367 }
368
369 static inline int omap_hsmmc_have_reg(void)
370 {
371 return 1;
372 }
373
374 #else
375
376 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
377 {
378 return -EINVAL;
379 }
380
381 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
382 {
383 }
384
385 static inline int omap_hsmmc_have_reg(void)
386 {
387 return 0;
388 }
389
390 #endif
391
392 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
393 {
394 int ret;
395
396 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
397 if (pdata->slots[0].cover)
398 pdata->slots[0].get_cover_state =
399 omap_hsmmc_get_cover_state;
400 else
401 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
402 pdata->slots[0].card_detect_irq =
403 gpio_to_irq(pdata->slots[0].switch_pin);
404 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
405 if (ret)
406 return ret;
407 ret = gpio_direction_input(pdata->slots[0].switch_pin);
408 if (ret)
409 goto err_free_sp;
410 } else
411 pdata->slots[0].switch_pin = -EINVAL;
412
413 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
414 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
415 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
416 if (ret)
417 goto err_free_cd;
418 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
419 if (ret)
420 goto err_free_wp;
421 } else
422 pdata->slots[0].gpio_wp = -EINVAL;
423
424 return 0;
425
426 err_free_wp:
427 gpio_free(pdata->slots[0].gpio_wp);
428 err_free_cd:
429 if (gpio_is_valid(pdata->slots[0].switch_pin))
430 err_free_sp:
431 gpio_free(pdata->slots[0].switch_pin);
432 return ret;
433 }
434
435 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
436 {
437 if (gpio_is_valid(pdata->slots[0].gpio_wp))
438 gpio_free(pdata->slots[0].gpio_wp);
439 if (gpio_is_valid(pdata->slots[0].switch_pin))
440 gpio_free(pdata->slots[0].switch_pin);
441 }
442
443 /*
444 * Start clock to the card
445 */
446 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
447 {
448 OMAP_HSMMC_WRITE(host->base, SYSCTL,
449 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
450 }
451
452 /*
453 * Stop clock to the card
454 */
455 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
456 {
457 OMAP_HSMMC_WRITE(host->base, SYSCTL,
458 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
459 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
460 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
461 }
462
463 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
464 struct mmc_command *cmd)
465 {
466 unsigned int irq_mask;
467
468 if (host->use_dma)
469 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
470 else
471 irq_mask = INT_EN_MASK;
472
473 /* Disable timeout for erases */
474 if (cmd->opcode == MMC_ERASE)
475 irq_mask &= ~DTO_EN;
476
477 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
478 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
479 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
480 }
481
482 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
483 {
484 OMAP_HSMMC_WRITE(host->base, ISE, 0);
485 OMAP_HSMMC_WRITE(host->base, IE, 0);
486 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
487 }
488
489 /* Calculate divisor for the given clock frequency */
490 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
491 {
492 u16 dsor = 0;
493
494 if (ios->clock) {
495 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
496 if (dsor > 250)
497 dsor = 250;
498 }
499
500 return dsor;
501 }
502
503 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
504 {
505 struct mmc_ios *ios = &host->mmc->ios;
506 unsigned long regval;
507 unsigned long timeout;
508 unsigned long clkdiv;
509
510 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
511
512 omap_hsmmc_stop_clock(host);
513
514 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
515 regval = regval & ~(CLKD_MASK | DTO_MASK);
516 clkdiv = calc_divisor(host, ios);
517 regval = regval | (clkdiv << 6) | (DTO << 16);
518 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
519 OMAP_HSMMC_WRITE(host->base, SYSCTL,
520 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
521
522 /* Wait till the ICS bit is set */
523 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
524 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
525 && time_before(jiffies, timeout))
526 cpu_relax();
527
528 /*
529 * Enable High-Speed Support
530 * Pre-Requisites
531 * - Controller should support High-Speed-Enable Bit
532 * - Controller should not be using DDR Mode
533 * - Controller should advertise that it supports High Speed
534 * in capabilities register
535 * - MMC/SD clock coming out of controller > 25MHz
536 */
537 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
538 (ios->timing != MMC_TIMING_UHS_DDR50) &&
539 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
540 regval = OMAP_HSMMC_READ(host->base, HCTL);
541 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
542 regval |= HSPE;
543 else
544 regval &= ~HSPE;
545
546 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
547 }
548
549 omap_hsmmc_start_clock(host);
550 }
551
552 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
553 {
554 struct mmc_ios *ios = &host->mmc->ios;
555 u32 con;
556
557 con = OMAP_HSMMC_READ(host->base, CON);
558 if (ios->timing == MMC_TIMING_UHS_DDR50)
559 con |= DDR; /* configure in DDR mode */
560 else
561 con &= ~DDR;
562 switch (ios->bus_width) {
563 case MMC_BUS_WIDTH_8:
564 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
565 break;
566 case MMC_BUS_WIDTH_4:
567 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
568 OMAP_HSMMC_WRITE(host->base, HCTL,
569 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
570 break;
571 case MMC_BUS_WIDTH_1:
572 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
573 OMAP_HSMMC_WRITE(host->base, HCTL,
574 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
575 break;
576 }
577 }
578
579 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
580 {
581 struct mmc_ios *ios = &host->mmc->ios;
582 u32 con;
583
584 con = OMAP_HSMMC_READ(host->base, CON);
585 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
586 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
587 else
588 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
589 }
590
591 #ifdef CONFIG_PM
592
593 /*
594 * Restore the MMC host context, if it was lost as result of a
595 * power state change.
596 */
597 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
598 {
599 struct mmc_ios *ios = &host->mmc->ios;
600 struct omap_mmc_platform_data *pdata = host->pdata;
601 int context_loss = 0;
602 u32 hctl, capa;
603 unsigned long timeout;
604
605 if (pdata->get_context_loss_count) {
606 context_loss = pdata->get_context_loss_count(host->dev);
607 if (context_loss < 0)
608 return 1;
609 }
610
611 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
612 context_loss == host->context_loss ? "not " : "");
613 if (host->context_loss == context_loss)
614 return 1;
615
616 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
617 return 1;
618
619 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
620 if (host->power_mode != MMC_POWER_OFF &&
621 (1 << ios->vdd) <= MMC_VDD_23_24)
622 hctl = SDVS18;
623 else
624 hctl = SDVS30;
625 capa = VS30 | VS18;
626 } else {
627 hctl = SDVS18;
628 capa = VS18;
629 }
630
631 OMAP_HSMMC_WRITE(host->base, HCTL,
632 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
633
634 OMAP_HSMMC_WRITE(host->base, CAPA,
635 OMAP_HSMMC_READ(host->base, CAPA) | capa);
636
637 OMAP_HSMMC_WRITE(host->base, HCTL,
638 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
639
640 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
641 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
642 && time_before(jiffies, timeout))
643 ;
644
645 omap_hsmmc_disable_irq(host);
646
647 /* Do not initialize card-specific things if the power is off */
648 if (host->power_mode == MMC_POWER_OFF)
649 goto out;
650
651 omap_hsmmc_set_bus_width(host);
652
653 omap_hsmmc_set_clock(host);
654
655 omap_hsmmc_set_bus_mode(host);
656
657 out:
658 host->context_loss = context_loss;
659
660 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
661 return 0;
662 }
663
664 /*
665 * Save the MMC host context (store the number of power state changes so far).
666 */
667 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
668 {
669 struct omap_mmc_platform_data *pdata = host->pdata;
670 int context_loss;
671
672 if (pdata->get_context_loss_count) {
673 context_loss = pdata->get_context_loss_count(host->dev);
674 if (context_loss < 0)
675 return;
676 host->context_loss = context_loss;
677 }
678 }
679
680 #else
681
682 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
683 {
684 return 0;
685 }
686
687 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
688 {
689 }
690
691 #endif
692
693 /*
694 * Send init stream sequence to card
695 * before sending IDLE command
696 */
697 static void send_init_stream(struct omap_hsmmc_host *host)
698 {
699 int reg = 0;
700 unsigned long timeout;
701
702 if (host->protect_card)
703 return;
704
705 disable_irq(host->irq);
706
707 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
708 OMAP_HSMMC_WRITE(host->base, CON,
709 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
710 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
711
712 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
713 while ((reg != CC_EN) && time_before(jiffies, timeout))
714 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
715
716 OMAP_HSMMC_WRITE(host->base, CON,
717 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
718
719 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
720 OMAP_HSMMC_READ(host->base, STAT);
721
722 enable_irq(host->irq);
723 }
724
725 static inline
726 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
727 {
728 int r = 1;
729
730 if (mmc_slot(host).get_cover_state)
731 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
732 return r;
733 }
734
735 static ssize_t
736 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
737 char *buf)
738 {
739 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
740 struct omap_hsmmc_host *host = mmc_priv(mmc);
741
742 return sprintf(buf, "%s\n",
743 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
744 }
745
746 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
747
748 static ssize_t
749 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
750 char *buf)
751 {
752 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
753 struct omap_hsmmc_host *host = mmc_priv(mmc);
754
755 return sprintf(buf, "%s\n", mmc_slot(host).name);
756 }
757
758 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
759
760 /*
761 * Configure the response type and send the cmd.
762 */
763 static void
764 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
765 struct mmc_data *data)
766 {
767 int cmdreg = 0, resptype = 0, cmdtype = 0;
768
769 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
770 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
771 host->cmd = cmd;
772
773 omap_hsmmc_enable_irq(host, cmd);
774
775 host->response_busy = 0;
776 if (cmd->flags & MMC_RSP_PRESENT) {
777 if (cmd->flags & MMC_RSP_136)
778 resptype = 1;
779 else if (cmd->flags & MMC_RSP_BUSY) {
780 resptype = 3;
781 host->response_busy = 1;
782 } else
783 resptype = 2;
784 }
785
786 /*
787 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
788 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
789 * a val of 0x3, rest 0x0.
790 */
791 if (cmd == host->mrq->stop)
792 cmdtype = 0x3;
793
794 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
795
796 if (data) {
797 cmdreg |= DP_SELECT | MSBS | BCE;
798 if (data->flags & MMC_DATA_READ)
799 cmdreg |= DDIR;
800 else
801 cmdreg &= ~(DDIR);
802 }
803
804 if (host->use_dma)
805 cmdreg |= DMAE;
806
807 host->req_in_progress = 1;
808
809 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
810 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
811 }
812
813 static int
814 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
815 {
816 if (data->flags & MMC_DATA_WRITE)
817 return DMA_TO_DEVICE;
818 else
819 return DMA_FROM_DEVICE;
820 }
821
822 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
823 struct mmc_data *data)
824 {
825 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
826 }
827
828 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
829 {
830 int dma_ch;
831 unsigned long flags;
832
833 spin_lock_irqsave(&host->irq_lock, flags);
834 host->req_in_progress = 0;
835 dma_ch = host->dma_ch;
836 spin_unlock_irqrestore(&host->irq_lock, flags);
837
838 omap_hsmmc_disable_irq(host);
839 /* Do not complete the request if DMA is still in progress */
840 if (mrq->data && host->use_dma && dma_ch != -1)
841 return;
842 host->mrq = NULL;
843 mmc_request_done(host->mmc, mrq);
844 }
845
846 /*
847 * Notify the transfer complete to MMC core
848 */
849 static void
850 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
851 {
852 if (!data) {
853 struct mmc_request *mrq = host->mrq;
854
855 /* TC before CC from CMD6 - don't know why, but it happens */
856 if (host->cmd && host->cmd->opcode == 6 &&
857 host->response_busy) {
858 host->response_busy = 0;
859 return;
860 }
861
862 omap_hsmmc_request_done(host, mrq);
863 return;
864 }
865
866 host->data = NULL;
867
868 if (!data->error)
869 data->bytes_xfered += data->blocks * (data->blksz);
870 else
871 data->bytes_xfered = 0;
872
873 if (!data->stop) {
874 omap_hsmmc_request_done(host, data->mrq);
875 return;
876 }
877 omap_hsmmc_start_command(host, data->stop, NULL);
878 }
879
880 /*
881 * Notify the core about command completion
882 */
883 static void
884 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
885 {
886 host->cmd = NULL;
887
888 if (cmd->flags & MMC_RSP_PRESENT) {
889 if (cmd->flags & MMC_RSP_136) {
890 /* response type 2 */
891 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
892 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
893 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
894 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
895 } else {
896 /* response types 1, 1b, 3, 4, 5, 6 */
897 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
898 }
899 }
900 if ((host->data == NULL && !host->response_busy) || cmd->error)
901 omap_hsmmc_request_done(host, cmd->mrq);
902 }
903
904 /*
905 * DMA clean up for command errors
906 */
907 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
908 {
909 int dma_ch;
910 unsigned long flags;
911
912 host->data->error = errno;
913
914 spin_lock_irqsave(&host->irq_lock, flags);
915 dma_ch = host->dma_ch;
916 host->dma_ch = -1;
917 spin_unlock_irqrestore(&host->irq_lock, flags);
918
919 if (host->use_dma && dma_ch != -1) {
920 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
921
922 dmaengine_terminate_all(chan);
923 dma_unmap_sg(chan->device->dev,
924 host->data->sg, host->data->sg_len,
925 omap_hsmmc_get_dma_dir(host, host->data));
926
927 host->data->host_cookie = 0;
928 }
929 host->data = NULL;
930 }
931
932 /*
933 * Readable error output
934 */
935 #ifdef CONFIG_MMC_DEBUG
936 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
937 {
938 /* --- means reserved bit without definition at documentation */
939 static const char *omap_hsmmc_status_bits[] = {
940 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
941 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
942 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
943 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
944 };
945 char res[256];
946 char *buf = res;
947 int len, i;
948
949 len = sprintf(buf, "MMC IRQ 0x%x :", status);
950 buf += len;
951
952 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
953 if (status & (1 << i)) {
954 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
955 buf += len;
956 }
957
958 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
959 }
960 #else
961 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
962 u32 status)
963 {
964 }
965 #endif /* CONFIG_MMC_DEBUG */
966
967 /*
968 * MMC controller internal state machines reset
969 *
970 * Used to reset command or data internal state machines, using respectively
971 * SRC or SRD bit of SYSCTL register
972 * Can be called from interrupt context
973 */
974 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
975 unsigned long bit)
976 {
977 unsigned long i = 0;
978 unsigned long limit = (loops_per_jiffy *
979 msecs_to_jiffies(MMC_TIMEOUT_MS));
980
981 OMAP_HSMMC_WRITE(host->base, SYSCTL,
982 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
983
984 /*
985 * OMAP4 ES2 and greater has an updated reset logic.
986 * Monitor a 0->1 transition first
987 */
988 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
989 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
990 && (i++ < limit))
991 cpu_relax();
992 }
993 i = 0;
994
995 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
996 (i++ < limit))
997 cpu_relax();
998
999 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1000 dev_err(mmc_dev(host->mmc),
1001 "Timeout waiting on controller reset in %s\n",
1002 __func__);
1003 }
1004
1005 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1006 int err, int end_cmd)
1007 {
1008 if (end_cmd) {
1009 omap_hsmmc_reset_controller_fsm(host, SRC);
1010 if (host->cmd)
1011 host->cmd->error = err;
1012 }
1013
1014 if (host->data) {
1015 omap_hsmmc_reset_controller_fsm(host, SRD);
1016 omap_hsmmc_dma_cleanup(host, err);
1017 } else if (host->mrq && host->mrq->cmd)
1018 host->mrq->cmd->error = err;
1019 }
1020
1021 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1022 {
1023 struct mmc_data *data;
1024 int end_cmd = 0, end_trans = 0;
1025
1026 data = host->data;
1027 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1028
1029 if (status & ERR_EN) {
1030 omap_hsmmc_dbg_report_irq(host, status);
1031
1032 if (status & (CTO_EN | CCRC_EN))
1033 end_cmd = 1;
1034 if (status & (CTO_EN | DTO_EN))
1035 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1036 else if (status & (CCRC_EN | DCRC_EN))
1037 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1038
1039 if (host->data || host->response_busy) {
1040 end_trans = !end_cmd;
1041 host->response_busy = 0;
1042 }
1043 }
1044
1045 OMAP_HSMMC_WRITE(host->base, STAT, status);
1046 if (end_cmd || ((status & CC_EN) && host->cmd))
1047 omap_hsmmc_cmd_done(host, host->cmd);
1048 if ((end_trans || (status & TC_EN)) && host->mrq)
1049 omap_hsmmc_xfer_done(host, data);
1050 }
1051
1052 /*
1053 * MMC controller IRQ handler
1054 */
1055 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1056 {
1057 struct omap_hsmmc_host *host = dev_id;
1058 int status;
1059
1060 status = OMAP_HSMMC_READ(host->base, STAT);
1061 while (status & INT_EN_MASK && host->req_in_progress) {
1062 omap_hsmmc_do_irq(host, status);
1063
1064 /* Flush posted write */
1065 status = OMAP_HSMMC_READ(host->base, STAT);
1066 }
1067
1068 return IRQ_HANDLED;
1069 }
1070
1071 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1072 {
1073 unsigned long i;
1074
1075 OMAP_HSMMC_WRITE(host->base, HCTL,
1076 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1077 for (i = 0; i < loops_per_jiffy; i++) {
1078 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1079 break;
1080 cpu_relax();
1081 }
1082 }
1083
1084 /*
1085 * Switch MMC interface voltage ... only relevant for MMC1.
1086 *
1087 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1088 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1089 * Some chips, like eMMC ones, use internal transceivers.
1090 */
1091 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1092 {
1093 u32 reg_val = 0;
1094 int ret;
1095
1096 /* Disable the clocks */
1097 pm_runtime_put_sync(host->dev);
1098 if (host->dbclk)
1099 clk_disable_unprepare(host->dbclk);
1100
1101 /* Turn the power off */
1102 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1103
1104 /* Turn the power ON with given VDD 1.8 or 3.0v */
1105 if (!ret)
1106 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1107 vdd);
1108 pm_runtime_get_sync(host->dev);
1109 if (host->dbclk)
1110 clk_prepare_enable(host->dbclk);
1111
1112 if (ret != 0)
1113 goto err;
1114
1115 OMAP_HSMMC_WRITE(host->base, HCTL,
1116 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1117 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1118
1119 /*
1120 * If a MMC dual voltage card is detected, the set_ios fn calls
1121 * this fn with VDD bit set for 1.8V. Upon card removal from the
1122 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1123 *
1124 * Cope with a bit of slop in the range ... per data sheets:
1125 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1126 * but recommended values are 1.71V to 1.89V
1127 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1128 * but recommended values are 2.7V to 3.3V
1129 *
1130 * Board setup code shouldn't permit anything very out-of-range.
1131 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1132 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1133 */
1134 if ((1 << vdd) <= MMC_VDD_23_24)
1135 reg_val |= SDVS18;
1136 else
1137 reg_val |= SDVS30;
1138
1139 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1140 set_sd_bus_power(host);
1141
1142 return 0;
1143 err:
1144 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1145 return ret;
1146 }
1147
1148 /* Protect the card while the cover is open */
1149 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1150 {
1151 if (!mmc_slot(host).get_cover_state)
1152 return;
1153
1154 host->reqs_blocked = 0;
1155 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1156 if (host->protect_card) {
1157 dev_info(host->dev, "%s: cover is closed, "
1158 "card is now accessible\n",
1159 mmc_hostname(host->mmc));
1160 host->protect_card = 0;
1161 }
1162 } else {
1163 if (!host->protect_card) {
1164 dev_info(host->dev, "%s: cover is open, "
1165 "card is now inaccessible\n",
1166 mmc_hostname(host->mmc));
1167 host->protect_card = 1;
1168 }
1169 }
1170 }
1171
1172 /*
1173 * irq handler to notify the core about card insertion/removal
1174 */
1175 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1176 {
1177 struct omap_hsmmc_host *host = dev_id;
1178 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1179 int carddetect;
1180
1181 if (host->suspended)
1182 return IRQ_HANDLED;
1183
1184 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1185
1186 if (slot->card_detect)
1187 carddetect = slot->card_detect(host->dev, host->slot_id);
1188 else {
1189 omap_hsmmc_protect_card(host);
1190 carddetect = -ENOSYS;
1191 }
1192
1193 if (carddetect)
1194 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1195 else
1196 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1197 return IRQ_HANDLED;
1198 }
1199
1200 static void omap_hsmmc_dma_callback(void *param)
1201 {
1202 struct omap_hsmmc_host *host = param;
1203 struct dma_chan *chan;
1204 struct mmc_data *data;
1205 int req_in_progress;
1206
1207 spin_lock_irq(&host->irq_lock);
1208 if (host->dma_ch < 0) {
1209 spin_unlock_irq(&host->irq_lock);
1210 return;
1211 }
1212
1213 data = host->mrq->data;
1214 chan = omap_hsmmc_get_dma_chan(host, data);
1215 if (!data->host_cookie)
1216 dma_unmap_sg(chan->device->dev,
1217 data->sg, data->sg_len,
1218 omap_hsmmc_get_dma_dir(host, data));
1219
1220 req_in_progress = host->req_in_progress;
1221 host->dma_ch = -1;
1222 spin_unlock_irq(&host->irq_lock);
1223
1224 /* If DMA has finished after TC, complete the request */
1225 if (!req_in_progress) {
1226 struct mmc_request *mrq = host->mrq;
1227
1228 host->mrq = NULL;
1229 mmc_request_done(host->mmc, mrq);
1230 }
1231 }
1232
1233 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1234 struct mmc_data *data,
1235 struct omap_hsmmc_next *next,
1236 struct dma_chan *chan)
1237 {
1238 int dma_len;
1239
1240 if (!next && data->host_cookie &&
1241 data->host_cookie != host->next_data.cookie) {
1242 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1243 " host->next_data.cookie %d\n",
1244 __func__, data->host_cookie, host->next_data.cookie);
1245 data->host_cookie = 0;
1246 }
1247
1248 /* Check if next job is already prepared */
1249 if (next ||
1250 (!next && data->host_cookie != host->next_data.cookie)) {
1251 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1252 omap_hsmmc_get_dma_dir(host, data));
1253
1254 } else {
1255 dma_len = host->next_data.dma_len;
1256 host->next_data.dma_len = 0;
1257 }
1258
1259
1260 if (dma_len == 0)
1261 return -EINVAL;
1262
1263 if (next) {
1264 next->dma_len = dma_len;
1265 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1266 } else
1267 host->dma_len = dma_len;
1268
1269 return 0;
1270 }
1271
1272 /*
1273 * Routine to configure and start DMA for the MMC card
1274 */
1275 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1276 struct mmc_request *req)
1277 {
1278 struct dma_slave_config cfg;
1279 struct dma_async_tx_descriptor *tx;
1280 int ret = 0, i;
1281 struct mmc_data *data = req->data;
1282 struct dma_chan *chan;
1283
1284 /* Sanity check: all the SG entries must be aligned by block size. */
1285 for (i = 0; i < data->sg_len; i++) {
1286 struct scatterlist *sgl;
1287
1288 sgl = data->sg + i;
1289 if (sgl->length % data->blksz)
1290 return -EINVAL;
1291 }
1292 if ((data->blksz % 4) != 0)
1293 /* REVISIT: The MMC buffer increments only when MSB is written.
1294 * Return error for blksz which is non multiple of four.
1295 */
1296 return -EINVAL;
1297
1298 BUG_ON(host->dma_ch != -1);
1299
1300 chan = omap_hsmmc_get_dma_chan(host, data);
1301
1302 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1303 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1304 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1305 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1306 cfg.src_maxburst = data->blksz / 4;
1307 cfg.dst_maxburst = data->blksz / 4;
1308
1309 ret = dmaengine_slave_config(chan, &cfg);
1310 if (ret)
1311 return ret;
1312
1313 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1314 if (ret)
1315 return ret;
1316
1317 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1318 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1319 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1320 if (!tx) {
1321 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1322 /* FIXME: cleanup */
1323 return -1;
1324 }
1325
1326 tx->callback = omap_hsmmc_dma_callback;
1327 tx->callback_param = host;
1328
1329 /* Does not fail */
1330 dmaengine_submit(tx);
1331
1332 host->dma_ch = 1;
1333
1334 dma_async_issue_pending(chan);
1335
1336 return 0;
1337 }
1338
1339 static void set_data_timeout(struct omap_hsmmc_host *host,
1340 unsigned int timeout_ns,
1341 unsigned int timeout_clks)
1342 {
1343 unsigned int timeout, cycle_ns;
1344 uint32_t reg, clkd, dto = 0;
1345
1346 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1347 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1348 if (clkd == 0)
1349 clkd = 1;
1350
1351 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1352 timeout = timeout_ns / cycle_ns;
1353 timeout += timeout_clks;
1354 if (timeout) {
1355 while ((timeout & 0x80000000) == 0) {
1356 dto += 1;
1357 timeout <<= 1;
1358 }
1359 dto = 31 - dto;
1360 timeout <<= 1;
1361 if (timeout && dto)
1362 dto += 1;
1363 if (dto >= 13)
1364 dto -= 13;
1365 else
1366 dto = 0;
1367 if (dto > 14)
1368 dto = 14;
1369 }
1370
1371 reg &= ~DTO_MASK;
1372 reg |= dto << DTO_SHIFT;
1373 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1374 }
1375
1376 /*
1377 * Configure block length for MMC/SD cards and initiate the transfer.
1378 */
1379 static int
1380 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1381 {
1382 int ret;
1383 host->data = req->data;
1384
1385 if (req->data == NULL) {
1386 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1387 /*
1388 * Set an arbitrary 100ms data timeout for commands with
1389 * busy signal.
1390 */
1391 if (req->cmd->flags & MMC_RSP_BUSY)
1392 set_data_timeout(host, 100000000U, 0);
1393 return 0;
1394 }
1395
1396 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1397 | (req->data->blocks << 16));
1398 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1399
1400 if (host->use_dma) {
1401 ret = omap_hsmmc_start_dma_transfer(host, req);
1402 if (ret != 0) {
1403 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1404 return ret;
1405 }
1406 }
1407 return 0;
1408 }
1409
1410 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1411 int err)
1412 {
1413 struct omap_hsmmc_host *host = mmc_priv(mmc);
1414 struct mmc_data *data = mrq->data;
1415
1416 if (host->use_dma && data->host_cookie) {
1417 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1418
1419 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1420 omap_hsmmc_get_dma_dir(host, data));
1421 data->host_cookie = 0;
1422 }
1423 }
1424
1425 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1426 bool is_first_req)
1427 {
1428 struct omap_hsmmc_host *host = mmc_priv(mmc);
1429
1430 if (mrq->data->host_cookie) {
1431 mrq->data->host_cookie = 0;
1432 return ;
1433 }
1434
1435 if (host->use_dma) {
1436 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1437
1438 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1439 &host->next_data, c))
1440 mrq->data->host_cookie = 0;
1441 }
1442 }
1443
1444 /*
1445 * Request function. for read/write operation
1446 */
1447 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1448 {
1449 struct omap_hsmmc_host *host = mmc_priv(mmc);
1450 int err;
1451
1452 BUG_ON(host->req_in_progress);
1453 BUG_ON(host->dma_ch != -1);
1454 if (host->protect_card) {
1455 if (host->reqs_blocked < 3) {
1456 /*
1457 * Ensure the controller is left in a consistent
1458 * state by resetting the command and data state
1459 * machines.
1460 */
1461 omap_hsmmc_reset_controller_fsm(host, SRD);
1462 omap_hsmmc_reset_controller_fsm(host, SRC);
1463 host->reqs_blocked += 1;
1464 }
1465 req->cmd->error = -EBADF;
1466 if (req->data)
1467 req->data->error = -EBADF;
1468 req->cmd->retries = 0;
1469 mmc_request_done(mmc, req);
1470 return;
1471 } else if (host->reqs_blocked)
1472 host->reqs_blocked = 0;
1473 WARN_ON(host->mrq != NULL);
1474 host->mrq = req;
1475 err = omap_hsmmc_prepare_data(host, req);
1476 if (err) {
1477 req->cmd->error = err;
1478 if (req->data)
1479 req->data->error = err;
1480 host->mrq = NULL;
1481 mmc_request_done(mmc, req);
1482 return;
1483 }
1484
1485 omap_hsmmc_start_command(host, req->cmd, req->data);
1486 }
1487
1488 /* Routine to configure clock values. Exposed API to core */
1489 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1490 {
1491 struct omap_hsmmc_host *host = mmc_priv(mmc);
1492 int do_send_init_stream = 0;
1493
1494 pm_runtime_get_sync(host->dev);
1495
1496 if (ios->power_mode != host->power_mode) {
1497 switch (ios->power_mode) {
1498 case MMC_POWER_OFF:
1499 mmc_slot(host).set_power(host->dev, host->slot_id,
1500 0, 0);
1501 break;
1502 case MMC_POWER_UP:
1503 mmc_slot(host).set_power(host->dev, host->slot_id,
1504 1, ios->vdd);
1505 break;
1506 case MMC_POWER_ON:
1507 do_send_init_stream = 1;
1508 break;
1509 }
1510 host->power_mode = ios->power_mode;
1511 }
1512
1513 /* FIXME: set registers based only on changes to ios */
1514
1515 omap_hsmmc_set_bus_width(host);
1516
1517 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1518 /* Only MMC1 can interface at 3V without some flavor
1519 * of external transceiver; but they all handle 1.8V.
1520 */
1521 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1522 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1523 /*
1524 * With pbias cell programming missing, this
1525 * can't be allowed on MMC1 when booting with device
1526 * tree.
1527 */
1528 !host->pbias_disable) {
1529 /*
1530 * The mmc_select_voltage fn of the core does
1531 * not seem to set the power_mode to
1532 * MMC_POWER_UP upon recalculating the voltage.
1533 * vdd 1.8v.
1534 */
1535 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1536 dev_dbg(mmc_dev(host->mmc),
1537 "Switch operation failed\n");
1538 }
1539 }
1540
1541 omap_hsmmc_set_clock(host);
1542
1543 if (do_send_init_stream)
1544 send_init_stream(host);
1545
1546 omap_hsmmc_set_bus_mode(host);
1547
1548 pm_runtime_put_autosuspend(host->dev);
1549 }
1550
1551 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1552 {
1553 struct omap_hsmmc_host *host = mmc_priv(mmc);
1554
1555 if (!mmc_slot(host).card_detect)
1556 return -ENOSYS;
1557 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1558 }
1559
1560 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1561 {
1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
1563
1564 if (!mmc_slot(host).get_ro)
1565 return -ENOSYS;
1566 return mmc_slot(host).get_ro(host->dev, 0);
1567 }
1568
1569 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1570 {
1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
1572
1573 if (mmc_slot(host).init_card)
1574 mmc_slot(host).init_card(card);
1575 }
1576
1577 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1578 {
1579 u32 hctl, capa, value;
1580
1581 /* Only MMC1 supports 3.0V */
1582 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1583 hctl = SDVS30;
1584 capa = VS30 | VS18;
1585 } else {
1586 hctl = SDVS18;
1587 capa = VS18;
1588 }
1589
1590 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1591 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1592
1593 value = OMAP_HSMMC_READ(host->base, CAPA);
1594 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1595
1596 /* Set SD bus power bit */
1597 set_sd_bus_power(host);
1598 }
1599
1600 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1601 {
1602 struct omap_hsmmc_host *host = mmc_priv(mmc);
1603
1604 pm_runtime_get_sync(host->dev);
1605
1606 return 0;
1607 }
1608
1609 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1610 {
1611 struct omap_hsmmc_host *host = mmc_priv(mmc);
1612
1613 pm_runtime_mark_last_busy(host->dev);
1614 pm_runtime_put_autosuspend(host->dev);
1615
1616 return 0;
1617 }
1618
1619 static const struct mmc_host_ops omap_hsmmc_ops = {
1620 .enable = omap_hsmmc_enable_fclk,
1621 .disable = omap_hsmmc_disable_fclk,
1622 .post_req = omap_hsmmc_post_req,
1623 .pre_req = omap_hsmmc_pre_req,
1624 .request = omap_hsmmc_request,
1625 .set_ios = omap_hsmmc_set_ios,
1626 .get_cd = omap_hsmmc_get_cd,
1627 .get_ro = omap_hsmmc_get_ro,
1628 .init_card = omap_hsmmc_init_card,
1629 /* NYET -- enable_sdio_irq */
1630 };
1631
1632 #ifdef CONFIG_DEBUG_FS
1633
1634 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1635 {
1636 struct mmc_host *mmc = s->private;
1637 struct omap_hsmmc_host *host = mmc_priv(mmc);
1638 int context_loss = 0;
1639
1640 if (host->pdata->get_context_loss_count)
1641 context_loss = host->pdata->get_context_loss_count(host->dev);
1642
1643 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1644 mmc->index, host->context_loss, context_loss);
1645
1646 if (host->suspended) {
1647 seq_printf(s, "host suspended, can't read registers\n");
1648 return 0;
1649 }
1650
1651 pm_runtime_get_sync(host->dev);
1652
1653 seq_printf(s, "CON:\t\t0x%08x\n",
1654 OMAP_HSMMC_READ(host->base, CON));
1655 seq_printf(s, "HCTL:\t\t0x%08x\n",
1656 OMAP_HSMMC_READ(host->base, HCTL));
1657 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1658 OMAP_HSMMC_READ(host->base, SYSCTL));
1659 seq_printf(s, "IE:\t\t0x%08x\n",
1660 OMAP_HSMMC_READ(host->base, IE));
1661 seq_printf(s, "ISE:\t\t0x%08x\n",
1662 OMAP_HSMMC_READ(host->base, ISE));
1663 seq_printf(s, "CAPA:\t\t0x%08x\n",
1664 OMAP_HSMMC_READ(host->base, CAPA));
1665
1666 pm_runtime_mark_last_busy(host->dev);
1667 pm_runtime_put_autosuspend(host->dev);
1668
1669 return 0;
1670 }
1671
1672 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1673 {
1674 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1675 }
1676
1677 static const struct file_operations mmc_regs_fops = {
1678 .open = omap_hsmmc_regs_open,
1679 .read = seq_read,
1680 .llseek = seq_lseek,
1681 .release = single_release,
1682 };
1683
1684 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1685 {
1686 if (mmc->debugfs_root)
1687 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1688 mmc, &mmc_regs_fops);
1689 }
1690
1691 #else
1692
1693 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1694 {
1695 }
1696
1697 #endif
1698
1699 #ifdef CONFIG_OF
1700 static u16 omap4_reg_offset = 0x100;
1701
1702 static const struct of_device_id omap_mmc_of_match[] = {
1703 {
1704 .compatible = "ti,omap2-hsmmc",
1705 },
1706 {
1707 .compatible = "ti,omap3-hsmmc",
1708 },
1709 {
1710 .compatible = "ti,omap4-hsmmc",
1711 .data = &omap4_reg_offset,
1712 },
1713 {},
1714 };
1715 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1716
1717 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1718 {
1719 struct omap_mmc_platform_data *pdata;
1720 struct device_node *np = dev->of_node;
1721 u32 bus_width, max_freq;
1722 int cd_gpio, wp_gpio;
1723
1724 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1725 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1726 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1727 return ERR_PTR(-EPROBE_DEFER);
1728
1729 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1730 if (!pdata)
1731 return NULL; /* out of memory */
1732
1733 if (of_find_property(np, "ti,dual-volt", NULL))
1734 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1735
1736 /* This driver only supports 1 slot */
1737 pdata->nr_slots = 1;
1738 pdata->slots[0].switch_pin = cd_gpio;
1739 pdata->slots[0].gpio_wp = wp_gpio;
1740
1741 if (of_find_property(np, "ti,non-removable", NULL)) {
1742 pdata->slots[0].nonremovable = true;
1743 pdata->slots[0].no_regulator_off_init = true;
1744 }
1745 of_property_read_u32(np, "bus-width", &bus_width);
1746 if (bus_width == 4)
1747 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1748 else if (bus_width == 8)
1749 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1750
1751 if (of_find_property(np, "ti,needs-special-reset", NULL))
1752 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1753
1754 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1755 pdata->max_freq = max_freq;
1756
1757 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1758 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1759
1760 return pdata;
1761 }
1762 #else
1763 static inline struct omap_mmc_platform_data
1764 *of_get_hsmmc_pdata(struct device *dev)
1765 {
1766 return NULL;
1767 }
1768 #endif
1769
1770 static int omap_hsmmc_probe(struct platform_device *pdev)
1771 {
1772 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1773 struct mmc_host *mmc;
1774 struct omap_hsmmc_host *host = NULL;
1775 struct resource *res;
1776 int ret, irq;
1777 const struct of_device_id *match;
1778 dma_cap_mask_t mask;
1779 unsigned tx_req, rx_req;
1780 struct pinctrl *pinctrl;
1781
1782 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1783 if (match) {
1784 pdata = of_get_hsmmc_pdata(&pdev->dev);
1785
1786 if (IS_ERR(pdata))
1787 return PTR_ERR(pdata);
1788
1789 if (match->data) {
1790 const u16 *offsetp = match->data;
1791 pdata->reg_offset = *offsetp;
1792 }
1793 }
1794
1795 if (pdata == NULL) {
1796 dev_err(&pdev->dev, "Platform Data is missing\n");
1797 return -ENXIO;
1798 }
1799
1800 if (pdata->nr_slots == 0) {
1801 dev_err(&pdev->dev, "No Slots\n");
1802 return -ENXIO;
1803 }
1804
1805 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1806 irq = platform_get_irq(pdev, 0);
1807 if (res == NULL || irq < 0)
1808 return -ENXIO;
1809
1810 res = request_mem_region(res->start, resource_size(res), pdev->name);
1811 if (res == NULL)
1812 return -EBUSY;
1813
1814 ret = omap_hsmmc_gpio_init(pdata);
1815 if (ret)
1816 goto err;
1817
1818 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1819 if (!mmc) {
1820 ret = -ENOMEM;
1821 goto err_alloc;
1822 }
1823
1824 host = mmc_priv(mmc);
1825 host->mmc = mmc;
1826 host->pdata = pdata;
1827 host->dev = &pdev->dev;
1828 host->use_dma = 1;
1829 host->dma_ch = -1;
1830 host->irq = irq;
1831 host->slot_id = 0;
1832 host->mapbase = res->start + pdata->reg_offset;
1833 host->base = ioremap(host->mapbase, SZ_4K);
1834 host->power_mode = MMC_POWER_OFF;
1835 host->next_data.cookie = 1;
1836
1837 platform_set_drvdata(pdev, host);
1838
1839 mmc->ops = &omap_hsmmc_ops;
1840
1841 /*
1842 * If regulator_disable can only put vcc_aux to sleep then there is
1843 * no off state.
1844 */
1845 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1846 mmc_slot(host).no_off = 1;
1847
1848 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1849
1850 if (pdata->max_freq > 0)
1851 mmc->f_max = pdata->max_freq;
1852 else
1853 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1854
1855 spin_lock_init(&host->irq_lock);
1856
1857 host->fclk = clk_get(&pdev->dev, "fck");
1858 if (IS_ERR(host->fclk)) {
1859 ret = PTR_ERR(host->fclk);
1860 host->fclk = NULL;
1861 goto err1;
1862 }
1863
1864 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1865 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1866 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1867 }
1868
1869 pm_runtime_enable(host->dev);
1870 pm_runtime_get_sync(host->dev);
1871 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1872 pm_runtime_use_autosuspend(host->dev);
1873
1874 omap_hsmmc_context_save(host);
1875
1876 /* This can be removed once we support PBIAS with DT */
1877 if (host->dev->of_node && host->mapbase == 0x4809c000)
1878 host->pbias_disable = 1;
1879
1880 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1881 /*
1882 * MMC can still work without debounce clock.
1883 */
1884 if (IS_ERR(host->dbclk)) {
1885 host->dbclk = NULL;
1886 } else if (clk_prepare_enable(host->dbclk) != 0) {
1887 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1888 clk_put(host->dbclk);
1889 host->dbclk = NULL;
1890 }
1891
1892 /* Since we do only SG emulation, we can have as many segs
1893 * as we want. */
1894 mmc->max_segs = 1024;
1895
1896 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1897 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1898 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1899 mmc->max_seg_size = mmc->max_req_size;
1900
1901 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1902 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1903
1904 mmc->caps |= mmc_slot(host).caps;
1905 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1906 mmc->caps |= MMC_CAP_4_BIT_DATA;
1907
1908 if (mmc_slot(host).nonremovable)
1909 mmc->caps |= MMC_CAP_NONREMOVABLE;
1910
1911 mmc->pm_caps = mmc_slot(host).pm_caps;
1912
1913 omap_hsmmc_conf_bus_power(host);
1914
1915 if (!pdev->dev.of_node) {
1916 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1917 if (!res) {
1918 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1919 ret = -ENXIO;
1920 goto err_irq;
1921 }
1922 tx_req = res->start;
1923
1924 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1925 if (!res) {
1926 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1927 ret = -ENXIO;
1928 goto err_irq;
1929 }
1930 rx_req = res->start;
1931 }
1932
1933 dma_cap_zero(mask);
1934 dma_cap_set(DMA_SLAVE, mask);
1935
1936 host->rx_chan =
1937 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1938 &rx_req, &pdev->dev, "rx");
1939
1940 if (!host->rx_chan) {
1941 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1942 ret = -ENXIO;
1943 goto err_irq;
1944 }
1945
1946 host->tx_chan =
1947 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1948 &tx_req, &pdev->dev, "tx");
1949
1950 if (!host->tx_chan) {
1951 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1952 ret = -ENXIO;
1953 goto err_irq;
1954 }
1955
1956 /* Request IRQ for MMC operations */
1957 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1958 mmc_hostname(mmc), host);
1959 if (ret) {
1960 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1961 goto err_irq;
1962 }
1963
1964 if (pdata->init != NULL) {
1965 if (pdata->init(&pdev->dev) != 0) {
1966 dev_err(mmc_dev(host->mmc),
1967 "Unable to configure MMC IRQs\n");
1968 goto err_irq_cd_init;
1969 }
1970 }
1971
1972 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1973 ret = omap_hsmmc_reg_get(host);
1974 if (ret)
1975 goto err_reg;
1976 host->use_reg = 1;
1977 }
1978
1979 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1980
1981 /* Request IRQ for card detect */
1982 if ((mmc_slot(host).card_detect_irq)) {
1983 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1984 NULL,
1985 omap_hsmmc_detect,
1986 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1987 mmc_hostname(mmc), host);
1988 if (ret) {
1989 dev_err(mmc_dev(host->mmc),
1990 "Unable to grab MMC CD IRQ\n");
1991 goto err_irq_cd;
1992 }
1993 pdata->suspend = omap_hsmmc_suspend_cdirq;
1994 pdata->resume = omap_hsmmc_resume_cdirq;
1995 }
1996
1997 omap_hsmmc_disable_irq(host);
1998
1999 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2000 if (IS_ERR(pinctrl))
2001 dev_warn(&pdev->dev,
2002 "pins are not configured from the driver\n");
2003
2004 omap_hsmmc_protect_card(host);
2005
2006 mmc_add_host(mmc);
2007
2008 if (mmc_slot(host).name != NULL) {
2009 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2010 if (ret < 0)
2011 goto err_slot_name;
2012 }
2013 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2014 ret = device_create_file(&mmc->class_dev,
2015 &dev_attr_cover_switch);
2016 if (ret < 0)
2017 goto err_slot_name;
2018 }
2019
2020 omap_hsmmc_debugfs(mmc);
2021 pm_runtime_mark_last_busy(host->dev);
2022 pm_runtime_put_autosuspend(host->dev);
2023
2024 return 0;
2025
2026 err_slot_name:
2027 mmc_remove_host(mmc);
2028 free_irq(mmc_slot(host).card_detect_irq, host);
2029 err_irq_cd:
2030 if (host->use_reg)
2031 omap_hsmmc_reg_put(host);
2032 err_reg:
2033 if (host->pdata->cleanup)
2034 host->pdata->cleanup(&pdev->dev);
2035 err_irq_cd_init:
2036 free_irq(host->irq, host);
2037 err_irq:
2038 if (host->tx_chan)
2039 dma_release_channel(host->tx_chan);
2040 if (host->rx_chan)
2041 dma_release_channel(host->rx_chan);
2042 pm_runtime_put_sync(host->dev);
2043 pm_runtime_disable(host->dev);
2044 clk_put(host->fclk);
2045 if (host->dbclk) {
2046 clk_disable_unprepare(host->dbclk);
2047 clk_put(host->dbclk);
2048 }
2049 err1:
2050 iounmap(host->base);
2051 mmc_free_host(mmc);
2052 err_alloc:
2053 omap_hsmmc_gpio_free(pdata);
2054 err:
2055 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2056 if (res)
2057 release_mem_region(res->start, resource_size(res));
2058 return ret;
2059 }
2060
2061 static int omap_hsmmc_remove(struct platform_device *pdev)
2062 {
2063 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2064 struct resource *res;
2065
2066 pm_runtime_get_sync(host->dev);
2067 mmc_remove_host(host->mmc);
2068 if (host->use_reg)
2069 omap_hsmmc_reg_put(host);
2070 if (host->pdata->cleanup)
2071 host->pdata->cleanup(&pdev->dev);
2072 free_irq(host->irq, host);
2073 if (mmc_slot(host).card_detect_irq)
2074 free_irq(mmc_slot(host).card_detect_irq, host);
2075
2076 if (host->tx_chan)
2077 dma_release_channel(host->tx_chan);
2078 if (host->rx_chan)
2079 dma_release_channel(host->rx_chan);
2080
2081 pm_runtime_put_sync(host->dev);
2082 pm_runtime_disable(host->dev);
2083 clk_put(host->fclk);
2084 if (host->dbclk) {
2085 clk_disable_unprepare(host->dbclk);
2086 clk_put(host->dbclk);
2087 }
2088
2089 omap_hsmmc_gpio_free(host->pdata);
2090 iounmap(host->base);
2091 mmc_free_host(host->mmc);
2092
2093 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2094 if (res)
2095 release_mem_region(res->start, resource_size(res));
2096
2097 return 0;
2098 }
2099
2100 #ifdef CONFIG_PM
2101 static int omap_hsmmc_prepare(struct device *dev)
2102 {
2103 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2104
2105 if (host->pdata->suspend)
2106 return host->pdata->suspend(dev, host->slot_id);
2107
2108 return 0;
2109 }
2110
2111 static void omap_hsmmc_complete(struct device *dev)
2112 {
2113 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2114
2115 if (host->pdata->resume)
2116 host->pdata->resume(dev, host->slot_id);
2117
2118 }
2119
2120 static int omap_hsmmc_suspend(struct device *dev)
2121 {
2122 int ret = 0;
2123 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2124
2125 if (!host)
2126 return 0;
2127
2128 if (host && host->suspended)
2129 return 0;
2130
2131 pm_runtime_get_sync(host->dev);
2132 host->suspended = 1;
2133 ret = mmc_suspend_host(host->mmc);
2134
2135 if (ret) {
2136 host->suspended = 0;
2137 goto err;
2138 }
2139
2140 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2141 omap_hsmmc_disable_irq(host);
2142 OMAP_HSMMC_WRITE(host->base, HCTL,
2143 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2144 }
2145
2146 if (host->dbclk)
2147 clk_disable_unprepare(host->dbclk);
2148 err:
2149 pm_runtime_put_sync(host->dev);
2150 return ret;
2151 }
2152
2153 /* Routine to resume the MMC device */
2154 static int omap_hsmmc_resume(struct device *dev)
2155 {
2156 int ret = 0;
2157 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2158
2159 if (!host)
2160 return 0;
2161
2162 if (host && !host->suspended)
2163 return 0;
2164
2165 pm_runtime_get_sync(host->dev);
2166
2167 if (host->dbclk)
2168 clk_prepare_enable(host->dbclk);
2169
2170 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2171 omap_hsmmc_conf_bus_power(host);
2172
2173 omap_hsmmc_protect_card(host);
2174
2175 /* Notify the core to resume the host */
2176 ret = mmc_resume_host(host->mmc);
2177 if (ret == 0)
2178 host->suspended = 0;
2179
2180 pm_runtime_mark_last_busy(host->dev);
2181 pm_runtime_put_autosuspend(host->dev);
2182
2183 return ret;
2184
2185 }
2186
2187 #else
2188 #define omap_hsmmc_prepare NULL
2189 #define omap_hsmmc_complete NULL
2190 #define omap_hsmmc_suspend NULL
2191 #define omap_hsmmc_resume NULL
2192 #endif
2193
2194 static int omap_hsmmc_runtime_suspend(struct device *dev)
2195 {
2196 struct omap_hsmmc_host *host;
2197
2198 host = platform_get_drvdata(to_platform_device(dev));
2199 omap_hsmmc_context_save(host);
2200 dev_dbg(dev, "disabled\n");
2201
2202 return 0;
2203 }
2204
2205 static int omap_hsmmc_runtime_resume(struct device *dev)
2206 {
2207 struct omap_hsmmc_host *host;
2208
2209 host = platform_get_drvdata(to_platform_device(dev));
2210 omap_hsmmc_context_restore(host);
2211 dev_dbg(dev, "enabled\n");
2212
2213 return 0;
2214 }
2215
2216 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2217 .suspend = omap_hsmmc_suspend,
2218 .resume = omap_hsmmc_resume,
2219 .prepare = omap_hsmmc_prepare,
2220 .complete = omap_hsmmc_complete,
2221 .runtime_suspend = omap_hsmmc_runtime_suspend,
2222 .runtime_resume = omap_hsmmc_runtime_resume,
2223 };
2224
2225 static struct platform_driver omap_hsmmc_driver = {
2226 .probe = omap_hsmmc_probe,
2227 .remove = omap_hsmmc_remove,
2228 .driver = {
2229 .name = DRIVER_NAME,
2230 .owner = THIS_MODULE,
2231 .pm = &omap_hsmmc_dev_pm_ops,
2232 .of_match_table = of_match_ptr(omap_mmc_of_match),
2233 },
2234 };
2235
2236 module_platform_driver(omap_hsmmc_driver);
2237 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2238 MODULE_LICENSE("GPL");
2239 MODULE_ALIAS("platform:" DRIVER_NAME);
2240 MODULE_AUTHOR("Texas Instruments Inc");
Linux with added FPC-III support