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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
blob54e8ba45c3ad343e76be8b255372d144cc7d8875
1 /* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/highmem.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/sd.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mfd/rtsx_pci.h>
32 #include <asm/unaligned.h>
33
34 /* SD Tuning Data Structure
35 * Record continuous timing phase path
36 */
37 struct timing_phase_path {
38 int start;
39 int end;
40 int mid;
41 int len;
42 };
43
44 struct realtek_pci_sdmmc {
45 struct platform_device *pdev;
46 struct rtsx_pcr *pcr;
47 struct mmc_host *mmc;
48 struct mmc_request *mrq;
49
50 struct mutex host_mutex;
51
52 u8 ssc_depth;
53 unsigned int clock;
54 bool vpclk;
55 bool double_clk;
56 bool eject;
57 bool initial_mode;
58 int power_state;
59 #define SDMMC_POWER_ON 1
60 #define SDMMC_POWER_OFF 0
61 };
62
63 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
64 {
65 return &(host->pdev->dev);
66 }
67
68 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
69 {
70 rtsx_pci_write_register(host->pcr, CARD_STOP,
71 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
72 }
73
74 #ifdef DEBUG
75 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
76 {
77 struct rtsx_pcr *pcr = host->pcr;
78 u16 i;
79 u8 *ptr;
80
81 /* Print SD host internal registers */
82 rtsx_pci_init_cmd(pcr);
83 for (i = 0xFDA0; i <= 0xFDAE; i++)
84 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
85 for (i = 0xFD52; i <= 0xFD69; i++)
86 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
87 rtsx_pci_send_cmd(pcr, 100);
88
89 ptr = rtsx_pci_get_cmd_data(pcr);
90 for (i = 0xFDA0; i <= 0xFDAE; i++)
91 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
92 for (i = 0xFD52; i <= 0xFD69; i++)
93 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
94 }
95 #else
96 #define sd_print_debug_regs(host)
97 #endif /* DEBUG */
98
99 static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
100 u8 *buf, int buf_len, int timeout)
101 {
102 struct rtsx_pcr *pcr = host->pcr;
103 int err, i;
104 u8 trans_mode;
105
106 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
107
108 if (!buf)
109 buf_len = 0;
110
111 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
112 trans_mode = SD_TM_AUTO_TUNING;
113 else
114 trans_mode = SD_TM_NORMAL_READ;
115
116 rtsx_pci_init_cmd(pcr);
117
118 for (i = 0; i < 5; i++)
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
120
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
123 0xFF, (u8)(byte_cnt >> 8));
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
125 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
126
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
128 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
129 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
130 if (trans_mode != SD_TM_AUTO_TUNING)
131 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
132 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
133
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
135 0xFF, trans_mode | SD_TRANSFER_START);
136 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
137 SD_TRANSFER_END, SD_TRANSFER_END);
138
139 err = rtsx_pci_send_cmd(pcr, timeout);
140 if (err < 0) {
141 sd_print_debug_regs(host);
142 dev_dbg(sdmmc_dev(host),
143 "rtsx_pci_send_cmd fail (err = %d)\n", err);
144 return err;
145 }
146
147 if (buf && buf_len) {
148 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
149 if (err < 0) {
150 dev_dbg(sdmmc_dev(host),
151 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
152 return err;
153 }
154 }
155
156 return 0;
157 }
158
159 static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
160 u8 *buf, int buf_len, int timeout)
161 {
162 struct rtsx_pcr *pcr = host->pcr;
163 int err, i;
164 u8 trans_mode;
165
166 if (!buf)
167 buf_len = 0;
168
169 if (buf && buf_len) {
170 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
171 if (err < 0) {
172 dev_dbg(sdmmc_dev(host),
173 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
174 return err;
175 }
176 }
177
178 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
179 rtsx_pci_init_cmd(pcr);
180
181 if (cmd) {
182 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
183 cmd[0] - 0x40);
184
185 for (i = 0; i < 5; i++)
186 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
187 SD_CMD0 + i, 0xFF, cmd[i]);
188 }
189
190 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
192 0xFF, (u8)(byte_cnt >> 8));
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
194 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
195
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
197 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
198 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
199
200 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
201 trans_mode | SD_TRANSFER_START);
202 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
203 SD_TRANSFER_END, SD_TRANSFER_END);
204
205 err = rtsx_pci_send_cmd(pcr, timeout);
206 if (err < 0) {
207 sd_print_debug_regs(host);
208 dev_dbg(sdmmc_dev(host),
209 "rtsx_pci_send_cmd fail (err = %d)\n", err);
210 return err;
211 }
212
213 return 0;
214 }
215
216 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
217 struct mmc_command *cmd)
218 {
219 struct rtsx_pcr *pcr = host->pcr;
220 u8 cmd_idx = (u8)cmd->opcode;
221 u32 arg = cmd->arg;
222 int err = 0;
223 int timeout = 100;
224 int i;
225 u8 *ptr;
226 int stat_idx = 0;
227 u8 rsp_type;
228 int rsp_len = 5;
229 bool clock_toggled = false;
230
231 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
232 __func__, cmd_idx, arg);
233
234 /* Response type:
235 * R0
236 * R1, R5, R6, R7
237 * R1b
238 * R2
239 * R3, R4
240 */
241 switch (mmc_resp_type(cmd)) {
242 case MMC_RSP_NONE:
243 rsp_type = SD_RSP_TYPE_R0;
244 rsp_len = 0;
245 break;
246 case MMC_RSP_R1:
247 rsp_type = SD_RSP_TYPE_R1;
248 break;
249 case MMC_RSP_R1 & ~MMC_RSP_CRC:
250 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
251 break;
252 case MMC_RSP_R1B:
253 rsp_type = SD_RSP_TYPE_R1b;
254 break;
255 case MMC_RSP_R2:
256 rsp_type = SD_RSP_TYPE_R2;
257 rsp_len = 16;
258 break;
259 case MMC_RSP_R3:
260 rsp_type = SD_RSP_TYPE_R3;
261 break;
262 default:
263 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
264 err = -EINVAL;
265 goto out;
266 }
267
268 if (rsp_type == SD_RSP_TYPE_R1b)
269 timeout = 3000;
270
271 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
272 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
273 0xFF, SD_CLK_TOGGLE_EN);
274 if (err < 0)
275 goto out;
276
277 clock_toggled = true;
278 }
279
280 rtsx_pci_init_cmd(pcr);
281
282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
285 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
286 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
287
288 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
290 0x01, PINGPONG_BUFFER);
291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
292 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
293 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
294 SD_TRANSFER_END | SD_STAT_IDLE,
295 SD_TRANSFER_END | SD_STAT_IDLE);
296
297 if (rsp_type == SD_RSP_TYPE_R2) {
298 /* Read data from ping-pong buffer */
299 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
300 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
301 stat_idx = 16;
302 } else if (rsp_type != SD_RSP_TYPE_R0) {
303 /* Read data from SD_CMDx registers */
304 for (i = SD_CMD0; i <= SD_CMD4; i++)
305 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
306 stat_idx = 5;
307 }
308
309 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
310
311 err = rtsx_pci_send_cmd(pcr, timeout);
312 if (err < 0) {
313 sd_print_debug_regs(host);
314 sd_clear_error(host);
315 dev_dbg(sdmmc_dev(host),
316 "rtsx_pci_send_cmd error (err = %d)\n", err);
317 goto out;
318 }
319
320 if (rsp_type == SD_RSP_TYPE_R0) {
321 err = 0;
322 goto out;
323 }
324
325 /* Eliminate returned value of CHECK_REG_CMD */
326 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
327
328 /* Check (Start,Transmission) bit of Response */
329 if ((ptr[0] & 0xC0) != 0) {
330 err = -EILSEQ;
331 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
332 goto out;
333 }
334
335 /* Check CRC7 */
336 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
337 if (ptr[stat_idx] & SD_CRC7_ERR) {
338 err = -EILSEQ;
339 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
340 goto out;
341 }
342 }
343
344 if (rsp_type == SD_RSP_TYPE_R2) {
345 for (i = 0; i < 4; i++) {
346 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
347 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
348 i, cmd->resp[i]);
349 }
350 } else {
351 cmd->resp[0] = get_unaligned_be32(ptr + 1);
352 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
353 cmd->resp[0]);
354 }
355
356 out:
357 cmd->error = err;
358
359 if (err && clock_toggled)
360 rtsx_pci_write_register(pcr, SD_BUS_STAT,
361 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
362 }
363
364 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
365 {
366 struct rtsx_pcr *pcr = host->pcr;
367 struct mmc_host *mmc = host->mmc;
368 struct mmc_card *card = mmc->card;
369 struct mmc_data *data = mrq->data;
370 int uhs = mmc_sd_card_uhs(card);
371 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
372 u8 cfg2, trans_mode;
373 int err;
374 size_t data_len = data->blksz * data->blocks;
375
376 if (read) {
377 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
378 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
379 trans_mode = SD_TM_AUTO_READ_3;
380 } else {
381 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
382 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
383 trans_mode = SD_TM_AUTO_WRITE_3;
384 }
385
386 if (!uhs)
387 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
388
389 rtsx_pci_init_cmd(pcr);
390
391 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
392 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
393 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
394 0xFF, (u8)data->blocks);
395 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
396 0xFF, (u8)(data->blocks >> 8));
397
398 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
399 DMA_DONE_INT, DMA_DONE_INT);
400 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
401 0xFF, (u8)(data_len >> 24));
402 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
403 0xFF, (u8)(data_len >> 16));
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
405 0xFF, (u8)(data_len >> 8));
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
407 if (read) {
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
409 0x03 | DMA_PACK_SIZE_MASK,
410 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
411 } else {
412 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
413 0x03 | DMA_PACK_SIZE_MASK,
414 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
415 }
416
417 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
418 0x01, RING_BUFFER);
419
420 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
421 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
422 trans_mode | SD_TRANSFER_START);
423 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
424 SD_TRANSFER_END, SD_TRANSFER_END);
425
426 rtsx_pci_send_cmd_no_wait(pcr);
427
428 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
429 if (err < 0) {
430 sd_clear_error(host);
431 return err;
432 }
433
434 return 0;
435 }
436
437 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
438 {
439 rtsx_pci_write_register(host->pcr, SD_CFG1,
440 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
441 }
442
443 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
444 {
445 rtsx_pci_write_register(host->pcr, SD_CFG1,
446 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
447 }
448
449 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
450 struct mmc_request *mrq)
451 {
452 struct mmc_command *cmd = mrq->cmd;
453 struct mmc_data *data = mrq->data;
454 u8 _cmd[5], *buf;
455
456 _cmd[0] = 0x40 | (u8)cmd->opcode;
457 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
458
459 buf = kzalloc(data->blksz, GFP_NOIO);
460 if (!buf) {
461 cmd->error = -ENOMEM;
462 return;
463 }
464
465 if (data->flags & MMC_DATA_READ) {
466 if (host->initial_mode)
467 sd_disable_initial_mode(host);
468
469 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
470 data->blksz, 200);
471
472 if (host->initial_mode)
473 sd_enable_initial_mode(host);
474
475 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
476 } else {
477 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
478
479 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
480 data->blksz, 200);
481 }
482
483 kfree(buf);
484 }
485
486 static int sd_change_phase(struct realtek_pci_sdmmc *host,
487 u8 sample_point, bool rx)
488 {
489 struct rtsx_pcr *pcr = host->pcr;
490 int err;
491
492 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
493 __func__, rx ? "RX" : "TX", sample_point);
494
495 rtsx_pci_init_cmd(pcr);
496
497 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
498 if (rx)
499 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
500 SD_VPRX_CTL, 0x1F, sample_point);
501 else
502 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
503 SD_VPTX_CTL, 0x1F, sample_point);
504 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
505 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
506 PHASE_NOT_RESET, PHASE_NOT_RESET);
507 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
508 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
509
510 err = rtsx_pci_send_cmd(pcr, 100);
511 if (err < 0)
512 return err;
513
514 return 0;
515 }
516
517 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
518 {
519 struct timing_phase_path path[MAX_PHASE + 1];
520 int i, j, cont_path_cnt;
521 int new_block, max_len, final_path_idx;
522 u8 final_phase = 0xFF;
523
524 /* Parse phase_map, take it as a bit-ring */
525 cont_path_cnt = 0;
526 new_block = 1;
527 j = 0;
528 for (i = 0; i < MAX_PHASE + 1; i++) {
529 if (phase_map & (1 << i)) {
530 if (new_block) {
531 new_block = 0;
532 j = cont_path_cnt++;
533 path[j].start = i;
534 path[j].end = i;
535 } else {
536 path[j].end = i;
537 }
538 } else {
539 new_block = 1;
540 if (cont_path_cnt) {
541 /* Calculate path length and middle point */
542 int idx = cont_path_cnt - 1;
543 path[idx].len =
544 path[idx].end - path[idx].start + 1;
545 path[idx].mid =
546 path[idx].start + path[idx].len / 2;
547 }
548 }
549 }
550
551 if (cont_path_cnt == 0) {
552 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
553 goto finish;
554 } else {
555 /* Calculate last continuous path length and middle point */
556 int idx = cont_path_cnt - 1;
557 path[idx].len = path[idx].end - path[idx].start + 1;
558 path[idx].mid = path[idx].start + path[idx].len / 2;
559 }
560
561 /* Connect the first and last continuous paths if they are adjacent */
562 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
563 /* Using negative index */
564 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
565 path[0].len += path[cont_path_cnt - 1].len;
566 path[0].mid = path[0].start + path[0].len / 2;
567 /* Convert negative middle point index to positive one */
568 if (path[0].mid < 0)
569 path[0].mid += MAX_PHASE + 1;
570 cont_path_cnt--;
571 }
572
573 /* Choose the longest continuous phase path */
574 max_len = 0;
575 final_phase = 0;
576 final_path_idx = 0;
577 for (i = 0; i < cont_path_cnt; i++) {
578 if (path[i].len > max_len) {
579 max_len = path[i].len;
580 final_phase = (u8)path[i].mid;
581 final_path_idx = i;
582 }
583
584 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
585 i, path[i].start);
586 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
587 i, path[i].end);
588 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
589 i, path[i].len);
590 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
591 i, path[i].mid);
592 }
593
594 finish:
595 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
596 return final_phase;
597 }
598
599 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
600 {
601 int err, i;
602 u8 val = 0;
603
604 for (i = 0; i < 100; i++) {
605 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
606 if (val & SD_DATA_IDLE)
607 return;
608
609 udelay(100);
610 }
611 }
612
613 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
614 u8 opcode, u8 sample_point)
615 {
616 int err;
617 u8 cmd[5] = {0};
618
619 err = sd_change_phase(host, sample_point, true);
620 if (err < 0)
621 return err;
622
623 cmd[0] = 0x40 | opcode;
624 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
625 if (err < 0) {
626 /* Wait till SD DATA IDLE */
627 sd_wait_data_idle(host);
628 sd_clear_error(host);
629 return err;
630 }
631
632 return 0;
633 }
634
635 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
636 u8 opcode, u32 *phase_map)
637 {
638 int err, i;
639 u32 raw_phase_map = 0;
640
641 for (i = MAX_PHASE; i >= 0; i--) {
642 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
643 if (err == 0)
644 raw_phase_map |= 1 << i;
645 }
646
647 if (phase_map)
648 *phase_map = raw_phase_map;
649
650 return 0;
651 }
652
653 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
654 {
655 int err, i;
656 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
657 u8 final_phase;
658
659 for (i = 0; i < RX_TUNING_CNT; i++) {
660 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
661 if (err < 0)
662 return err;
663
664 if (raw_phase_map[i] == 0)
665 break;
666 }
667
668 phase_map = 0xFFFFFFFF;
669 for (i = 0; i < RX_TUNING_CNT; i++) {
670 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
671 i, raw_phase_map[i]);
672 phase_map &= raw_phase_map[i];
673 }
674 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
675
676 if (phase_map) {
677 final_phase = sd_search_final_phase(host, phase_map);
678 if (final_phase == 0xFF)
679 return -EINVAL;
680
681 err = sd_change_phase(host, final_phase, true);
682 if (err < 0)
683 return err;
684 } else {
685 return -EINVAL;
686 }
687
688 return 0;
689 }
690
691 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
692 {
693 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
694 struct rtsx_pcr *pcr = host->pcr;
695 struct mmc_command *cmd = mrq->cmd;
696 struct mmc_data *data = mrq->data;
697 unsigned int data_size = 0;
698 int err;
699
700 if (host->eject) {
701 cmd->error = -ENOMEDIUM;
702 goto finish;
703 }
704
705 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
706 if (err) {
707 cmd->error = err;
708 goto finish;
709 }
710
711 mutex_lock(&pcr->pcr_mutex);
712
713 rtsx_pci_start_run(pcr);
714
715 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
716 host->initial_mode, host->double_clk, host->vpclk);
717 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
718 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
719 CARD_SHARE_MASK, CARD_SHARE_48_SD);
720
721 mutex_lock(&host->host_mutex);
722 host->mrq = mrq;
723 mutex_unlock(&host->host_mutex);
724
725 if (mrq->data)
726 data_size = data->blocks * data->blksz;
727
728 if (!data_size || mmc_op_multi(cmd->opcode) ||
729 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
730 (cmd->opcode == MMC_WRITE_BLOCK)) {
731 sd_send_cmd_get_rsp(host, cmd);
732
733 if (!cmd->error && data_size) {
734 sd_rw_multi(host, mrq);
735
736 if (mmc_op_multi(cmd->opcode) && mrq->stop)
737 sd_send_cmd_get_rsp(host, mrq->stop);
738 }
739 } else {
740 sd_normal_rw(host, mrq);
741 }
742
743 if (mrq->data) {
744 if (cmd->error || data->error)
745 data->bytes_xfered = 0;
746 else
747 data->bytes_xfered = data->blocks * data->blksz;
748 }
749
750 mutex_unlock(&pcr->pcr_mutex);
751
752 finish:
753 if (cmd->error)
754 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
755
756 mutex_lock(&host->host_mutex);
757 host->mrq = NULL;
758 mutex_unlock(&host->host_mutex);
759
760 mmc_request_done(mmc, mrq);
761 }
762
763 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
764 unsigned char bus_width)
765 {
766 int err = 0;
767 u8 width[] = {
768 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
769 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
770 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
771 };
772
773 if (bus_width <= MMC_BUS_WIDTH_8)
774 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
775 0x03, width[bus_width]);
776
777 return err;
778 }
779
780 static int sd_power_on(struct realtek_pci_sdmmc *host)
781 {
782 struct rtsx_pcr *pcr = host->pcr;
783 int err;
784
785 if (host->power_state == SDMMC_POWER_ON)
786 return 0;
787
788 rtsx_pci_init_cmd(pcr);
789 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
790 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
791 CARD_SHARE_MASK, CARD_SHARE_48_SD);
792 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
793 SD_CLK_EN, SD_CLK_EN);
794 err = rtsx_pci_send_cmd(pcr, 100);
795 if (err < 0)
796 return err;
797
798 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
799 if (err < 0)
800 return err;
801
802 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
803 if (err < 0)
804 return err;
805
806 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
807 if (err < 0)
808 return err;
809
810 host->power_state = SDMMC_POWER_ON;
811 return 0;
812 }
813
814 static int sd_power_off(struct realtek_pci_sdmmc *host)
815 {
816 struct rtsx_pcr *pcr = host->pcr;
817 int err;
818
819 host->power_state = SDMMC_POWER_OFF;
820
821 rtsx_pci_init_cmd(pcr);
822
823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
824 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
825
826 err = rtsx_pci_send_cmd(pcr, 100);
827 if (err < 0)
828 return err;
829
830 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
831 if (err < 0)
832 return err;
833
834 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
835 }
836
837 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
838 unsigned char power_mode)
839 {
840 int err;
841
842 if (power_mode == MMC_POWER_OFF)
843 err = sd_power_off(host);
844 else
845 err = sd_power_on(host);
846
847 return err;
848 }
849
850 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
851 {
852 struct rtsx_pcr *pcr = host->pcr;
853 int err = 0;
854
855 rtsx_pci_init_cmd(pcr);
856
857 switch (timing) {
858 case MMC_TIMING_UHS_SDR104:
859 case MMC_TIMING_UHS_SDR50:
860 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
861 0x0C | SD_ASYNC_FIFO_NOT_RST,
862 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
863 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
864 CLK_LOW_FREQ, CLK_LOW_FREQ);
865 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
866 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
867 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
868 break;
869
870 case MMC_TIMING_UHS_DDR50:
871 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
872 0x0C | SD_ASYNC_FIFO_NOT_RST,
873 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
874 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
875 CLK_LOW_FREQ, CLK_LOW_FREQ);
876 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
877 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
878 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
879 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
880 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
882 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
883 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
884 break;
885
886 case MMC_TIMING_MMC_HS:
887 case MMC_TIMING_SD_HS:
888 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
889 0x0C, SD_20_MODE);
890 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
891 CLK_LOW_FREQ, CLK_LOW_FREQ);
892 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
893 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
894 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
896 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
897 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
898 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
899 break;
900
901 default:
902 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
903 SD_CFG1, 0x0C, SD_20_MODE);
904 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
905 CLK_LOW_FREQ, CLK_LOW_FREQ);
906 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
907 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
908 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
909 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
910 SD_PUSH_POINT_CTL, 0xFF, 0);
911 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
912 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
913 break;
914 }
915
916 err = rtsx_pci_send_cmd(pcr, 100);
917
918 return err;
919 }
920
921 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
922 {
923 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
924 struct rtsx_pcr *pcr = host->pcr;
925
926 if (host->eject)
927 return;
928
929 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
930 return;
931
932 mutex_lock(&pcr->pcr_mutex);
933
934 rtsx_pci_start_run(pcr);
935
936 sd_set_bus_width(host, ios->bus_width);
937 sd_set_power_mode(host, ios->power_mode);
938 sd_set_timing(host, ios->timing);
939
940 host->vpclk = false;
941 host->double_clk = true;
942
943 switch (ios->timing) {
944 case MMC_TIMING_UHS_SDR104:
945 case MMC_TIMING_UHS_SDR50:
946 host->ssc_depth = RTSX_SSC_DEPTH_2M;
947 host->vpclk = true;
948 host->double_clk = false;
949 break;
950 case MMC_TIMING_UHS_DDR50:
951 case MMC_TIMING_UHS_SDR25:
952 host->ssc_depth = RTSX_SSC_DEPTH_1M;
953 break;
954 default:
955 host->ssc_depth = RTSX_SSC_DEPTH_500K;
956 break;
957 }
958
959 host->initial_mode = (ios->clock <= 1000000) ? true : false;
960
961 host->clock = ios->clock;
962 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
963 host->initial_mode, host->double_clk, host->vpclk);
964
965 mutex_unlock(&pcr->pcr_mutex);
966 }
967
968 static int sdmmc_get_ro(struct mmc_host *mmc)
969 {
970 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
971 struct rtsx_pcr *pcr = host->pcr;
972 int ro = 0;
973 u32 val;
974
975 if (host->eject)
976 return -ENOMEDIUM;
977
978 mutex_lock(&pcr->pcr_mutex);
979
980 rtsx_pci_start_run(pcr);
981
982 /* Check SD mechanical write-protect switch */
983 val = rtsx_pci_readl(pcr, RTSX_BIPR);
984 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
985 if (val & SD_WRITE_PROTECT)
986 ro = 1;
987
988 mutex_unlock(&pcr->pcr_mutex);
989
990 return ro;
991 }
992
993 static int sdmmc_get_cd(struct mmc_host *mmc)
994 {
995 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
996 struct rtsx_pcr *pcr = host->pcr;
997 int cd = 0;
998 u32 val;
999
1000 if (host->eject)
1001 return -ENOMEDIUM;
1002
1003 mutex_lock(&pcr->pcr_mutex);
1004
1005 rtsx_pci_start_run(pcr);
1006
1007 /* Check SD card detect */
1008 val = rtsx_pci_card_exist(pcr);
1009 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1010 if (val & SD_EXIST)
1011 cd = 1;
1012
1013 mutex_unlock(&pcr->pcr_mutex);
1014
1015 return cd;
1016 }
1017
1018 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1019 {
1020 struct rtsx_pcr *pcr = host->pcr;
1021 int err;
1022 u8 stat;
1023
1024 /* Reference to Signal Voltage Switch Sequence in SD spec.
1025 * Wait for a period of time so that the card can drive SD_CMD and
1026 * SD_DAT[3:0] to low after sending back CMD11 response.
1027 */
1028 mdelay(1);
1029
1030 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1031 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1032 * abort the voltage switch sequence;
1033 */
1034 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1035 if (err < 0)
1036 return err;
1037
1038 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1039 SD_DAT1_STATUS | SD_DAT0_STATUS))
1040 return -EINVAL;
1041
1042 /* Stop toggle SD clock */
1043 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1044 0xFF, SD_CLK_FORCE_STOP);
1045 if (err < 0)
1046 return err;
1047
1048 return 0;
1049 }
1050
1051 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1052 {
1053 struct rtsx_pcr *pcr = host->pcr;
1054 int err;
1055 u8 stat, mask, val;
1056
1057 /* Wait 1.8V output of voltage regulator in card stable */
1058 msleep(50);
1059
1060 /* Toggle SD clock again */
1061 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1062 if (err < 0)
1063 return err;
1064
1065 /* Wait for a period of time so that the card can drive
1066 * SD_DAT[3:0] to high at 1.8V
1067 */
1068 msleep(20);
1069
1070 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1071 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1072 if (err < 0)
1073 return err;
1074
1075 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1076 SD_DAT1_STATUS | SD_DAT0_STATUS;
1077 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1078 SD_DAT1_STATUS | SD_DAT0_STATUS;
1079 if ((stat & mask) != val) {
1080 dev_dbg(sdmmc_dev(host),
1081 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1082 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1083 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1084 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1085 return -EINVAL;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1092 {
1093 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1094 struct rtsx_pcr *pcr = host->pcr;
1095 int err = 0;
1096 u8 voltage;
1097
1098 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1099 __func__, ios->signal_voltage);
1100
1101 if (host->eject)
1102 return -ENOMEDIUM;
1103
1104 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1105 if (err)
1106 return err;
1107
1108 mutex_lock(&pcr->pcr_mutex);
1109
1110 rtsx_pci_start_run(pcr);
1111
1112 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1113 voltage = OUTPUT_3V3;
1114 else
1115 voltage = OUTPUT_1V8;
1116
1117 if (voltage == OUTPUT_1V8) {
1118 err = sd_wait_voltage_stable_1(host);
1119 if (err < 0)
1120 goto out;
1121 }
1122
1123 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1124 if (err < 0)
1125 goto out;
1126
1127 if (voltage == OUTPUT_1V8) {
1128 err = sd_wait_voltage_stable_2(host);
1129 if (err < 0)
1130 goto out;
1131 }
1132
1133 out:
1134 /* Stop toggle SD clock in idle */
1135 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1136 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1137
1138 mutex_unlock(&pcr->pcr_mutex);
1139
1140 return err;
1141 }
1142
1143 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1144 {
1145 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1146 struct rtsx_pcr *pcr = host->pcr;
1147 int err = 0;
1148
1149 if (host->eject)
1150 return -ENOMEDIUM;
1151
1152 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1153 if (err)
1154 return err;
1155
1156 mutex_lock(&pcr->pcr_mutex);
1157
1158 rtsx_pci_start_run(pcr);
1159
1160 /* Set initial TX phase */
1161 switch (mmc->ios.timing) {
1162 case MMC_TIMING_UHS_SDR104:
1163 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1164 break;
1165
1166 case MMC_TIMING_UHS_SDR50:
1167 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1168 break;
1169
1170 case MMC_TIMING_UHS_DDR50:
1171 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1172 break;
1173
1174 default:
1175 err = 0;
1176 }
1177
1178 if (err)
1179 goto out;
1180
1181 /* Tuning RX phase */
1182 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1183 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1184 err = sd_tuning_rx(host, opcode);
1185 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1186 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1187
1188 out:
1189 mutex_unlock(&pcr->pcr_mutex);
1190
1191 return err;
1192 }
1193
1194 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1195 .request = sdmmc_request,
1196 .set_ios = sdmmc_set_ios,
1197 .get_ro = sdmmc_get_ro,
1198 .get_cd = sdmmc_get_cd,
1199 .start_signal_voltage_switch = sdmmc_switch_voltage,
1200 .execute_tuning = sdmmc_execute_tuning,
1201 };
1202
1203 #ifdef CONFIG_PM
1204 static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1205 pm_message_t state)
1206 {
1207 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1208 struct mmc_host *mmc = host->mmc;
1209 int err;
1210
1211 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1212
1213 err = mmc_suspend_host(mmc);
1214 if (err)
1215 return err;
1216
1217 return 0;
1218 }
1219
1220 static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1221 {
1222 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1223 struct mmc_host *mmc = host->mmc;
1224
1225 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1226
1227 return mmc_resume_host(mmc);
1228 }
1229 #else /* CONFIG_PM */
1230 #define rtsx_pci_sdmmc_suspend NULL
1231 #define rtsx_pci_sdmmc_resume NULL
1232 #endif /* CONFIG_PM */
1233
1234 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1235 {
1236 struct mmc_host *mmc = host->mmc;
1237 struct rtsx_pcr *pcr = host->pcr;
1238
1239 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1240
1241 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1242 mmc->caps |= MMC_CAP_UHS_SDR50;
1243 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1244 mmc->caps |= MMC_CAP_UHS_SDR104;
1245 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1246 mmc->caps |= MMC_CAP_UHS_DDR50;
1247 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1248 mmc->caps |= MMC_CAP_1_8V_DDR;
1249 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1250 mmc->caps |= MMC_CAP_8_BIT_DATA;
1251 }
1252
1253 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1254 {
1255 struct mmc_host *mmc = host->mmc;
1256
1257 mmc->f_min = 250000;
1258 mmc->f_max = 208000000;
1259 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1260 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1261 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1262 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1263 mmc->max_current_330 = 400;
1264 mmc->max_current_180 = 800;
1265 mmc->ops = &realtek_pci_sdmmc_ops;
1266
1267 init_extra_caps(host);
1268
1269 mmc->max_segs = 256;
1270 mmc->max_seg_size = 65536;
1271 mmc->max_blk_size = 512;
1272 mmc->max_blk_count = 65535;
1273 mmc->max_req_size = 524288;
1274 }
1275
1276 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1277 {
1278 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1279
1280 mmc_detect_change(host->mmc, 0);
1281 }
1282
1283 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1284 {
1285 struct mmc_host *mmc;
1286 struct realtek_pci_sdmmc *host;
1287 struct rtsx_pcr *pcr;
1288 struct pcr_handle *handle = pdev->dev.platform_data;
1289
1290 if (!handle)
1291 return -ENXIO;
1292
1293 pcr = handle->pcr;
1294 if (!pcr)
1295 return -ENXIO;
1296
1297 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1298
1299 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1300 if (!mmc)
1301 return -ENOMEM;
1302
1303 host = mmc_priv(mmc);
1304 host->pcr = pcr;
1305 host->mmc = mmc;
1306 host->pdev = pdev;
1307 host->power_state = SDMMC_POWER_OFF;
1308 platform_set_drvdata(pdev, host);
1309 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1310 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1311
1312 mutex_init(&host->host_mutex);
1313
1314 realtek_init_host(host);
1315
1316 mmc_add_host(mmc);
1317
1318 return 0;
1319 }
1320
1321 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1322 {
1323 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1324 struct rtsx_pcr *pcr;
1325 struct mmc_host *mmc;
1326
1327 if (!host)
1328 return 0;
1329
1330 pcr = host->pcr;
1331 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1332 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1333 mmc = host->mmc;
1334 host->eject = true;
1335
1336 mutex_lock(&host->host_mutex);
1337 if (host->mrq) {
1338 dev_dbg(&(pdev->dev),
1339 "%s: Controller removed during transfer\n",
1340 mmc_hostname(mmc));
1341
1342 rtsx_pci_complete_unfinished_transfer(pcr);
1343
1344 host->mrq->cmd->error = -ENOMEDIUM;
1345 if (host->mrq->stop)
1346 host->mrq->stop->error = -ENOMEDIUM;
1347 mmc_request_done(mmc, host->mrq);
1348 }
1349 mutex_unlock(&host->host_mutex);
1350
1351 mmc_remove_host(mmc);
1352 mmc_free_host(mmc);
1353
1354 dev_dbg(&(pdev->dev),
1355 ": Realtek PCI-E SDMMC controller has been removed\n");
1356
1357 return 0;
1358 }
1359
1360 static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1361 {
1362 .name = DRV_NAME_RTSX_PCI_SDMMC,
1363 }, {
1364 /* sentinel */
1365 }
1366 };
1367 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1368
1369 static struct platform_driver rtsx_pci_sdmmc_driver = {
1370 .probe = rtsx_pci_sdmmc_drv_probe,
1371 .remove = rtsx_pci_sdmmc_drv_remove,
1372 .id_table = rtsx_pci_sdmmc_ids,
1373 .suspend = rtsx_pci_sdmmc_suspend,
1374 .resume = rtsx_pci_sdmmc_resume,
1375 .driver = {
1376 .owner = THIS_MODULE,
1377 .name = DRV_NAME_RTSX_PCI_SDMMC,
1378 },
1379 };
1380 module_platform_driver(rtsx_pci_sdmmc_driver);
1381
1382 MODULE_LICENSE("GPL");
1383 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1384 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
Linux with added FPC-III support