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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / mmc / host / s3cmci.c
blob8d6794cdf899cd812e394b862c111a6c65b53dc4
1 /*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/clk.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/gpio.h>
23 #include <linux/irq.h>
24 #include <linux/io.h>
25
26 #include <mach/dma.h>
27
28 #include <linux/platform_data/mmc-s3cmci.h>
29
30 #include "s3cmci.h"
31
32 #define DRIVER_NAME "s3c-mci"
33
34 #define S3C2410_SDICON (0x00)
35 #define S3C2410_SDIPRE (0x04)
36 #define S3C2410_SDICMDARG (0x08)
37 #define S3C2410_SDICMDCON (0x0C)
38 #define S3C2410_SDICMDSTAT (0x10)
39 #define S3C2410_SDIRSP0 (0x14)
40 #define S3C2410_SDIRSP1 (0x18)
41 #define S3C2410_SDIRSP2 (0x1C)
42 #define S3C2410_SDIRSP3 (0x20)
43 #define S3C2410_SDITIMER (0x24)
44 #define S3C2410_SDIBSIZE (0x28)
45 #define S3C2410_SDIDCON (0x2C)
46 #define S3C2410_SDIDCNT (0x30)
47 #define S3C2410_SDIDSTA (0x34)
48 #define S3C2410_SDIFSTA (0x38)
49
50 #define S3C2410_SDIDATA (0x3C)
51 #define S3C2410_SDIIMSK (0x40)
52
53 #define S3C2440_SDIDATA (0x40)
54 #define S3C2440_SDIIMSK (0x3C)
55
56 #define S3C2440_SDICON_SDRESET (1 << 8)
57 #define S3C2410_SDICON_SDIOIRQ (1 << 3)
58 #define S3C2410_SDICON_FIFORESET (1 << 1)
59 #define S3C2410_SDICON_CLOCKTYPE (1 << 0)
60
61 #define S3C2410_SDICMDCON_LONGRSP (1 << 10)
62 #define S3C2410_SDICMDCON_WAITRSP (1 << 9)
63 #define S3C2410_SDICMDCON_CMDSTART (1 << 8)
64 #define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
65 #define S3C2410_SDICMDCON_INDEX (0x3f)
66
67 #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
68 #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
69 #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
70 #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
71
72 #define S3C2440_SDIDCON_DS_WORD (2 << 22)
73 #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
74 #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
75 #define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
76 #define S3C2410_SDIDCON_WIDEBUS (1 << 16)
77 #define S3C2410_SDIDCON_DMAEN (1 << 15)
78 #define S3C2410_SDIDCON_STOP (1 << 14)
79 #define S3C2440_SDIDCON_DATSTART (1 << 14)
80
81 #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
82 #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
83
84 #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
85
86 #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
87 #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
88 #define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
89 #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
90 #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
91 #define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
92 #define S3C2410_SDIDSTA_TXDATAON (1 << 1)
93 #define S3C2410_SDIDSTA_RXDATAON (1 << 0)
94
95 #define S3C2440_SDIFSTA_FIFORESET (1 << 16)
96 #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
97 #define S3C2410_SDIFSTA_TFDET (1 << 13)
98 #define S3C2410_SDIFSTA_RFDET (1 << 12)
99 #define S3C2410_SDIFSTA_COUNTMASK (0x7f)
100
101 #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
102 #define S3C2410_SDIIMSK_CMDSENT (1 << 16)
103 #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
104 #define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
105 #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
106 #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
107 #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
108 #define S3C2410_SDIIMSK_DATACRC (1 << 9)
109 #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
110 #define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
111 #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
112 #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
113 #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
114
115 enum dbg_channels {
116 dbg_err = (1 << 0),
117 dbg_debug = (1 << 1),
118 dbg_info = (1 << 2),
119 dbg_irq = (1 << 3),
120 dbg_sg = (1 << 4),
121 dbg_dma = (1 << 5),
122 dbg_pio = (1 << 6),
123 dbg_fail = (1 << 7),
124 dbg_conf = (1 << 8),
125 };
126
127 static const int dbgmap_err = dbg_fail;
128 static const int dbgmap_info = dbg_info | dbg_conf;
129 static const int dbgmap_debug = dbg_err | dbg_debug;
130
131 #define dbg(host, channels, args...) \
132 do { \
133 if (dbgmap_err & channels) \
134 dev_err(&host->pdev->dev, args); \
135 else if (dbgmap_info & channels) \
136 dev_info(&host->pdev->dev, args); \
137 else if (dbgmap_debug & channels) \
138 dev_dbg(&host->pdev->dev, args); \
139 } while (0)
140
141 static struct s3c2410_dma_client s3cmci_dma_client = {
142 .name = "s3c-mci",
143 };
144
145 static void finalize_request(struct s3cmci_host *host);
146 static void s3cmci_send_request(struct mmc_host *mmc);
147 static void s3cmci_reset(struct s3cmci_host *host);
148
149 #ifdef CONFIG_MMC_DEBUG
150
151 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
152 {
153 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
154 u32 datcon, datcnt, datsta, fsta, imask;
155
156 con = readl(host->base + S3C2410_SDICON);
157 pre = readl(host->base + S3C2410_SDIPRE);
158 cmdarg = readl(host->base + S3C2410_SDICMDARG);
159 cmdcon = readl(host->base + S3C2410_SDICMDCON);
160 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
161 r0 = readl(host->base + S3C2410_SDIRSP0);
162 r1 = readl(host->base + S3C2410_SDIRSP1);
163 r2 = readl(host->base + S3C2410_SDIRSP2);
164 r3 = readl(host->base + S3C2410_SDIRSP3);
165 timer = readl(host->base + S3C2410_SDITIMER);
166 bsize = readl(host->base + S3C2410_SDIBSIZE);
167 datcon = readl(host->base + S3C2410_SDIDCON);
168 datcnt = readl(host->base + S3C2410_SDIDCNT);
169 datsta = readl(host->base + S3C2410_SDIDSTA);
170 fsta = readl(host->base + S3C2410_SDIFSTA);
171 imask = readl(host->base + host->sdiimsk);
172
173 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
174 prefix, con, pre, timer);
175
176 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
177 prefix, cmdcon, cmdarg, cmdsta);
178
179 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
180 " DSTA:[%08x] DCNT:[%08x]\n",
181 prefix, datcon, fsta, datsta, datcnt);
182
183 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
184 " R2:[%08x] R3:[%08x]\n",
185 prefix, r0, r1, r2, r3);
186 }
187
188 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
189 int stop)
190 {
191 snprintf(host->dbgmsg_cmd, 300,
192 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
193 host->ccnt, (stop ? " (STOP)" : ""),
194 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
195
196 if (cmd->data) {
197 snprintf(host->dbgmsg_dat, 300,
198 "#%u bsize:%u blocks:%u bytes:%u",
199 host->dcnt, cmd->data->blksz,
200 cmd->data->blocks,
201 cmd->data->blocks * cmd->data->blksz);
202 } else {
203 host->dbgmsg_dat[0] = '\0';
204 }
205 }
206
207 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
208 int fail)
209 {
210 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
211
212 if (!cmd)
213 return;
214
215 if (cmd->error == 0) {
216 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
217 host->dbgmsg_cmd, cmd->resp[0]);
218 } else {
219 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
220 cmd->error, host->dbgmsg_cmd, host->status);
221 }
222
223 if (!cmd->data)
224 return;
225
226 if (cmd->data->error == 0) {
227 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
228 } else {
229 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
230 cmd->data->error, host->dbgmsg_dat,
231 readl(host->base + S3C2410_SDIDCNT));
232 }
233 }
234 #else
235 static void dbg_dumpcmd(struct s3cmci_host *host,
236 struct mmc_command *cmd, int fail) { }
237
238 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
239 int stop) { }
240
241 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
242
243 #endif /* CONFIG_MMC_DEBUG */
244
245 /**
246 * s3cmci_host_usedma - return whether the host is using dma or pio
247 * @host: The host state
248 *
249 * Return true if the host is using DMA to transfer data, else false
250 * to use PIO mode. Will return static data depending on the driver
251 * configuration.
252 */
253 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
254 {
255 #ifdef CONFIG_MMC_S3C_PIO
256 return false;
257 #elif defined(CONFIG_MMC_S3C_DMA)
258 return true;
259 #else
260 return host->dodma;
261 #endif
262 }
263
264 /**
265 * s3cmci_host_canpio - return true if host has pio code available
266 *
267 * Return true if the driver has been compiled with the PIO support code
268 * available.
269 */
270 static inline bool s3cmci_host_canpio(void)
271 {
272 #ifdef CONFIG_MMC_S3C_PIO
273 return true;
274 #else
275 return false;
276 #endif
277 }
278
279 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
280 {
281 u32 newmask;
282
283 newmask = readl(host->base + host->sdiimsk);
284 newmask |= imask;
285
286 writel(newmask, host->base + host->sdiimsk);
287
288 return newmask;
289 }
290
291 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
292 {
293 u32 newmask;
294
295 newmask = readl(host->base + host->sdiimsk);
296 newmask &= ~imask;
297
298 writel(newmask, host->base + host->sdiimsk);
299
300 return newmask;
301 }
302
303 static inline void clear_imask(struct s3cmci_host *host)
304 {
305 u32 mask = readl(host->base + host->sdiimsk);
306
307 /* preserve the SDIO IRQ mask state */
308 mask &= S3C2410_SDIIMSK_SDIOIRQ;
309 writel(mask, host->base + host->sdiimsk);
310 }
311
312 /**
313 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
314 * @host: The host to check.
315 *
316 * Test to see if the SDIO interrupt is being signalled in case the
317 * controller has failed to re-detect a card interrupt. Read GPE8 and
318 * see if it is low and if so, signal a SDIO interrupt.
319 *
320 * This is currently called if a request is finished (we assume that the
321 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
322 * already being indicated.
323 */
324 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
325 {
326 if (host->sdio_irqen) {
327 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
328 pr_debug("%s: signalling irq\n", __func__);
329 mmc_signal_sdio_irq(host->mmc);
330 }
331 }
332 }
333
334 static inline int get_data_buffer(struct s3cmci_host *host,
335 u32 *bytes, u32 **pointer)
336 {
337 struct scatterlist *sg;
338
339 if (host->pio_active == XFER_NONE)
340 return -EINVAL;
341
342 if ((!host->mrq) || (!host->mrq->data))
343 return -EINVAL;
344
345 if (host->pio_sgptr >= host->mrq->data->sg_len) {
346 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
347 host->pio_sgptr, host->mrq->data->sg_len);
348 return -EBUSY;
349 }
350 sg = &host->mrq->data->sg[host->pio_sgptr];
351
352 *bytes = sg->length;
353 *pointer = sg_virt(sg);
354
355 host->pio_sgptr++;
356
357 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
358 host->pio_sgptr, host->mrq->data->sg_len);
359
360 return 0;
361 }
362
363 static inline u32 fifo_count(struct s3cmci_host *host)
364 {
365 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
366
367 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
368 return fifostat;
369 }
370
371 static inline u32 fifo_free(struct s3cmci_host *host)
372 {
373 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
374
375 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
376 return 63 - fifostat;
377 }
378
379 /**
380 * s3cmci_enable_irq - enable IRQ, after having disabled it.
381 * @host: The device state.
382 * @more: True if more IRQs are expected from transfer.
383 *
384 * Enable the main IRQ if needed after it has been disabled.
385 *
386 * The IRQ can be one of the following states:
387 * - disabled during IDLE
388 * - disabled whilst processing data
389 * - enabled during transfer
390 * - enabled whilst awaiting SDIO interrupt detection
391 */
392 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
393 {
394 unsigned long flags;
395 bool enable = false;
396
397 local_irq_save(flags);
398
399 host->irq_enabled = more;
400 host->irq_disabled = false;
401
402 enable = more | host->sdio_irqen;
403
404 if (host->irq_state != enable) {
405 host->irq_state = enable;
406
407 if (enable)
408 enable_irq(host->irq);
409 else
410 disable_irq(host->irq);
411 }
412
413 local_irq_restore(flags);
414 }
415
416 /**
417 *
418 */
419 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
420 {
421 unsigned long flags;
422
423 local_irq_save(flags);
424
425 /* pr_debug("%s: transfer %d\n", __func__, transfer); */
426
427 host->irq_disabled = transfer;
428
429 if (transfer && host->irq_state) {
430 host->irq_state = false;
431 disable_irq(host->irq);
432 }
433
434 local_irq_restore(flags);
435 }
436
437 static void do_pio_read(struct s3cmci_host *host)
438 {
439 int res;
440 u32 fifo;
441 u32 *ptr;
442 u32 fifo_words;
443 void __iomem *from_ptr;
444
445 /* write real prescaler to host, it might be set slow to fix */
446 writel(host->prescaler, host->base + S3C2410_SDIPRE);
447
448 from_ptr = host->base + host->sdidata;
449
450 while ((fifo = fifo_count(host))) {
451 if (!host->pio_bytes) {
452 res = get_data_buffer(host, &host->pio_bytes,
453 &host->pio_ptr);
454 if (res) {
455 host->pio_active = XFER_NONE;
456 host->complete_what = COMPLETION_FINALIZE;
457
458 dbg(host, dbg_pio, "pio_read(): "
459 "complete (no more data).\n");
460 return;
461 }
462
463 dbg(host, dbg_pio,
464 "pio_read(): new target: [%i]@[%p]\n",
465 host->pio_bytes, host->pio_ptr);
466 }
467
468 dbg(host, dbg_pio,
469 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
470 fifo, host->pio_bytes,
471 readl(host->base + S3C2410_SDIDCNT));
472
473 /* If we have reached the end of the block, we can
474 * read a word and get 1 to 3 bytes. If we in the
475 * middle of the block, we have to read full words,
476 * otherwise we will write garbage, so round down to
477 * an even multiple of 4. */
478 if (fifo >= host->pio_bytes)
479 fifo = host->pio_bytes;
480 else
481 fifo -= fifo & 3;
482
483 host->pio_bytes -= fifo;
484 host->pio_count += fifo;
485
486 fifo_words = fifo >> 2;
487 ptr = host->pio_ptr;
488 while (fifo_words--)
489 *ptr++ = readl(from_ptr);
490 host->pio_ptr = ptr;
491
492 if (fifo & 3) {
493 u32 n = fifo & 3;
494 u32 data = readl(from_ptr);
495 u8 *p = (u8 *)host->pio_ptr;
496
497 while (n--) {
498 *p++ = data;
499 data >>= 8;
500 }
501 }
502 }
503
504 if (!host->pio_bytes) {
505 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
506 if (res) {
507 dbg(host, dbg_pio,
508 "pio_read(): complete (no more buffers).\n");
509 host->pio_active = XFER_NONE;
510 host->complete_what = COMPLETION_FINALIZE;
511
512 return;
513 }
514 }
515
516 enable_imask(host,
517 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
518 }
519
520 static void do_pio_write(struct s3cmci_host *host)
521 {
522 void __iomem *to_ptr;
523 int res;
524 u32 fifo;
525 u32 *ptr;
526
527 to_ptr = host->base + host->sdidata;
528
529 while ((fifo = fifo_free(host)) > 3) {
530 if (!host->pio_bytes) {
531 res = get_data_buffer(host, &host->pio_bytes,
532 &host->pio_ptr);
533 if (res) {
534 dbg(host, dbg_pio,
535 "pio_write(): complete (no more data).\n");
536 host->pio_active = XFER_NONE;
537
538 return;
539 }
540
541 dbg(host, dbg_pio,
542 "pio_write(): new source: [%i]@[%p]\n",
543 host->pio_bytes, host->pio_ptr);
544
545 }
546
547 /* If we have reached the end of the block, we have to
548 * write exactly the remaining number of bytes. If we
549 * in the middle of the block, we have to write full
550 * words, so round down to an even multiple of 4. */
551 if (fifo >= host->pio_bytes)
552 fifo = host->pio_bytes;
553 else
554 fifo -= fifo & 3;
555
556 host->pio_bytes -= fifo;
557 host->pio_count += fifo;
558
559 fifo = (fifo + 3) >> 2;
560 ptr = host->pio_ptr;
561 while (fifo--)
562 writel(*ptr++, to_ptr);
563 host->pio_ptr = ptr;
564 }
565
566 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
567 }
568
569 static void pio_tasklet(unsigned long data)
570 {
571 struct s3cmci_host *host = (struct s3cmci_host *) data;
572
573 s3cmci_disable_irq(host, true);
574
575 if (host->pio_active == XFER_WRITE)
576 do_pio_write(host);
577
578 if (host->pio_active == XFER_READ)
579 do_pio_read(host);
580
581 if (host->complete_what == COMPLETION_FINALIZE) {
582 clear_imask(host);
583 if (host->pio_active != XFER_NONE) {
584 dbg(host, dbg_err, "unfinished %s "
585 "- pio_count:[%u] pio_bytes:[%u]\n",
586 (host->pio_active == XFER_READ) ? "read" : "write",
587 host->pio_count, host->pio_bytes);
588
589 if (host->mrq->data)
590 host->mrq->data->error = -EINVAL;
591 }
592
593 s3cmci_enable_irq(host, false);
594 finalize_request(host);
595 } else
596 s3cmci_enable_irq(host, true);
597 }
598
599 /*
600 * ISR for SDI Interface IRQ
601 * Communication between driver and ISR works as follows:
602 * host->mrq points to current request
603 * host->complete_what Indicates when the request is considered done
604 * COMPLETION_CMDSENT when the command was sent
605 * COMPLETION_RSPFIN when a response was received
606 * COMPLETION_XFERFINISH when the data transfer is finished
607 * COMPLETION_XFERFINISH_RSPFIN both of the above.
608 * host->complete_request is the completion-object the driver waits for
609 *
610 * 1) Driver sets up host->mrq and host->complete_what
611 * 2) Driver prepares the transfer
612 * 3) Driver enables interrupts
613 * 4) Driver starts transfer
614 * 5) Driver waits for host->complete_rquest
615 * 6) ISR checks for request status (errors and success)
616 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
617 * 7) ISR completes host->complete_request
618 * 8) ISR disables interrupts
619 * 9) Driver wakes up and takes care of the request
620 *
621 * Note: "->error"-fields are expected to be set to 0 before the request
622 * was issued by mmc.c - therefore they are only set, when an error
623 * contition comes up
624 */
625
626 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
627 {
628 struct s3cmci_host *host = dev_id;
629 struct mmc_command *cmd;
630 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
631 u32 mci_cclear = 0, mci_dclear;
632 unsigned long iflags;
633
634 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
635 mci_imsk = readl(host->base + host->sdiimsk);
636
637 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
638 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
639 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
640 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
641
642 mmc_signal_sdio_irq(host->mmc);
643 return IRQ_HANDLED;
644 }
645 }
646
647 spin_lock_irqsave(&host->complete_lock, iflags);
648
649 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
650 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
651 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
652 mci_dclear = 0;
653
654 if ((host->complete_what == COMPLETION_NONE) ||
655 (host->complete_what == COMPLETION_FINALIZE)) {
656 host->status = "nothing to complete";
657 clear_imask(host);
658 goto irq_out;
659 }
660
661 if (!host->mrq) {
662 host->status = "no active mrq";
663 clear_imask(host);
664 goto irq_out;
665 }
666
667 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
668
669 if (!cmd) {
670 host->status = "no active cmd";
671 clear_imask(host);
672 goto irq_out;
673 }
674
675 if (!s3cmci_host_usedma(host)) {
676 if ((host->pio_active == XFER_WRITE) &&
677 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
678
679 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
680 tasklet_schedule(&host->pio_tasklet);
681 host->status = "pio tx";
682 }
683
684 if ((host->pio_active == XFER_READ) &&
685 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
686
687 disable_imask(host,
688 S3C2410_SDIIMSK_RXFIFOHALF |
689 S3C2410_SDIIMSK_RXFIFOLAST);
690
691 tasklet_schedule(&host->pio_tasklet);
692 host->status = "pio rx";
693 }
694 }
695
696 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
697 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
698 cmd->error = -ETIMEDOUT;
699 host->status = "error: command timeout";
700 goto fail_transfer;
701 }
702
703 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
704 if (host->complete_what == COMPLETION_CMDSENT) {
705 host->status = "ok: command sent";
706 goto close_transfer;
707 }
708
709 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
710 }
711
712 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
713 if (cmd->flags & MMC_RSP_CRC) {
714 if (host->mrq->cmd->flags & MMC_RSP_136) {
715 dbg(host, dbg_irq,
716 "fixup: ignore CRC fail with long rsp\n");
717 } else {
718 /* note, we used to fail the transfer
719 * here, but it seems that this is just
720 * the hardware getting it wrong.
721 *
722 * cmd->error = -EILSEQ;
723 * host->status = "error: bad command crc";
724 * goto fail_transfer;
725 */
726 }
727 }
728
729 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
730 }
731
732 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
733 if (host->complete_what == COMPLETION_RSPFIN) {
734 host->status = "ok: command response received";
735 goto close_transfer;
736 }
737
738 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
739 host->complete_what = COMPLETION_XFERFINISH;
740
741 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
742 }
743
744 /* errors handled after this point are only relevant
745 when a data transfer is in progress */
746
747 if (!cmd->data)
748 goto clear_status_bits;
749
750 /* Check for FIFO failure */
751 if (host->is2440) {
752 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
753 dbg(host, dbg_err, "FIFO failure\n");
754 host->mrq->data->error = -EILSEQ;
755 host->status = "error: 2440 fifo failure";
756 goto fail_transfer;
757 }
758 } else {
759 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
760 dbg(host, dbg_err, "FIFO failure\n");
761 cmd->data->error = -EILSEQ;
762 host->status = "error: fifo failure";
763 goto fail_transfer;
764 }
765 }
766
767 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
768 dbg(host, dbg_err, "bad data crc (outgoing)\n");
769 cmd->data->error = -EILSEQ;
770 host->status = "error: bad data crc (outgoing)";
771 goto fail_transfer;
772 }
773
774 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
775 dbg(host, dbg_err, "bad data crc (incoming)\n");
776 cmd->data->error = -EILSEQ;
777 host->status = "error: bad data crc (incoming)";
778 goto fail_transfer;
779 }
780
781 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
782 dbg(host, dbg_err, "data timeout\n");
783 cmd->data->error = -ETIMEDOUT;
784 host->status = "error: data timeout";
785 goto fail_transfer;
786 }
787
788 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
789 if (host->complete_what == COMPLETION_XFERFINISH) {
790 host->status = "ok: data transfer completed";
791 goto close_transfer;
792 }
793
794 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
795 host->complete_what = COMPLETION_RSPFIN;
796
797 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
798 }
799
800 clear_status_bits:
801 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
802 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
803
804 goto irq_out;
805
806 fail_transfer:
807 host->pio_active = XFER_NONE;
808
809 close_transfer:
810 host->complete_what = COMPLETION_FINALIZE;
811
812 clear_imask(host);
813 tasklet_schedule(&host->pio_tasklet);
814
815 goto irq_out;
816
817 irq_out:
818 dbg(host, dbg_irq,
819 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
820 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
821
822 spin_unlock_irqrestore(&host->complete_lock, iflags);
823 return IRQ_HANDLED;
824
825 }
826
827 /*
828 * ISR for the CardDetect Pin
829 */
830
831 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
832 {
833 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
834
835 dbg(host, dbg_irq, "card detect\n");
836
837 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
838
839 return IRQ_HANDLED;
840 }
841
842 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
843 void *buf_id, int size,
844 enum s3c2410_dma_buffresult result)
845 {
846 struct s3cmci_host *host = buf_id;
847 unsigned long iflags;
848 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
849
850 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
851 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
852 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
853 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
854
855 BUG_ON(!host->mrq);
856 BUG_ON(!host->mrq->data);
857 BUG_ON(!host->dmatogo);
858
859 spin_lock_irqsave(&host->complete_lock, iflags);
860
861 if (result != S3C2410_RES_OK) {
862 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
863 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
864 mci_csta, mci_dsta, mci_fsta,
865 mci_dcnt, result, host->dmatogo);
866
867 goto fail_request;
868 }
869
870 host->dmatogo--;
871 if (host->dmatogo) {
872 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
873 "DCNT:[%08x] toGo:%u\n",
874 size, mci_dsta, mci_dcnt, host->dmatogo);
875
876 goto out;
877 }
878
879 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
880 size, mci_dsta, mci_dcnt);
881
882 host->dma_complete = 1;
883 host->complete_what = COMPLETION_FINALIZE;
884
885 out:
886 tasklet_schedule(&host->pio_tasklet);
887 spin_unlock_irqrestore(&host->complete_lock, iflags);
888 return;
889
890 fail_request:
891 host->mrq->data->error = -EINVAL;
892 host->complete_what = COMPLETION_FINALIZE;
893 clear_imask(host);
894
895 goto out;
896 }
897
898 static void finalize_request(struct s3cmci_host *host)
899 {
900 struct mmc_request *mrq = host->mrq;
901 struct mmc_command *cmd;
902 int debug_as_failure = 0;
903
904 if (host->complete_what != COMPLETION_FINALIZE)
905 return;
906
907 if (!mrq)
908 return;
909 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
910
911 if (cmd->data && (cmd->error == 0) &&
912 (cmd->data->error == 0)) {
913 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
914 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
915 host->dma_complete);
916 return;
917 }
918 }
919
920 /* Read response from controller. */
921 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
922 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
923 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
924 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
925
926 writel(host->prescaler, host->base + S3C2410_SDIPRE);
927
928 if (cmd->error)
929 debug_as_failure = 1;
930
931 if (cmd->data && cmd->data->error)
932 debug_as_failure = 1;
933
934 dbg_dumpcmd(host, cmd, debug_as_failure);
935
936 /* Cleanup controller */
937 writel(0, host->base + S3C2410_SDICMDARG);
938 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
939 writel(0, host->base + S3C2410_SDICMDCON);
940 clear_imask(host);
941
942 if (cmd->data && cmd->error)
943 cmd->data->error = cmd->error;
944
945 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
946 host->cmd_is_stop = 1;
947 s3cmci_send_request(host->mmc);
948 return;
949 }
950
951 /* If we have no data transfer we are finished here */
952 if (!mrq->data)
953 goto request_done;
954
955 /* Calculate the amout of bytes transfer if there was no error */
956 if (mrq->data->error == 0) {
957 mrq->data->bytes_xfered =
958 (mrq->data->blocks * mrq->data->blksz);
959 } else {
960 mrq->data->bytes_xfered = 0;
961 }
962
963 /* If we had an error while transferring data we flush the
964 * DMA channel and the fifo to clear out any garbage. */
965 if (mrq->data->error != 0) {
966 if (s3cmci_host_usedma(host))
967 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
968
969 if (host->is2440) {
970 /* Clear failure register and reset fifo. */
971 writel(S3C2440_SDIFSTA_FIFORESET |
972 S3C2440_SDIFSTA_FIFOFAIL,
973 host->base + S3C2410_SDIFSTA);
974 } else {
975 u32 mci_con;
976
977 /* reset fifo */
978 mci_con = readl(host->base + S3C2410_SDICON);
979 mci_con |= S3C2410_SDICON_FIFORESET;
980
981 writel(mci_con, host->base + S3C2410_SDICON);
982 }
983 }
984
985 request_done:
986 host->complete_what = COMPLETION_NONE;
987 host->mrq = NULL;
988
989 s3cmci_check_sdio_irq(host);
990 mmc_request_done(host->mmc, mrq);
991 }
992
993 static void s3cmci_dma_setup(struct s3cmci_host *host,
994 enum dma_data_direction source)
995 {
996 static enum dma_data_direction last_source = -1;
997 static int setup_ok;
998
999 if (last_source == source)
1000 return;
1001
1002 last_source = source;
1003
1004 s3c2410_dma_devconfig(host->dma, source,
1005 host->mem->start + host->sdidata);
1006
1007 if (!setup_ok) {
1008 s3c2410_dma_config(host->dma, 4);
1009 s3c2410_dma_set_buffdone_fn(host->dma,
1010 s3cmci_dma_done_callback);
1011 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
1012 setup_ok = 1;
1013 }
1014 }
1015
1016 static void s3cmci_send_command(struct s3cmci_host *host,
1017 struct mmc_command *cmd)
1018 {
1019 u32 ccon, imsk;
1020
1021 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
1022 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
1023 S3C2410_SDIIMSK_RESPONSECRC;
1024
1025 enable_imask(host, imsk);
1026
1027 if (cmd->data)
1028 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
1029 else if (cmd->flags & MMC_RSP_PRESENT)
1030 host->complete_what = COMPLETION_RSPFIN;
1031 else
1032 host->complete_what = COMPLETION_CMDSENT;
1033
1034 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
1035
1036 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
1037 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
1038
1039 if (cmd->flags & MMC_RSP_PRESENT)
1040 ccon |= S3C2410_SDICMDCON_WAITRSP;
1041
1042 if (cmd->flags & MMC_RSP_136)
1043 ccon |= S3C2410_SDICMDCON_LONGRSP;
1044
1045 writel(ccon, host->base + S3C2410_SDICMDCON);
1046 }
1047
1048 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
1049 {
1050 u32 dcon, imsk, stoptries = 3;
1051
1052 /* write DCON register */
1053
1054 if (!data) {
1055 writel(0, host->base + S3C2410_SDIDCON);
1056 return 0;
1057 }
1058
1059 if ((data->blksz & 3) != 0) {
1060 /* We cannot deal with unaligned blocks with more than
1061 * one block being transferred. */
1062
1063 if (data->blocks > 1) {
1064 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
1065 return -EINVAL;
1066 }
1067 }
1068
1069 while (readl(host->base + S3C2410_SDIDSTA) &
1070 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
1071
1072 dbg(host, dbg_err,
1073 "mci_setup_data() transfer stillin progress.\n");
1074
1075 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1076 s3cmci_reset(host);
1077
1078 if ((stoptries--) == 0) {
1079 dbg_dumpregs(host, "DRF");
1080 return -EINVAL;
1081 }
1082 }
1083
1084 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1085
1086 if (s3cmci_host_usedma(host))
1087 dcon |= S3C2410_SDIDCON_DMAEN;
1088
1089 if (host->bus_width == MMC_BUS_WIDTH_4)
1090 dcon |= S3C2410_SDIDCON_WIDEBUS;
1091
1092 if (!(data->flags & MMC_DATA_STREAM))
1093 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1094
1095 if (data->flags & MMC_DATA_WRITE) {
1096 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1097 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1098 }
1099
1100 if (data->flags & MMC_DATA_READ) {
1101 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1102 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1103 }
1104
1105 if (host->is2440) {
1106 dcon |= S3C2440_SDIDCON_DS_WORD;
1107 dcon |= S3C2440_SDIDCON_DATSTART;
1108 }
1109
1110 writel(dcon, host->base + S3C2410_SDIDCON);
1111
1112 /* write BSIZE register */
1113
1114 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1115
1116 /* add to IMASK register */
1117 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1118 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1119
1120 enable_imask(host, imsk);
1121
1122 /* write TIMER register */
1123
1124 if (host->is2440) {
1125 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1126 } else {
1127 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1128
1129 /* FIX: set slow clock to prevent timeouts on read */
1130 if (data->flags & MMC_DATA_READ)
1131 writel(0xFF, host->base + S3C2410_SDIPRE);
1132 }
1133
1134 return 0;
1135 }
1136
1137 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1138
1139 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1140 {
1141 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1142
1143 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1144
1145 host->pio_sgptr = 0;
1146 host->pio_bytes = 0;
1147 host->pio_count = 0;
1148 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1149
1150 if (rw) {
1151 do_pio_write(host);
1152 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1153 } else {
1154 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1155 | S3C2410_SDIIMSK_RXFIFOLAST);
1156 }
1157
1158 return 0;
1159 }
1160
1161 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1162 {
1163 int dma_len, i;
1164 int rw = data->flags & MMC_DATA_WRITE;
1165
1166 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1167
1168 s3cmci_dma_setup(host, rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1169 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1170
1171 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1172 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1173
1174 if (dma_len == 0)
1175 return -ENOMEM;
1176
1177 host->dma_complete = 0;
1178 host->dmatogo = dma_len;
1179
1180 for (i = 0; i < dma_len; i++) {
1181 int res;
1182
1183 dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1184 sg_dma_address(&data->sg[i]),
1185 sg_dma_len(&data->sg[i]));
1186
1187 res = s3c2410_dma_enqueue(host->dma, host,
1188 sg_dma_address(&data->sg[i]),
1189 sg_dma_len(&data->sg[i]));
1190
1191 if (res) {
1192 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1193 return -EBUSY;
1194 }
1195 }
1196
1197 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
1198
1199 return 0;
1200 }
1201
1202 static void s3cmci_send_request(struct mmc_host *mmc)
1203 {
1204 struct s3cmci_host *host = mmc_priv(mmc);
1205 struct mmc_request *mrq = host->mrq;
1206 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1207
1208 host->ccnt++;
1209 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1210
1211 /* Clear command, data and fifo status registers
1212 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1213 */
1214 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1215 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1216 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1217
1218 if (cmd->data) {
1219 int res = s3cmci_setup_data(host, cmd->data);
1220
1221 host->dcnt++;
1222
1223 if (res) {
1224 dbg(host, dbg_err, "setup data error %d\n", res);
1225 cmd->error = res;
1226 cmd->data->error = res;
1227
1228 mmc_request_done(mmc, mrq);
1229 return;
1230 }
1231
1232 if (s3cmci_host_usedma(host))
1233 res = s3cmci_prepare_dma(host, cmd->data);
1234 else
1235 res = s3cmci_prepare_pio(host, cmd->data);
1236
1237 if (res) {
1238 dbg(host, dbg_err, "data prepare error %d\n", res);
1239 cmd->error = res;
1240 cmd->data->error = res;
1241
1242 mmc_request_done(mmc, mrq);
1243 return;
1244 }
1245 }
1246
1247 /* Send command */
1248 s3cmci_send_command(host, cmd);
1249
1250 /* Enable Interrupt */
1251 s3cmci_enable_irq(host, true);
1252 }
1253
1254 static int s3cmci_card_present(struct mmc_host *mmc)
1255 {
1256 struct s3cmci_host *host = mmc_priv(mmc);
1257 struct s3c24xx_mci_pdata *pdata = host->pdata;
1258 int ret;
1259
1260 if (pdata->no_detect)
1261 return -ENOSYS;
1262
1263 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1264 return ret ^ pdata->detect_invert;
1265 }
1266
1267 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1268 {
1269 struct s3cmci_host *host = mmc_priv(mmc);
1270
1271 host->status = "mmc request";
1272 host->cmd_is_stop = 0;
1273 host->mrq = mrq;
1274
1275 if (s3cmci_card_present(mmc) == 0) {
1276 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1277 host->mrq->cmd->error = -ENOMEDIUM;
1278 mmc_request_done(mmc, mrq);
1279 } else
1280 s3cmci_send_request(mmc);
1281 }
1282
1283 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1284 {
1285 u32 mci_psc;
1286
1287 /* Set clock */
1288 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1289 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1290
1291 if (host->real_rate <= ios->clock)
1292 break;
1293 }
1294
1295 if (mci_psc > 255)
1296 mci_psc = 255;
1297
1298 host->prescaler = mci_psc;
1299 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1300
1301 /* If requested clock is 0, real_rate will be 0, too */
1302 if (ios->clock == 0)
1303 host->real_rate = 0;
1304 }
1305
1306 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1307 {
1308 struct s3cmci_host *host = mmc_priv(mmc);
1309 u32 mci_con;
1310
1311 /* Set the power state */
1312
1313 mci_con = readl(host->base + S3C2410_SDICON);
1314
1315 switch (ios->power_mode) {
1316 case MMC_POWER_ON:
1317 case MMC_POWER_UP:
1318 /* Configure GPE5...GPE10 pins in SD mode */
1319 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1320 S3C_GPIO_PULL_NONE);
1321
1322 if (host->pdata->set_power)
1323 host->pdata->set_power(ios->power_mode, ios->vdd);
1324
1325 if (!host->is2440)
1326 mci_con |= S3C2410_SDICON_FIFORESET;
1327
1328 break;
1329
1330 case MMC_POWER_OFF:
1331 default:
1332 gpio_direction_output(S3C2410_GPE(5), 0);
1333
1334 if (host->is2440)
1335 mci_con |= S3C2440_SDICON_SDRESET;
1336
1337 if (host->pdata->set_power)
1338 host->pdata->set_power(ios->power_mode, ios->vdd);
1339
1340 break;
1341 }
1342
1343 s3cmci_set_clk(host, ios);
1344
1345 /* Set CLOCK_ENABLE */
1346 if (ios->clock)
1347 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1348 else
1349 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1350
1351 writel(mci_con, host->base + S3C2410_SDICON);
1352
1353 if ((ios->power_mode == MMC_POWER_ON) ||
1354 (ios->power_mode == MMC_POWER_UP)) {
1355 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1356 host->real_rate/1000, ios->clock/1000);
1357 } else {
1358 dbg(host, dbg_conf, "powered down.\n");
1359 }
1360
1361 host->bus_width = ios->bus_width;
1362 }
1363
1364 static void s3cmci_reset(struct s3cmci_host *host)
1365 {
1366 u32 con = readl(host->base + S3C2410_SDICON);
1367
1368 con |= S3C2440_SDICON_SDRESET;
1369 writel(con, host->base + S3C2410_SDICON);
1370 }
1371
1372 static int s3cmci_get_ro(struct mmc_host *mmc)
1373 {
1374 struct s3cmci_host *host = mmc_priv(mmc);
1375 struct s3c24xx_mci_pdata *pdata = host->pdata;
1376 int ret;
1377
1378 if (pdata->no_wprotect)
1379 return 0;
1380
1381 ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1382 ret ^= pdata->wprotect_invert;
1383
1384 return ret;
1385 }
1386
1387 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1388 {
1389 struct s3cmci_host *host = mmc_priv(mmc);
1390 unsigned long flags;
1391 u32 con;
1392
1393 local_irq_save(flags);
1394
1395 con = readl(host->base + S3C2410_SDICON);
1396 host->sdio_irqen = enable;
1397
1398 if (enable == host->sdio_irqen)
1399 goto same_state;
1400
1401 if (enable) {
1402 con |= S3C2410_SDICON_SDIOIRQ;
1403 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1404
1405 if (!host->irq_state && !host->irq_disabled) {
1406 host->irq_state = true;
1407 enable_irq(host->irq);
1408 }
1409 } else {
1410 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1411 con &= ~S3C2410_SDICON_SDIOIRQ;
1412
1413 if (!host->irq_enabled && host->irq_state) {
1414 disable_irq_nosync(host->irq);
1415 host->irq_state = false;
1416 }
1417 }
1418
1419 writel(con, host->base + S3C2410_SDICON);
1420
1421 same_state:
1422 local_irq_restore(flags);
1423
1424 s3cmci_check_sdio_irq(host);
1425 }
1426
1427 static struct mmc_host_ops s3cmci_ops = {
1428 .request = s3cmci_request,
1429 .set_ios = s3cmci_set_ios,
1430 .get_ro = s3cmci_get_ro,
1431 .get_cd = s3cmci_card_present,
1432 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1433 };
1434
1435 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1436 /* This is currently here to avoid a number of if (host->pdata)
1437 * checks. Any zero fields to ensure reasonable defaults are picked. */
1438 .no_wprotect = 1,
1439 .no_detect = 1,
1440 };
1441
1442 #ifdef CONFIG_CPU_FREQ
1443
1444 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1445 unsigned long val, void *data)
1446 {
1447 struct s3cmci_host *host;
1448 struct mmc_host *mmc;
1449 unsigned long newclk;
1450 unsigned long flags;
1451
1452 host = container_of(nb, struct s3cmci_host, freq_transition);
1453 newclk = clk_get_rate(host->clk);
1454 mmc = host->mmc;
1455
1456 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1457 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1458 spin_lock_irqsave(&mmc->lock, flags);
1459
1460 host->clk_rate = newclk;
1461
1462 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1463 mmc->ios.clock != 0)
1464 s3cmci_set_clk(host, &mmc->ios);
1465
1466 spin_unlock_irqrestore(&mmc->lock, flags);
1467 }
1468
1469 return 0;
1470 }
1471
1472 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1473 {
1474 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1475
1476 return cpufreq_register_notifier(&host->freq_transition,
1477 CPUFREQ_TRANSITION_NOTIFIER);
1478 }
1479
1480 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1481 {
1482 cpufreq_unregister_notifier(&host->freq_transition,
1483 CPUFREQ_TRANSITION_NOTIFIER);
1484 }
1485
1486 #else
1487 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1488 {
1489 return 0;
1490 }
1491
1492 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1493 {
1494 }
1495 #endif
1496
1497
1498 #ifdef CONFIG_DEBUG_FS
1499
1500 static int s3cmci_state_show(struct seq_file *seq, void *v)
1501 {
1502 struct s3cmci_host *host = seq->private;
1503
1504 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1505 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1506 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1507 seq_printf(seq, "is2440 = %d\n", host->is2440);
1508 seq_printf(seq, "IRQ = %d\n", host->irq);
1509 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1510 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1511 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1512 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1513 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1514 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1515 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1516
1517 return 0;
1518 }
1519
1520 static int s3cmci_state_open(struct inode *inode, struct file *file)
1521 {
1522 return single_open(file, s3cmci_state_show, inode->i_private);
1523 }
1524
1525 static const struct file_operations s3cmci_fops_state = {
1526 .owner = THIS_MODULE,
1527 .open = s3cmci_state_open,
1528 .read = seq_read,
1529 .llseek = seq_lseek,
1530 .release = single_release,
1531 };
1532
1533 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1534
1535 struct s3cmci_reg {
1536 unsigned short addr;
1537 unsigned char *name;
1538 } debug_regs[] = {
1539 DBG_REG(CON),
1540 DBG_REG(PRE),
1541 DBG_REG(CMDARG),
1542 DBG_REG(CMDCON),
1543 DBG_REG(CMDSTAT),
1544 DBG_REG(RSP0),
1545 DBG_REG(RSP1),
1546 DBG_REG(RSP2),
1547 DBG_REG(RSP3),
1548 DBG_REG(TIMER),
1549 DBG_REG(BSIZE),
1550 DBG_REG(DCON),
1551 DBG_REG(DCNT),
1552 DBG_REG(DSTA),
1553 DBG_REG(FSTA),
1554 {}
1555 };
1556
1557 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1558 {
1559 struct s3cmci_host *host = seq->private;
1560 struct s3cmci_reg *rptr = debug_regs;
1561
1562 for (; rptr->name; rptr++)
1563 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1564 readl(host->base + rptr->addr));
1565
1566 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1567
1568 return 0;
1569 }
1570
1571 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1572 {
1573 return single_open(file, s3cmci_regs_show, inode->i_private);
1574 }
1575
1576 static const struct file_operations s3cmci_fops_regs = {
1577 .owner = THIS_MODULE,
1578 .open = s3cmci_regs_open,
1579 .read = seq_read,
1580 .llseek = seq_lseek,
1581 .release = single_release,
1582 };
1583
1584 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1585 {
1586 struct device *dev = &host->pdev->dev;
1587
1588 host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1589 if (IS_ERR(host->debug_root)) {
1590 dev_err(dev, "failed to create debugfs root\n");
1591 return;
1592 }
1593
1594 host->debug_state = debugfs_create_file("state", 0444,
1595 host->debug_root, host,
1596 &s3cmci_fops_state);
1597
1598 if (IS_ERR(host->debug_state))
1599 dev_err(dev, "failed to create debug state file\n");
1600
1601 host->debug_regs = debugfs_create_file("regs", 0444,
1602 host->debug_root, host,
1603 &s3cmci_fops_regs);
1604
1605 if (IS_ERR(host->debug_regs))
1606 dev_err(dev, "failed to create debug regs file\n");
1607 }
1608
1609 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1610 {
1611 debugfs_remove(host->debug_regs);
1612 debugfs_remove(host->debug_state);
1613 debugfs_remove(host->debug_root);
1614 }
1615
1616 #else
1617 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1618 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1619
1620 #endif /* CONFIG_DEBUG_FS */
1621
1622 static int s3cmci_probe(struct platform_device *pdev)
1623 {
1624 struct s3cmci_host *host;
1625 struct mmc_host *mmc;
1626 int ret;
1627 int is2440;
1628 int i;
1629
1630 is2440 = platform_get_device_id(pdev)->driver_data;
1631
1632 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1633 if (!mmc) {
1634 ret = -ENOMEM;
1635 goto probe_out;
1636 }
1637
1638 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1639 ret = gpio_request(i, dev_name(&pdev->dev));
1640 if (ret) {
1641 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1642
1643 for (i--; i >= S3C2410_GPE(5); i--)
1644 gpio_free(i);
1645
1646 goto probe_free_host;
1647 }
1648 }
1649
1650 host = mmc_priv(mmc);
1651 host->mmc = mmc;
1652 host->pdev = pdev;
1653 host->is2440 = is2440;
1654
1655 host->pdata = pdev->dev.platform_data;
1656 if (!host->pdata) {
1657 pdev->dev.platform_data = &s3cmci_def_pdata;
1658 host->pdata = &s3cmci_def_pdata;
1659 }
1660
1661 spin_lock_init(&host->complete_lock);
1662 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1663
1664 if (is2440) {
1665 host->sdiimsk = S3C2440_SDIIMSK;
1666 host->sdidata = S3C2440_SDIDATA;
1667 host->clk_div = 1;
1668 } else {
1669 host->sdiimsk = S3C2410_SDIIMSK;
1670 host->sdidata = S3C2410_SDIDATA;
1671 host->clk_div = 2;
1672 }
1673
1674 host->complete_what = COMPLETION_NONE;
1675 host->pio_active = XFER_NONE;
1676
1677 #ifdef CONFIG_MMC_S3C_PIODMA
1678 host->dodma = host->pdata->use_dma;
1679 #endif
1680
1681 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1682 if (!host->mem) {
1683 dev_err(&pdev->dev,
1684 "failed to get io memory region resource.\n");
1685
1686 ret = -ENOENT;
1687 goto probe_free_gpio;
1688 }
1689
1690 host->mem = request_mem_region(host->mem->start,
1691 resource_size(host->mem), pdev->name);
1692
1693 if (!host->mem) {
1694 dev_err(&pdev->dev, "failed to request io memory region.\n");
1695 ret = -ENOENT;
1696 goto probe_free_gpio;
1697 }
1698
1699 host->base = ioremap(host->mem->start, resource_size(host->mem));
1700 if (!host->base) {
1701 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1702 ret = -EINVAL;
1703 goto probe_free_mem_region;
1704 }
1705
1706 host->irq = platform_get_irq(pdev, 0);
1707 if (host->irq == 0) {
1708 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1709 ret = -EINVAL;
1710 goto probe_iounmap;
1711 }
1712
1713 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1714 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1715 ret = -ENOENT;
1716 goto probe_iounmap;
1717 }
1718
1719 /* We get spurious interrupts even when we have set the IMSK
1720 * register to ignore everything, so use disable_irq() to make
1721 * ensure we don't lock the system with un-serviceable requests. */
1722
1723 disable_irq(host->irq);
1724 host->irq_state = false;
1725
1726 if (!host->pdata->no_detect) {
1727 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1728 if (ret) {
1729 dev_err(&pdev->dev, "failed to get detect gpio\n");
1730 goto probe_free_irq;
1731 }
1732
1733 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1734
1735 if (host->irq_cd >= 0) {
1736 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1737 IRQF_TRIGGER_RISING |
1738 IRQF_TRIGGER_FALLING,
1739 DRIVER_NAME, host)) {
1740 dev_err(&pdev->dev,
1741 "can't get card detect irq.\n");
1742 ret = -ENOENT;
1743 goto probe_free_gpio_cd;
1744 }
1745 } else {
1746 dev_warn(&pdev->dev,
1747 "host detect has no irq available\n");
1748 gpio_direction_input(host->pdata->gpio_detect);
1749 }
1750 } else
1751 host->irq_cd = -1;
1752
1753 if (!host->pdata->no_wprotect) {
1754 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1755 if (ret) {
1756 dev_err(&pdev->dev, "failed to get writeprotect\n");
1757 goto probe_free_irq_cd;
1758 }
1759
1760 gpio_direction_input(host->pdata->gpio_wprotect);
1761 }
1762
1763 /* depending on the dma state, get a dma channel to use. */
1764
1765 if (s3cmci_host_usedma(host)) {
1766 host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1767 host);
1768 if (host->dma < 0) {
1769 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1770 if (!s3cmci_host_canpio()) {
1771 ret = -EBUSY;
1772 goto probe_free_gpio_wp;
1773 } else {
1774 dev_warn(&pdev->dev, "falling back to PIO.\n");
1775 host->dodma = 0;
1776 }
1777 }
1778 }
1779
1780 host->clk = clk_get(&pdev->dev, "sdi");
1781 if (IS_ERR(host->clk)) {
1782 dev_err(&pdev->dev, "failed to find clock source.\n");
1783 ret = PTR_ERR(host->clk);
1784 host->clk = NULL;
1785 goto probe_free_dma;
1786 }
1787
1788 ret = clk_enable(host->clk);
1789 if (ret) {
1790 dev_err(&pdev->dev, "failed to enable clock source.\n");
1791 goto clk_free;
1792 }
1793
1794 host->clk_rate = clk_get_rate(host->clk);
1795
1796 mmc->ops = &s3cmci_ops;
1797 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1798 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1799 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1800 #else
1801 mmc->caps = MMC_CAP_4_BIT_DATA;
1802 #endif
1803 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1804 mmc->f_max = host->clk_rate / host->clk_div;
1805
1806 if (host->pdata->ocr_avail)
1807 mmc->ocr_avail = host->pdata->ocr_avail;
1808
1809 mmc->max_blk_count = 4095;
1810 mmc->max_blk_size = 4095;
1811 mmc->max_req_size = 4095 * 512;
1812 mmc->max_seg_size = mmc->max_req_size;
1813
1814 mmc->max_segs = 128;
1815
1816 dbg(host, dbg_debug,
1817 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1818 (host->is2440?"2440":""),
1819 host->base, host->irq, host->irq_cd, host->dma);
1820
1821 ret = s3cmci_cpufreq_register(host);
1822 if (ret) {
1823 dev_err(&pdev->dev, "failed to register cpufreq\n");
1824 goto free_dmabuf;
1825 }
1826
1827 ret = mmc_add_host(mmc);
1828 if (ret) {
1829 dev_err(&pdev->dev, "failed to add mmc host.\n");
1830 goto free_cpufreq;
1831 }
1832
1833 s3cmci_debugfs_attach(host);
1834
1835 platform_set_drvdata(pdev, mmc);
1836 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1837 s3cmci_host_usedma(host) ? "dma" : "pio",
1838 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1839
1840 return 0;
1841
1842 free_cpufreq:
1843 s3cmci_cpufreq_deregister(host);
1844
1845 free_dmabuf:
1846 clk_disable(host->clk);
1847
1848 clk_free:
1849 clk_put(host->clk);
1850
1851 probe_free_dma:
1852 if (s3cmci_host_usedma(host))
1853 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1854
1855 probe_free_gpio_wp:
1856 if (!host->pdata->no_wprotect)
1857 gpio_free(host->pdata->gpio_wprotect);
1858
1859 probe_free_gpio_cd:
1860 if (!host->pdata->no_detect)
1861 gpio_free(host->pdata->gpio_detect);
1862
1863 probe_free_irq_cd:
1864 if (host->irq_cd >= 0)
1865 free_irq(host->irq_cd, host);
1866
1867 probe_free_irq:
1868 free_irq(host->irq, host);
1869
1870 probe_iounmap:
1871 iounmap(host->base);
1872
1873 probe_free_mem_region:
1874 release_mem_region(host->mem->start, resource_size(host->mem));
1875
1876 probe_free_gpio:
1877 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1878 gpio_free(i);
1879
1880 probe_free_host:
1881 mmc_free_host(mmc);
1882
1883 probe_out:
1884 return ret;
1885 }
1886
1887 static void s3cmci_shutdown(struct platform_device *pdev)
1888 {
1889 struct mmc_host *mmc = platform_get_drvdata(pdev);
1890 struct s3cmci_host *host = mmc_priv(mmc);
1891
1892 if (host->irq_cd >= 0)
1893 free_irq(host->irq_cd, host);
1894
1895 s3cmci_debugfs_remove(host);
1896 s3cmci_cpufreq_deregister(host);
1897 mmc_remove_host(mmc);
1898 clk_disable(host->clk);
1899 }
1900
1901 static int s3cmci_remove(struct platform_device *pdev)
1902 {
1903 struct mmc_host *mmc = platform_get_drvdata(pdev);
1904 struct s3cmci_host *host = mmc_priv(mmc);
1905 struct s3c24xx_mci_pdata *pd = host->pdata;
1906 int i;
1907
1908 s3cmci_shutdown(pdev);
1909
1910 clk_put(host->clk);
1911
1912 tasklet_disable(&host->pio_tasklet);
1913
1914 if (s3cmci_host_usedma(host))
1915 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1916
1917 free_irq(host->irq, host);
1918
1919 if (!pd->no_wprotect)
1920 gpio_free(pd->gpio_wprotect);
1921
1922 if (!pd->no_detect)
1923 gpio_free(pd->gpio_detect);
1924
1925 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1926 gpio_free(i);
1927
1928
1929 iounmap(host->base);
1930 release_mem_region(host->mem->start, resource_size(host->mem));
1931
1932 mmc_free_host(mmc);
1933 return 0;
1934 }
1935
1936 static struct platform_device_id s3cmci_driver_ids[] = {
1937 {
1938 .name = "s3c2410-sdi",
1939 .driver_data = 0,
1940 }, {
1941 .name = "s3c2412-sdi",
1942 .driver_data = 1,
1943 }, {
1944 .name = "s3c2440-sdi",
1945 .driver_data = 1,
1946 },
1947 { }
1948 };
1949
1950 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1951
1952
1953 #ifdef CONFIG_PM
1954
1955 static int s3cmci_suspend(struct device *dev)
1956 {
1957 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1958
1959 return mmc_suspend_host(mmc);
1960 }
1961
1962 static int s3cmci_resume(struct device *dev)
1963 {
1964 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1965
1966 return mmc_resume_host(mmc);
1967 }
1968
1969 static const struct dev_pm_ops s3cmci_pm = {
1970 .suspend = s3cmci_suspend,
1971 .resume = s3cmci_resume,
1972 };
1973
1974 #define s3cmci_pm_ops &s3cmci_pm
1975 #else /* CONFIG_PM */
1976 #define s3cmci_pm_ops NULL
1977 #endif /* CONFIG_PM */
1978
1979
1980 static struct platform_driver s3cmci_driver = {
1981 .driver = {
1982 .name = "s3c-sdi",
1983 .owner = THIS_MODULE,
1984 .pm = s3cmci_pm_ops,
1985 },
1986 .id_table = s3cmci_driver_ids,
1987 .probe = s3cmci_probe,
1988 .remove = s3cmci_remove,
1989 .shutdown = s3cmci_shutdown,
1990 };
1991
1992 module_platform_driver(s3cmci_driver);
1993
1994 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1995 MODULE_LICENSE("GPL v2");
1996 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
Linux with added FPC-III support