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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci.c
blob27ae563d0caa43ce8d01e14bf7adc4132bfbd29e
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/sdhci-pci-data.h>
28
29 #include "sdhci.h"
30
31 /*
32 * PCI device IDs
33 */
34 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
35 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
36 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
37 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
38 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
39 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
40
41 /*
42 * PCI registers
43 */
44
45 #define PCI_SDHCI_IFPIO 0x00
46 #define PCI_SDHCI_IFDMA 0x01
47 #define PCI_SDHCI_IFVENDOR 0x02
48
49 #define PCI_SLOT_INFO 0x40 /* 8 bits */
50 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
51 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
52
53 #define MAX_SLOTS 8
54
55 struct sdhci_pci_chip;
56 struct sdhci_pci_slot;
57
58 struct sdhci_pci_fixes {
59 unsigned int quirks;
60 unsigned int quirks2;
61 bool allow_runtime_pm;
62 bool own_cd_for_runtime_pm;
63
64 int (*probe) (struct sdhci_pci_chip *);
65
66 int (*probe_slot) (struct sdhci_pci_slot *);
67 void (*remove_slot) (struct sdhci_pci_slot *, int);
68
69 int (*suspend) (struct sdhci_pci_chip *);
70 int (*resume) (struct sdhci_pci_chip *);
71 };
72
73 struct sdhci_pci_slot {
74 struct sdhci_pci_chip *chip;
75 struct sdhci_host *host;
76 struct sdhci_pci_data *data;
77
78 int pci_bar;
79 int rst_n_gpio;
80 int cd_gpio;
81 int cd_irq;
82
83 void (*hw_reset)(struct sdhci_host *host);
84 };
85
86 struct sdhci_pci_chip {
87 struct pci_dev *pdev;
88
89 unsigned int quirks;
90 unsigned int quirks2;
91 bool allow_runtime_pm;
92 const struct sdhci_pci_fixes *fixes;
93
94 int num_slots; /* Slots on controller */
95 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
96 };
97
98
99 /*****************************************************************************\
100 * *
101 * Hardware specific quirk handling *
102 * *
103 \*****************************************************************************/
104
105 static int ricoh_probe(struct sdhci_pci_chip *chip)
106 {
107 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
108 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
109 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
110 return 0;
111 }
112
113 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
114 {
115 slot->host->caps =
116 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
117 & SDHCI_TIMEOUT_CLK_MASK) |
118
119 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
120 & SDHCI_CLOCK_BASE_MASK) |
121
122 SDHCI_TIMEOUT_CLK_UNIT |
123 SDHCI_CAN_VDD_330 |
124 SDHCI_CAN_DO_HISPD |
125 SDHCI_CAN_DO_SDMA;
126 return 0;
127 }
128
129 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
130 {
131 /* Apply a delay to allow controller to settle */
132 /* Otherwise it becomes confused if card state changed
133 during suspend */
134 msleep(500);
135 return 0;
136 }
137
138 static const struct sdhci_pci_fixes sdhci_ricoh = {
139 .probe = ricoh_probe,
140 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
141 SDHCI_QUIRK_FORCE_DMA |
142 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
143 };
144
145 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
146 .probe_slot = ricoh_mmc_probe_slot,
147 .resume = ricoh_mmc_resume,
148 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
149 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
150 SDHCI_QUIRK_NO_CARD_NO_RESET |
151 SDHCI_QUIRK_MISSING_CAPS
152 };
153
154 static const struct sdhci_pci_fixes sdhci_ene_712 = {
155 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
156 SDHCI_QUIRK_BROKEN_DMA,
157 };
158
159 static const struct sdhci_pci_fixes sdhci_ene_714 = {
160 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
161 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
162 SDHCI_QUIRK_BROKEN_DMA,
163 };
164
165 static const struct sdhci_pci_fixes sdhci_cafe = {
166 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
167 SDHCI_QUIRK_NO_BUSY_IRQ |
168 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
169 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
170 };
171
172 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
173 {
174 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
175 return 0;
176 }
177
178 /*
179 * ADMA operation is disabled for Moorestown platform due to
180 * hardware bugs.
181 */
182 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
183 {
184 /*
185 * slots number is fixed here for MRST as SDIO3/5 are never used and
186 * have hardware bugs.
187 */
188 chip->num_slots = 1;
189 return 0;
190 }
191
192 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
193 {
194 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
195 return 0;
196 }
197
198 #ifdef CONFIG_PM_RUNTIME
199
200 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
201 {
202 struct sdhci_pci_slot *slot = dev_id;
203 struct sdhci_host *host = slot->host;
204
205 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
206 return IRQ_HANDLED;
207 }
208
209 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
210 {
211 int err, irq, gpio = slot->cd_gpio;
212
213 slot->cd_gpio = -EINVAL;
214 slot->cd_irq = -EINVAL;
215
216 if (!gpio_is_valid(gpio))
217 return;
218
219 err = gpio_request(gpio, "sd_cd");
220 if (err < 0)
221 goto out;
222
223 err = gpio_direction_input(gpio);
224 if (err < 0)
225 goto out_free;
226
227 irq = gpio_to_irq(gpio);
228 if (irq < 0)
229 goto out_free;
230
231 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
232 IRQF_TRIGGER_FALLING, "sd_cd", slot);
233 if (err)
234 goto out_free;
235
236 slot->cd_gpio = gpio;
237 slot->cd_irq = irq;
238
239 return;
240
241 out_free:
242 gpio_free(gpio);
243 out:
244 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
245 }
246
247 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
248 {
249 if (slot->cd_irq >= 0)
250 free_irq(slot->cd_irq, slot);
251 if (gpio_is_valid(slot->cd_gpio))
252 gpio_free(slot->cd_gpio);
253 }
254
255 #else
256
257 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
258 {
259 }
260
261 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
262 {
263 }
264
265 #endif
266
267 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
268 {
269 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
270 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
271 MMC_CAP2_HC_ERASE_SZ;
272 return 0;
273 }
274
275 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
276 {
277 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
278 return 0;
279 }
280
281 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
282 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
283 .probe_slot = mrst_hc_probe_slot,
284 };
285
286 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
287 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
288 .probe = mrst_hc_probe,
289 };
290
291 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
292 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
293 .allow_runtime_pm = true,
294 .own_cd_for_runtime_pm = true,
295 };
296
297 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
298 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
299 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
300 .allow_runtime_pm = true,
301 .probe_slot = mfd_sdio_probe_slot,
302 };
303
304 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
305 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
306 .allow_runtime_pm = true,
307 .probe_slot = mfd_emmc_probe_slot,
308 };
309
310 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
311 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
312 .probe_slot = pch_hc_probe_slot,
313 };
314
315 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
316 {
317 u8 reg;
318
319 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
320 reg |= 0x10;
321 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
322 /* For eMMC, minimum is 1us but give it 9us for good measure */
323 udelay(9);
324 reg &= ~0x10;
325 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
326 /* For eMMC, minimum is 200us but give it 300us for good measure */
327 usleep_range(300, 1000);
328 }
329
330 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
331 {
332 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
333 MMC_CAP_HW_RESET;
334 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
335 slot->hw_reset = sdhci_pci_int_hw_reset;
336 return 0;
337 }
338
339 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
340 {
341 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
342 return 0;
343 }
344
345 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
346 .allow_runtime_pm = true,
347 .probe_slot = byt_emmc_probe_slot,
348 };
349
350 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
351 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
352 .allow_runtime_pm = true,
353 .probe_slot = byt_sdio_probe_slot,
354 };
355
356 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
357 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON,
358 .allow_runtime_pm = true,
359 .own_cd_for_runtime_pm = true,
360 };
361
362 /* O2Micro extra registers */
363 #define O2_SD_LOCK_WP 0xD3
364 #define O2_SD_MULTI_VCC3V 0xEE
365 #define O2_SD_CLKREQ 0xEC
366 #define O2_SD_CAPS 0xE0
367 #define O2_SD_ADMA1 0xE2
368 #define O2_SD_ADMA2 0xE7
369 #define O2_SD_INF_MOD 0xF1
370
371 static int o2_probe(struct sdhci_pci_chip *chip)
372 {
373 int ret;
374 u8 scratch;
375
376 switch (chip->pdev->device) {
377 case PCI_DEVICE_ID_O2_8220:
378 case PCI_DEVICE_ID_O2_8221:
379 case PCI_DEVICE_ID_O2_8320:
380 case PCI_DEVICE_ID_O2_8321:
381 /* This extra setup is required due to broken ADMA. */
382 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
383 if (ret)
384 return ret;
385 scratch &= 0x7f;
386 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
387
388 /* Set Multi 3 to VCC3V# */
389 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
390
391 /* Disable CLK_REQ# support after media DET */
392 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
393 if (ret)
394 return ret;
395 scratch |= 0x20;
396 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
397
398 /* Choose capabilities, enable SDMA. We have to write 0x01
399 * to the capabilities register first to unlock it.
400 */
401 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
402 if (ret)
403 return ret;
404 scratch |= 0x01;
405 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
406 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
407
408 /* Disable ADMA1/2 */
409 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
410 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
411
412 /* Disable the infinite transfer mode */
413 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
414 if (ret)
415 return ret;
416 scratch |= 0x08;
417 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
418
419 /* Lock WP */
420 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
421 if (ret)
422 return ret;
423 scratch |= 0x80;
424 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
425 }
426
427 return 0;
428 }
429
430 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
431 {
432 u8 scratch;
433 int ret;
434
435 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
436 if (ret)
437 return ret;
438
439 /*
440 * Turn PMOS on [bit 0], set over current detection to 2.4 V
441 * [bit 1:2] and enable over current debouncing [bit 6].
442 */
443 if (on)
444 scratch |= 0x47;
445 else
446 scratch &= ~0x47;
447
448 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
449 if (ret)
450 return ret;
451
452 return 0;
453 }
454
455 static int jmicron_probe(struct sdhci_pci_chip *chip)
456 {
457 int ret;
458 u16 mmcdev = 0;
459
460 if (chip->pdev->revision == 0) {
461 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
462 SDHCI_QUIRK_32BIT_DMA_SIZE |
463 SDHCI_QUIRK_32BIT_ADMA_SIZE |
464 SDHCI_QUIRK_RESET_AFTER_REQUEST |
465 SDHCI_QUIRK_BROKEN_SMALL_PIO;
466 }
467
468 /*
469 * JMicron chips can have two interfaces to the same hardware
470 * in order to work around limitations in Microsoft's driver.
471 * We need to make sure we only bind to one of them.
472 *
473 * This code assumes two things:
474 *
475 * 1. The PCI code adds subfunctions in order.
476 *
477 * 2. The MMC interface has a lower subfunction number
478 * than the SD interface.
479 */
480 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
481 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
482 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
483 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
484
485 if (mmcdev) {
486 struct pci_dev *sd_dev;
487
488 sd_dev = NULL;
489 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
490 mmcdev, sd_dev)) != NULL) {
491 if ((PCI_SLOT(chip->pdev->devfn) ==
492 PCI_SLOT(sd_dev->devfn)) &&
493 (chip->pdev->bus == sd_dev->bus))
494 break;
495 }
496
497 if (sd_dev) {
498 pci_dev_put(sd_dev);
499 dev_info(&chip->pdev->dev, "Refusing to bind to "
500 "secondary interface.\n");
501 return -ENODEV;
502 }
503 }
504
505 /*
506 * JMicron chips need a bit of a nudge to enable the power
507 * output pins.
508 */
509 ret = jmicron_pmos(chip, 1);
510 if (ret) {
511 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
512 return ret;
513 }
514
515 /* quirk for unsable RO-detection on JM388 chips */
516 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
517 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
518 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
519
520 return 0;
521 }
522
523 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
524 {
525 u8 scratch;
526
527 scratch = readb(host->ioaddr + 0xC0);
528
529 if (on)
530 scratch |= 0x01;
531 else
532 scratch &= ~0x01;
533
534 writeb(scratch, host->ioaddr + 0xC0);
535 }
536
537 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
538 {
539 if (slot->chip->pdev->revision == 0) {
540 u16 version;
541
542 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
543 version = (version & SDHCI_VENDOR_VER_MASK) >>
544 SDHCI_VENDOR_VER_SHIFT;
545
546 /*
547 * Older versions of the chip have lots of nasty glitches
548 * in the ADMA engine. It's best just to avoid it
549 * completely.
550 */
551 if (version < 0xAC)
552 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
553 }
554
555 /* JM388 MMC doesn't support 1.8V while SD supports it */
556 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
557 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
558 MMC_VDD_29_30 | MMC_VDD_30_31 |
559 MMC_VDD_165_195; /* allow 1.8V */
560 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
561 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
562 }
563
564 /*
565 * The secondary interface requires a bit set to get the
566 * interrupts.
567 */
568 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
569 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
570 jmicron_enable_mmc(slot->host, 1);
571
572 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
573
574 return 0;
575 }
576
577 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
578 {
579 if (dead)
580 return;
581
582 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
583 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
584 jmicron_enable_mmc(slot->host, 0);
585 }
586
587 static int jmicron_suspend(struct sdhci_pci_chip *chip)
588 {
589 int i;
590
591 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
592 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
593 for (i = 0; i < chip->num_slots; i++)
594 jmicron_enable_mmc(chip->slots[i]->host, 0);
595 }
596
597 return 0;
598 }
599
600 static int jmicron_resume(struct sdhci_pci_chip *chip)
601 {
602 int ret, i;
603
604 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
605 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
606 for (i = 0; i < chip->num_slots; i++)
607 jmicron_enable_mmc(chip->slots[i]->host, 1);
608 }
609
610 ret = jmicron_pmos(chip, 1);
611 if (ret) {
612 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
613 return ret;
614 }
615
616 return 0;
617 }
618
619 static const struct sdhci_pci_fixes sdhci_o2 = {
620 .probe = o2_probe,
621 };
622
623 static const struct sdhci_pci_fixes sdhci_jmicron = {
624 .probe = jmicron_probe,
625
626 .probe_slot = jmicron_probe_slot,
627 .remove_slot = jmicron_remove_slot,
628
629 .suspend = jmicron_suspend,
630 .resume = jmicron_resume,
631 };
632
633 /* SysKonnect CardBus2SDIO extra registers */
634 #define SYSKT_CTRL 0x200
635 #define SYSKT_RDFIFO_STAT 0x204
636 #define SYSKT_WRFIFO_STAT 0x208
637 #define SYSKT_POWER_DATA 0x20c
638 #define SYSKT_POWER_330 0xef
639 #define SYSKT_POWER_300 0xf8
640 #define SYSKT_POWER_184 0xcc
641 #define SYSKT_POWER_CMD 0x20d
642 #define SYSKT_POWER_START (1 << 7)
643 #define SYSKT_POWER_STATUS 0x20e
644 #define SYSKT_POWER_STATUS_OK (1 << 0)
645 #define SYSKT_BOARD_REV 0x210
646 #define SYSKT_CHIP_REV 0x211
647 #define SYSKT_CONF_DATA 0x212
648 #define SYSKT_CONF_DATA_1V8 (1 << 2)
649 #define SYSKT_CONF_DATA_2V5 (1 << 1)
650 #define SYSKT_CONF_DATA_3V3 (1 << 0)
651
652 static int syskt_probe(struct sdhci_pci_chip *chip)
653 {
654 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
655 chip->pdev->class &= ~0x0000FF;
656 chip->pdev->class |= PCI_SDHCI_IFDMA;
657 }
658 return 0;
659 }
660
661 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
662 {
663 int tm, ps;
664
665 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
666 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
667 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
668 "board rev %d.%d, chip rev %d.%d\n",
669 board_rev >> 4, board_rev & 0xf,
670 chip_rev >> 4, chip_rev & 0xf);
671 if (chip_rev >= 0x20)
672 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
673
674 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
675 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
676 udelay(50);
677 tm = 10; /* Wait max 1 ms */
678 do {
679 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
680 if (ps & SYSKT_POWER_STATUS_OK)
681 break;
682 udelay(100);
683 } while (--tm);
684 if (!tm) {
685 dev_err(&slot->chip->pdev->dev,
686 "power regulator never stabilized");
687 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
688 return -ENODEV;
689 }
690
691 return 0;
692 }
693
694 static const struct sdhci_pci_fixes sdhci_syskt = {
695 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
696 .probe = syskt_probe,
697 .probe_slot = syskt_probe_slot,
698 };
699
700 static int via_probe(struct sdhci_pci_chip *chip)
701 {
702 if (chip->pdev->revision == 0x10)
703 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
704
705 return 0;
706 }
707
708 static const struct sdhci_pci_fixes sdhci_via = {
709 .probe = via_probe,
710 };
711
712 static const struct pci_device_id pci_ids[] = {
713 {
714 .vendor = PCI_VENDOR_ID_RICOH,
715 .device = PCI_DEVICE_ID_RICOH_R5C822,
716 .subvendor = PCI_ANY_ID,
717 .subdevice = PCI_ANY_ID,
718 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
719 },
720
721 {
722 .vendor = PCI_VENDOR_ID_RICOH,
723 .device = 0x843,
724 .subvendor = PCI_ANY_ID,
725 .subdevice = PCI_ANY_ID,
726 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
727 },
728
729 {
730 .vendor = PCI_VENDOR_ID_RICOH,
731 .device = 0xe822,
732 .subvendor = PCI_ANY_ID,
733 .subdevice = PCI_ANY_ID,
734 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
735 },
736
737 {
738 .vendor = PCI_VENDOR_ID_RICOH,
739 .device = 0xe823,
740 .subvendor = PCI_ANY_ID,
741 .subdevice = PCI_ANY_ID,
742 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
743 },
744
745 {
746 .vendor = PCI_VENDOR_ID_ENE,
747 .device = PCI_DEVICE_ID_ENE_CB712_SD,
748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
750 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
751 },
752
753 {
754 .vendor = PCI_VENDOR_ID_ENE,
755 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
756 .subvendor = PCI_ANY_ID,
757 .subdevice = PCI_ANY_ID,
758 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
759 },
760
761 {
762 .vendor = PCI_VENDOR_ID_ENE,
763 .device = PCI_DEVICE_ID_ENE_CB714_SD,
764 .subvendor = PCI_ANY_ID,
765 .subdevice = PCI_ANY_ID,
766 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
767 },
768
769 {
770 .vendor = PCI_VENDOR_ID_ENE,
771 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
772 .subvendor = PCI_ANY_ID,
773 .subdevice = PCI_ANY_ID,
774 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
775 },
776
777 {
778 .vendor = PCI_VENDOR_ID_MARVELL,
779 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
780 .subvendor = PCI_ANY_ID,
781 .subdevice = PCI_ANY_ID,
782 .driver_data = (kernel_ulong_t)&sdhci_cafe,
783 },
784
785 {
786 .vendor = PCI_VENDOR_ID_JMICRON,
787 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
788 .subvendor = PCI_ANY_ID,
789 .subdevice = PCI_ANY_ID,
790 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
791 },
792
793 {
794 .vendor = PCI_VENDOR_ID_JMICRON,
795 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
796 .subvendor = PCI_ANY_ID,
797 .subdevice = PCI_ANY_ID,
798 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
799 },
800
801 {
802 .vendor = PCI_VENDOR_ID_JMICRON,
803 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
807 },
808
809 {
810 .vendor = PCI_VENDOR_ID_JMICRON,
811 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
812 .subvendor = PCI_ANY_ID,
813 .subdevice = PCI_ANY_ID,
814 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
815 },
816
817 {
818 .vendor = PCI_VENDOR_ID_SYSKONNECT,
819 .device = 0x8000,
820 .subvendor = PCI_ANY_ID,
821 .subdevice = PCI_ANY_ID,
822 .driver_data = (kernel_ulong_t)&sdhci_syskt,
823 },
824
825 {
826 .vendor = PCI_VENDOR_ID_VIA,
827 .device = 0x95d0,
828 .subvendor = PCI_ANY_ID,
829 .subdevice = PCI_ANY_ID,
830 .driver_data = (kernel_ulong_t)&sdhci_via,
831 },
832
833 {
834 .vendor = PCI_VENDOR_ID_INTEL,
835 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
836 .subvendor = PCI_ANY_ID,
837 .subdevice = PCI_ANY_ID,
838 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
839 },
840
841 {
842 .vendor = PCI_VENDOR_ID_INTEL,
843 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
844 .subvendor = PCI_ANY_ID,
845 .subdevice = PCI_ANY_ID,
846 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
847 },
848
849 {
850 .vendor = PCI_VENDOR_ID_INTEL,
851 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
852 .subvendor = PCI_ANY_ID,
853 .subdevice = PCI_ANY_ID,
854 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
855 },
856
857 {
858 .vendor = PCI_VENDOR_ID_INTEL,
859 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
860 .subvendor = PCI_ANY_ID,
861 .subdevice = PCI_ANY_ID,
862 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
863 },
864
865 {
866 .vendor = PCI_VENDOR_ID_INTEL,
867 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
868 .subvendor = PCI_ANY_ID,
869 .subdevice = PCI_ANY_ID,
870 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
871 },
872
873 {
874 .vendor = PCI_VENDOR_ID_INTEL,
875 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
876 .subvendor = PCI_ANY_ID,
877 .subdevice = PCI_ANY_ID,
878 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
879 },
880
881 {
882 .vendor = PCI_VENDOR_ID_INTEL,
883 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
884 .subvendor = PCI_ANY_ID,
885 .subdevice = PCI_ANY_ID,
886 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
887 },
888
889 {
890 .vendor = PCI_VENDOR_ID_INTEL,
891 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
892 .subvendor = PCI_ANY_ID,
893 .subdevice = PCI_ANY_ID,
894 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
895 },
896
897 {
898 .vendor = PCI_VENDOR_ID_INTEL,
899 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
900 .subvendor = PCI_ANY_ID,
901 .subdevice = PCI_ANY_ID,
902 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
903 },
904
905 {
906 .vendor = PCI_VENDOR_ID_INTEL,
907 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
908 .subvendor = PCI_ANY_ID,
909 .subdevice = PCI_ANY_ID,
910 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
911 },
912
913 {
914 .vendor = PCI_VENDOR_ID_INTEL,
915 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
916 .subvendor = PCI_ANY_ID,
917 .subdevice = PCI_ANY_ID,
918 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
919 },
920
921 {
922 .vendor = PCI_VENDOR_ID_INTEL,
923 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
924 .subvendor = PCI_ANY_ID,
925 .subdevice = PCI_ANY_ID,
926 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
927 },
928
929 {
930 .vendor = PCI_VENDOR_ID_INTEL,
931 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
932 .subvendor = PCI_ANY_ID,
933 .subdevice = PCI_ANY_ID,
934 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
935 },
936
937 {
938 .vendor = PCI_VENDOR_ID_INTEL,
939 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
940 .subvendor = PCI_ANY_ID,
941 .subdevice = PCI_ANY_ID,
942 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
943 },
944
945 {
946 .vendor = PCI_VENDOR_ID_O2,
947 .device = PCI_DEVICE_ID_O2_8120,
948 .subvendor = PCI_ANY_ID,
949 .subdevice = PCI_ANY_ID,
950 .driver_data = (kernel_ulong_t)&sdhci_o2,
951 },
952
953 {
954 .vendor = PCI_VENDOR_ID_O2,
955 .device = PCI_DEVICE_ID_O2_8220,
956 .subvendor = PCI_ANY_ID,
957 .subdevice = PCI_ANY_ID,
958 .driver_data = (kernel_ulong_t)&sdhci_o2,
959 },
960
961 {
962 .vendor = PCI_VENDOR_ID_O2,
963 .device = PCI_DEVICE_ID_O2_8221,
964 .subvendor = PCI_ANY_ID,
965 .subdevice = PCI_ANY_ID,
966 .driver_data = (kernel_ulong_t)&sdhci_o2,
967 },
968
969 {
970 .vendor = PCI_VENDOR_ID_O2,
971 .device = PCI_DEVICE_ID_O2_8320,
972 .subvendor = PCI_ANY_ID,
973 .subdevice = PCI_ANY_ID,
974 .driver_data = (kernel_ulong_t)&sdhci_o2,
975 },
976
977 {
978 .vendor = PCI_VENDOR_ID_O2,
979 .device = PCI_DEVICE_ID_O2_8321,
980 .subvendor = PCI_ANY_ID,
981 .subdevice = PCI_ANY_ID,
982 .driver_data = (kernel_ulong_t)&sdhci_o2,
983 },
984
985 { /* Generic SD host controller */
986 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
987 },
988
989 { /* end: all zeroes */ },
990 };
991
992 MODULE_DEVICE_TABLE(pci, pci_ids);
993
994 /*****************************************************************************\
995 * *
996 * SDHCI core callbacks *
997 * *
998 \*****************************************************************************/
999
1000 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1001 {
1002 struct sdhci_pci_slot *slot;
1003 struct pci_dev *pdev;
1004 int ret;
1005
1006 slot = sdhci_priv(host);
1007 pdev = slot->chip->pdev;
1008
1009 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1010 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1011 (host->flags & SDHCI_USE_SDMA)) {
1012 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1013 "doesn't fully claim to support it.\n");
1014 }
1015
1016 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1017 if (ret)
1018 return ret;
1019
1020 pci_set_master(pdev);
1021
1022 return 0;
1023 }
1024
1025 static int sdhci_pci_bus_width(struct sdhci_host *host, int width)
1026 {
1027 u8 ctrl;
1028
1029 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1030
1031 switch (width) {
1032 case MMC_BUS_WIDTH_8:
1033 ctrl |= SDHCI_CTRL_8BITBUS;
1034 ctrl &= ~SDHCI_CTRL_4BITBUS;
1035 break;
1036 case MMC_BUS_WIDTH_4:
1037 ctrl |= SDHCI_CTRL_4BITBUS;
1038 ctrl &= ~SDHCI_CTRL_8BITBUS;
1039 break;
1040 default:
1041 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1042 break;
1043 }
1044
1045 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1046
1047 return 0;
1048 }
1049
1050 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1051 {
1052 struct sdhci_pci_slot *slot = sdhci_priv(host);
1053 int rst_n_gpio = slot->rst_n_gpio;
1054
1055 if (!gpio_is_valid(rst_n_gpio))
1056 return;
1057 gpio_set_value_cansleep(rst_n_gpio, 0);
1058 /* For eMMC, minimum is 1us but give it 10us for good measure */
1059 udelay(10);
1060 gpio_set_value_cansleep(rst_n_gpio, 1);
1061 /* For eMMC, minimum is 200us but give it 300us for good measure */
1062 usleep_range(300, 1000);
1063 }
1064
1065 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1066 {
1067 struct sdhci_pci_slot *slot = sdhci_priv(host);
1068
1069 if (slot->hw_reset)
1070 slot->hw_reset(host);
1071 }
1072
1073 static const struct sdhci_ops sdhci_pci_ops = {
1074 .enable_dma = sdhci_pci_enable_dma,
1075 .platform_bus_width = sdhci_pci_bus_width,
1076 .hw_reset = sdhci_pci_hw_reset,
1077 };
1078
1079 /*****************************************************************************\
1080 * *
1081 * Suspend/resume *
1082 * *
1083 \*****************************************************************************/
1084
1085 #ifdef CONFIG_PM
1086
1087 static int sdhci_pci_suspend(struct device *dev)
1088 {
1089 struct pci_dev *pdev = to_pci_dev(dev);
1090 struct sdhci_pci_chip *chip;
1091 struct sdhci_pci_slot *slot;
1092 mmc_pm_flag_t slot_pm_flags;
1093 mmc_pm_flag_t pm_flags = 0;
1094 int i, ret;
1095
1096 chip = pci_get_drvdata(pdev);
1097 if (!chip)
1098 return 0;
1099
1100 for (i = 0; i < chip->num_slots; i++) {
1101 slot = chip->slots[i];
1102 if (!slot)
1103 continue;
1104
1105 ret = sdhci_suspend_host(slot->host);
1106
1107 if (ret)
1108 goto err_pci_suspend;
1109
1110 slot_pm_flags = slot->host->mmc->pm_flags;
1111 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1112 sdhci_enable_irq_wakeups(slot->host);
1113
1114 pm_flags |= slot_pm_flags;
1115 }
1116
1117 if (chip->fixes && chip->fixes->suspend) {
1118 ret = chip->fixes->suspend(chip);
1119 if (ret)
1120 goto err_pci_suspend;
1121 }
1122
1123 pci_save_state(pdev);
1124 if (pm_flags & MMC_PM_KEEP_POWER) {
1125 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1126 pci_pme_active(pdev, true);
1127 pci_enable_wake(pdev, PCI_D3hot, 1);
1128 }
1129 pci_set_power_state(pdev, PCI_D3hot);
1130 } else {
1131 pci_enable_wake(pdev, PCI_D3hot, 0);
1132 pci_disable_device(pdev);
1133 pci_set_power_state(pdev, PCI_D3hot);
1134 }
1135
1136 return 0;
1137
1138 err_pci_suspend:
1139 while (--i >= 0)
1140 sdhci_resume_host(chip->slots[i]->host);
1141 return ret;
1142 }
1143
1144 static int sdhci_pci_resume(struct device *dev)
1145 {
1146 struct pci_dev *pdev = to_pci_dev(dev);
1147 struct sdhci_pci_chip *chip;
1148 struct sdhci_pci_slot *slot;
1149 int i, ret;
1150
1151 chip = pci_get_drvdata(pdev);
1152 if (!chip)
1153 return 0;
1154
1155 pci_set_power_state(pdev, PCI_D0);
1156 pci_restore_state(pdev);
1157 ret = pci_enable_device(pdev);
1158 if (ret)
1159 return ret;
1160
1161 if (chip->fixes && chip->fixes->resume) {
1162 ret = chip->fixes->resume(chip);
1163 if (ret)
1164 return ret;
1165 }
1166
1167 for (i = 0; i < chip->num_slots; i++) {
1168 slot = chip->slots[i];
1169 if (!slot)
1170 continue;
1171
1172 ret = sdhci_resume_host(slot->host);
1173 if (ret)
1174 return ret;
1175 }
1176
1177 return 0;
1178 }
1179
1180 #else /* CONFIG_PM */
1181
1182 #define sdhci_pci_suspend NULL
1183 #define sdhci_pci_resume NULL
1184
1185 #endif /* CONFIG_PM */
1186
1187 #ifdef CONFIG_PM_RUNTIME
1188
1189 static int sdhci_pci_runtime_suspend(struct device *dev)
1190 {
1191 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1192 struct sdhci_pci_chip *chip;
1193 struct sdhci_pci_slot *slot;
1194 int i, ret;
1195
1196 chip = pci_get_drvdata(pdev);
1197 if (!chip)
1198 return 0;
1199
1200 for (i = 0; i < chip->num_slots; i++) {
1201 slot = chip->slots[i];
1202 if (!slot)
1203 continue;
1204
1205 ret = sdhci_runtime_suspend_host(slot->host);
1206
1207 if (ret)
1208 goto err_pci_runtime_suspend;
1209 }
1210
1211 if (chip->fixes && chip->fixes->suspend) {
1212 ret = chip->fixes->suspend(chip);
1213 if (ret)
1214 goto err_pci_runtime_suspend;
1215 }
1216
1217 return 0;
1218
1219 err_pci_runtime_suspend:
1220 while (--i >= 0)
1221 sdhci_runtime_resume_host(chip->slots[i]->host);
1222 return ret;
1223 }
1224
1225 static int sdhci_pci_runtime_resume(struct device *dev)
1226 {
1227 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1228 struct sdhci_pci_chip *chip;
1229 struct sdhci_pci_slot *slot;
1230 int i, ret;
1231
1232 chip = pci_get_drvdata(pdev);
1233 if (!chip)
1234 return 0;
1235
1236 if (chip->fixes && chip->fixes->resume) {
1237 ret = chip->fixes->resume(chip);
1238 if (ret)
1239 return ret;
1240 }
1241
1242 for (i = 0; i < chip->num_slots; i++) {
1243 slot = chip->slots[i];
1244 if (!slot)
1245 continue;
1246
1247 ret = sdhci_runtime_resume_host(slot->host);
1248 if (ret)
1249 return ret;
1250 }
1251
1252 return 0;
1253 }
1254
1255 static int sdhci_pci_runtime_idle(struct device *dev)
1256 {
1257 return 0;
1258 }
1259
1260 #else
1261
1262 #define sdhci_pci_runtime_suspend NULL
1263 #define sdhci_pci_runtime_resume NULL
1264 #define sdhci_pci_runtime_idle NULL
1265
1266 #endif
1267
1268 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1269 .suspend = sdhci_pci_suspend,
1270 .resume = sdhci_pci_resume,
1271 .runtime_suspend = sdhci_pci_runtime_suspend,
1272 .runtime_resume = sdhci_pci_runtime_resume,
1273 .runtime_idle = sdhci_pci_runtime_idle,
1274 };
1275
1276 /*****************************************************************************\
1277 * *
1278 * Device probing/removal *
1279 * *
1280 \*****************************************************************************/
1281
1282 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1283 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1284 int slotno)
1285 {
1286 struct sdhci_pci_slot *slot;
1287 struct sdhci_host *host;
1288 int ret, bar = first_bar + slotno;
1289
1290 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1291 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1292 return ERR_PTR(-ENODEV);
1293 }
1294
1295 if (pci_resource_len(pdev, bar) < 0x100) {
1296 dev_err(&pdev->dev, "Invalid iomem size. You may "
1297 "experience problems.\n");
1298 }
1299
1300 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1301 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1302 return ERR_PTR(-ENODEV);
1303 }
1304
1305 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1306 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1307 return ERR_PTR(-ENODEV);
1308 }
1309
1310 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1311 if (IS_ERR(host)) {
1312 dev_err(&pdev->dev, "cannot allocate host\n");
1313 return ERR_CAST(host);
1314 }
1315
1316 slot = sdhci_priv(host);
1317
1318 slot->chip = chip;
1319 slot->host = host;
1320 slot->pci_bar = bar;
1321 slot->rst_n_gpio = -EINVAL;
1322 slot->cd_gpio = -EINVAL;
1323
1324 /* Retrieve platform data if there is any */
1325 if (*sdhci_pci_get_data)
1326 slot->data = sdhci_pci_get_data(pdev, slotno);
1327
1328 if (slot->data) {
1329 if (slot->data->setup) {
1330 ret = slot->data->setup(slot->data);
1331 if (ret) {
1332 dev_err(&pdev->dev, "platform setup failed\n");
1333 goto free;
1334 }
1335 }
1336 slot->rst_n_gpio = slot->data->rst_n_gpio;
1337 slot->cd_gpio = slot->data->cd_gpio;
1338 }
1339
1340 host->hw_name = "PCI";
1341 host->ops = &sdhci_pci_ops;
1342 host->quirks = chip->quirks;
1343 host->quirks2 = chip->quirks2;
1344
1345 host->irq = pdev->irq;
1346
1347 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1348 if (ret) {
1349 dev_err(&pdev->dev, "cannot request region\n");
1350 goto cleanup;
1351 }
1352
1353 host->ioaddr = pci_ioremap_bar(pdev, bar);
1354 if (!host->ioaddr) {
1355 dev_err(&pdev->dev, "failed to remap registers\n");
1356 ret = -ENOMEM;
1357 goto release;
1358 }
1359
1360 if (chip->fixes && chip->fixes->probe_slot) {
1361 ret = chip->fixes->probe_slot(slot);
1362 if (ret)
1363 goto unmap;
1364 }
1365
1366 if (gpio_is_valid(slot->rst_n_gpio)) {
1367 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1368 gpio_direction_output(slot->rst_n_gpio, 1);
1369 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1370 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1371 } else {
1372 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1373 slot->rst_n_gpio = -EINVAL;
1374 }
1375 }
1376
1377 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1378 host->mmc->slotno = slotno;
1379 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1380
1381 ret = sdhci_add_host(host);
1382 if (ret)
1383 goto remove;
1384
1385 sdhci_pci_add_own_cd(slot);
1386
1387 /*
1388 * Check if the chip needs a separate GPIO for card detect to wake up
1389 * from runtime suspend. If it is not there, don't allow runtime PM.
1390 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1391 */
1392 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1393 !gpio_is_valid(slot->cd_gpio))
1394 chip->allow_runtime_pm = false;
1395
1396 return slot;
1397
1398 remove:
1399 if (gpio_is_valid(slot->rst_n_gpio))
1400 gpio_free(slot->rst_n_gpio);
1401
1402 if (chip->fixes && chip->fixes->remove_slot)
1403 chip->fixes->remove_slot(slot, 0);
1404
1405 unmap:
1406 iounmap(host->ioaddr);
1407
1408 release:
1409 pci_release_region(pdev, bar);
1410
1411 cleanup:
1412 if (slot->data && slot->data->cleanup)
1413 slot->data->cleanup(slot->data);
1414
1415 free:
1416 sdhci_free_host(host);
1417
1418 return ERR_PTR(ret);
1419 }
1420
1421 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1422 {
1423 int dead;
1424 u32 scratch;
1425
1426 sdhci_pci_remove_own_cd(slot);
1427
1428 dead = 0;
1429 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1430 if (scratch == (u32)-1)
1431 dead = 1;
1432
1433 sdhci_remove_host(slot->host, dead);
1434
1435 if (gpio_is_valid(slot->rst_n_gpio))
1436 gpio_free(slot->rst_n_gpio);
1437
1438 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1439 slot->chip->fixes->remove_slot(slot, dead);
1440
1441 if (slot->data && slot->data->cleanup)
1442 slot->data->cleanup(slot->data);
1443
1444 pci_release_region(slot->chip->pdev, slot->pci_bar);
1445
1446 sdhci_free_host(slot->host);
1447 }
1448
1449 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1450 {
1451 pm_runtime_put_noidle(dev);
1452 pm_runtime_allow(dev);
1453 pm_runtime_set_autosuspend_delay(dev, 50);
1454 pm_runtime_use_autosuspend(dev);
1455 pm_suspend_ignore_children(dev, 1);
1456 }
1457
1458 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1459 {
1460 pm_runtime_forbid(dev);
1461 pm_runtime_get_noresume(dev);
1462 }
1463
1464 static int sdhci_pci_probe(struct pci_dev *pdev,
1465 const struct pci_device_id *ent)
1466 {
1467 struct sdhci_pci_chip *chip;
1468 struct sdhci_pci_slot *slot;
1469
1470 u8 slots, first_bar;
1471 int ret, i;
1472
1473 BUG_ON(pdev == NULL);
1474 BUG_ON(ent == NULL);
1475
1476 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1477 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1478
1479 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1480 if (ret)
1481 return ret;
1482
1483 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1484 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1485 if (slots == 0)
1486 return -ENODEV;
1487
1488 BUG_ON(slots > MAX_SLOTS);
1489
1490 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1491 if (ret)
1492 return ret;
1493
1494 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1495
1496 if (first_bar > 5) {
1497 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1498 return -ENODEV;
1499 }
1500
1501 ret = pci_enable_device(pdev);
1502 if (ret)
1503 return ret;
1504
1505 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1506 if (!chip) {
1507 ret = -ENOMEM;
1508 goto err;
1509 }
1510
1511 chip->pdev = pdev;
1512 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1513 if (chip->fixes) {
1514 chip->quirks = chip->fixes->quirks;
1515 chip->quirks2 = chip->fixes->quirks2;
1516 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1517 }
1518 chip->num_slots = slots;
1519
1520 pci_set_drvdata(pdev, chip);
1521
1522 if (chip->fixes && chip->fixes->probe) {
1523 ret = chip->fixes->probe(chip);
1524 if (ret)
1525 goto free;
1526 }
1527
1528 slots = chip->num_slots; /* Quirk may have changed this */
1529
1530 for (i = 0; i < slots; i++) {
1531 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1532 if (IS_ERR(slot)) {
1533 for (i--; i >= 0; i--)
1534 sdhci_pci_remove_slot(chip->slots[i]);
1535 ret = PTR_ERR(slot);
1536 goto free;
1537 }
1538
1539 chip->slots[i] = slot;
1540 }
1541
1542 if (chip->allow_runtime_pm)
1543 sdhci_pci_runtime_pm_allow(&pdev->dev);
1544
1545 return 0;
1546
1547 free:
1548 pci_set_drvdata(pdev, NULL);
1549 kfree(chip);
1550
1551 err:
1552 pci_disable_device(pdev);
1553 return ret;
1554 }
1555
1556 static void sdhci_pci_remove(struct pci_dev *pdev)
1557 {
1558 int i;
1559 struct sdhci_pci_chip *chip;
1560
1561 chip = pci_get_drvdata(pdev);
1562
1563 if (chip) {
1564 if (chip->allow_runtime_pm)
1565 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1566
1567 for (i = 0; i < chip->num_slots; i++)
1568 sdhci_pci_remove_slot(chip->slots[i]);
1569
1570 pci_set_drvdata(pdev, NULL);
1571 kfree(chip);
1572 }
1573
1574 pci_disable_device(pdev);
1575 }
1576
1577 static struct pci_driver sdhci_driver = {
1578 .name = "sdhci-pci",
1579 .id_table = pci_ids,
1580 .probe = sdhci_pci_probe,
1581 .remove = sdhci_pci_remove,
1582 .driver = {
1583 .pm = &sdhci_pci_pm_ops
1584 },
1585 };
1586
1587 module_pci_driver(sdhci_driver);
1588
1589 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1590 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1591 MODULE_LICENSE("GPL");
Linux with added FPC-III support